KR890007855U - DM circuit for data transmission / reception integrated circuit - Google Patents

DM circuit for data transmission / reception integrated circuit

Info

Publication number
KR890007855U
KR890007855U KR2019870015033U KR870015033U KR890007855U KR 890007855 U KR890007855 U KR 890007855U KR 2019870015033 U KR2019870015033 U KR 2019870015033U KR 870015033 U KR870015033 U KR 870015033U KR 890007855 U KR890007855 U KR 890007855U
Authority
KR
South Korea
Prior art keywords
circuit
data transmission
reception integrated
integrated circuit
reception
Prior art date
Application number
KR2019870015033U
Other languages
Korean (ko)
Other versions
KR900003527Y1 (en
Inventor
주현오
민승기
Original Assignee
금성통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성통신 주식회사 filed Critical 금성통신 주식회사
Priority to KR2019870015033U priority Critical patent/KR900003527Y1/en
Publication of KR890007855U publication Critical patent/KR890007855U/en
Application granted granted Critical
Publication of KR900003527Y1 publication Critical patent/KR900003527Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
KR2019870015033U 1987-09-02 1987-09-02 Dma circuit for ic used in data transmission and receiving KR900003527Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019870015033U KR900003527Y1 (en) 1987-09-02 1987-09-02 Dma circuit for ic used in data transmission and receiving

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019870015033U KR900003527Y1 (en) 1987-09-02 1987-09-02 Dma circuit for ic used in data transmission and receiving

Publications (2)

Publication Number Publication Date
KR890007855U true KR890007855U (en) 1989-05-17
KR900003527Y1 KR900003527Y1 (en) 1990-04-28

Family

ID=19267394

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019870015033U KR900003527Y1 (en) 1987-09-02 1987-09-02 Dma circuit for ic used in data transmission and receiving

Country Status (1)

Country Link
KR (1) KR900003527Y1 (en)

Also Published As

Publication number Publication date
KR900003527Y1 (en) 1990-04-28

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Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
LAPS Lapse due to unpaid annual fee