KR890005490U - Compensation circuit for readability - Google Patents

Compensation circuit for readability

Info

Publication number
KR890005490U
KR890005490U KR2019870014723U KR870014723U KR890005490U KR 890005490 U KR890005490 U KR 890005490U KR 2019870014723 U KR2019870014723 U KR 2019870014723U KR 870014723 U KR870014723 U KR 870014723U KR 890005490 U KR890005490 U KR 890005490U
Authority
KR
South Korea
Prior art keywords
readability
compensation circuit
compensation
circuit
Prior art date
Application number
KR2019870014723U
Other languages
Korean (ko)
Other versions
KR910005588Y1 (en
Inventor
장정훈
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019870014723U priority Critical patent/KR910005588Y1/en
Publication of KR890005490U publication Critical patent/KR890005490U/en
Application granted granted Critical
Publication of KR910005588Y1 publication Critical patent/KR910005588Y1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
    • G11B5/09—Digital recording
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
KR2019870014723U 1987-08-31 1987-08-31 Compensation circuit for read-proof KR910005588Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019870014723U KR910005588Y1 (en) 1987-08-31 1987-08-31 Compensation circuit for read-proof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019870014723U KR910005588Y1 (en) 1987-08-31 1987-08-31 Compensation circuit for read-proof

Publications (2)

Publication Number Publication Date
KR890005490U true KR890005490U (en) 1989-04-20
KR910005588Y1 KR910005588Y1 (en) 1991-07-27

Family

ID=19267194

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019870014723U KR910005588Y1 (en) 1987-08-31 1987-08-31 Compensation circuit for read-proof

Country Status (1)

Country Link
KR (1) KR910005588Y1 (en)

Also Published As

Publication number Publication date
KR910005588Y1 (en) 1991-07-27

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19970624

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee