KR890005372B1 - Automatic minuite control circuits of frequency synthesiser system - Google Patents

Abstract

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Description

Frequency synthesizer type automatic fine tuning circuit

1 is an overall circuit diagram of the present invention.

2 is a circuit diagram of the present invention.

3 is a waveform diagram of each part of the circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

8: sink separation unit 9: sink detection unit

6: phase comparator CT ₂ , CT ₂ , CT ₃ : counter

CPA, CPB: Comparator RT ₃ ,: Latch

FA, FB: Flip-flop IA, IB, IC: Inverter

NA, NB: NANDGATE OR: OAGATE

AN: AND gate RES ₁ , RES ₂ : Reset signal

The present invention relates to an automatic fine tuning (AFT) circuit of a frequency synthesizer method.

The frequency synthesizer method is widely used in adjusting televisions because it synthesizes frequencies and tunes a desired channel, and the remote control television detects an AFT S curve to prevent local oscillation frequency fluctuations.

However, such automatic fine tuning function can always detect the frequency fluctuation only within the set AFT range, so that a weak signal component outside the automatic fine tuning range cannot be precisely tuned.

SUMMARY OF THE INVENTION An object of the present invention is to provide a television circuit capable of tuning according to the amount of noise by detecting a horizontal synchronization signal of a video signal and tuning the amount of noise generated at the time of tuning out of the automatic fine adjustment range. In the tuning circuit where the output of the programmable counter and the output of the counter are compared in the phase comparator to adjust the frequency of the local oscillator, and the controller is controlled by the output of the video detector, the sink isolating the sync signal of the video signal. The negative synchronization signal is applied to the sink detector to detect the amount of noise so that the division ratio of the controller is determined.

This will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a sink separator 8 and a sink detector 9 shown in dotted lines in a circuit of a frequency synthesizer system which is generally used as an overall circuit diagram of the present invention.

First, a general frequency synthesizer method is described.

분주시킨 카운터(10)의 기준 주파수와 비교시켜 그 차 성분만큼 출력시킨다.Once the desired broadcast channel is tuned, the AFT S-curve of the video detector 3 is detected by the comparator 4 and applied to the controller 5 so that the controller 5 generates a state signal of the division ratio corresponding to the frequency. The 1 / N divided state signal is applied to the programmable counter 7 to the phase comparator 6 so that the oscillation frequency of the oscillator 11 is adjusted in the phase comparator 6.

The reference frequency of the divided counter 10 is compared and output by the difference component.

The output of the phase comparator 12 which compares the frequency of the programmable counter 7 and the reference frequency of the counter 10 is applied to one terminal (-) of the comparator CP ₁ so that the reference voltage of the other terminal (+) ( Vref) is applied to the local oscillator 2 via a low pass filter 12 formed of a resistor R ₂ and a capacitor C ₂ .

Therefore, in the local oscillator 2, the local oscillation frequency changes according to the voltage applied from the low pass filter 12, and the local oscillation frequency is repeatedly applied to the programmable counter 7 through the prescale 1. Therefore, the oscillation frequency of the local oscillator 2 is determined. Accordingly, the broadcast signal applied through the RF amplifier RF is converted into the IF signal by the local oscillation frequency in the mixer MIX, and then through the IF amplifier IF. It is applied to the video detector (3).

Therefore, when the AFT S is actually present within the tuning range of the curve, the image carrier frequency of the RF actually input is detected by the comparator 4 and input to the controller 5, thereby changing the division ratio of the programmable counter 7. This function is the same as that of the conventional frequency synthesizer automatic fine tuning, but as described above, when the AFT S-curve range is out of the automatic fine tuning tuning range, There was a loss of AFT functionality.

According to the present invention, when the AFT S-curve range is out of the automatic fine tuning tuning range, the sync separation unit 8 separates a noise signal together with a synchronization signal (called a sink), and the sync detector 9 By detecting the number of noises and changing the division ratio of the controller 5 according to the amount of noise, tuning is possible even when out of the tuning range. The detailed configuration of the sink detector 9 is shown in FIG.

That is, the output signal SN of the sync signal and the noise signal separated by the sink separator 8 are clock terminals of the binary counter CT ₁ (CT ₂ ) through the comparator CPA CPB in which the reference voltage is set. It was configured to be applied to (CK) and each of the binary counter (CT ₁₎ an output terminal (Q ₂₎ (Q ₂₎ of the (CT ₂₎ is connected to the NAND gate (NA) (NB) binary counter (CT ₁ The output of each binary counter CT ₁ (CT ₂ ) is applied to the enable terminal EN of (CT ₂ ) and simultaneously applied to the OR gate (OR) through the inverter (IA) (IB). The reset terminal R of the flip-flop FA FB is connected to the terminal Q ₁ .

The reset signal RES ₁ is configured to be applied to the clock terminal CK of the flip-flop FA (FB) through the inverter IC so that the power supply B ⁺ is applied to the input terminal D. The output of (FA) (FB) is configured to be applied to one terminal of the AND gate (AN) through the oragate (OR).

In addition, the reset signal RES ₁ is applied to the other terminal of the AND gate AN so that the output of the AND gate AN is applied to the seven stage counter CT ₃ clock terminal CK to be counted. The count value of the seven-stage counter CT ₃ is applied to the controller 5 through the seven-stage latch RT ₃ to change the division ratio.

At this time, the reset signal RES ₁ is configured to be applied once when the horizontal synchronization signal passes two times, and the reset signal RES ₂ is configured to be supplied as a vertical synchronization signal.

The present invention configured as described above is to detect the number of the synchronization signal and the noise when out of the automatic fine tuning tuning range to apply to the controller (5) to change the division ratio of the video controller (3) The output SN of the sink separating unit 8 that separates the sync signal among the output video signals of the VCR is input to the comparator CPA CPB at 5V _PP, and the comparator CPA has a noise component equal to or greater than + 4V of the reference arm. The oversink component is detected and applied to the binary counter CT ₂ , and the comparator CPB detects a noise component and a sink component equal to or more than a reference voltage of +1 V and supplies it to the binary counter CT ₂ .

(See CPA, CPB in Figure 3)

In other words, the sink separation section 8 applies the output SN, which is the separation of the synchronous signal and the noise signal, from the video signal to the comparator CPA CPB (see SN of FIG. 3). Comparator CPA (CPB) In the present invention, the noise component and the sync signal component are detected at the threshold levels of 4V and 1V, and are applied to the clock terminal CK of the binary counter CT ₁ (CT ₂ ).

(See CPA, CPB in Figure 3)

And is used as a clock signal of the counter (CT ₁₎ outputs a binary comparator (CPA) The binary counter by (CT ₁₎ a reset terminal (R) after a reset is applied to the reset signal, the counter At this time, the enable terminal EN of the binary counter CT ₁ is reset so that the counter CT ₁ is reset so that the output terminals Q ₁ and Q ₂ are all at the low level. Will be applied at the level.

In addition, the period of the reset signal RES ₁ is generated once every two times of the synchronization signal, and is generated based on almost 1/2 times.If no noise is included, it is reset once and counts until the next reset. This will be counted twice, but when the noise is included (by sync signal) more counting will be generated by the noise.

For example, when the counting number of the noise and synchronization signal is 3, the output terminal Q ₁ of the binary counter CT ₁ is at the "H" level, and the output terminal Q ₂ is also at the "H" level. The output of (NA) becomes "L", the output of NAND gate (NA) becomes "L", and the "L" level status signal is applied to the enable terminal (EN) of the binary counter (CT ₁ ) to perform counting. It stops and remains in this state until the next reset signal RES ₁ is applied.

When the output of the NAND gate NA reaches the "L" level, it is applied to one side of the AND gate AN through the ora gate OR as the "H" level state signal inverted by the inverter IA.

And written by giving a flip-flop (FA) is a reset signal (RES ₁₎ has started coming from and then to the reset signal (RES ₁₎ operating at a negative edge and until the first counting begins made "H" level state of This is a function of applying a countered output to the oragate OR when no counting is performed at the output terminal Q ₁ of the binary counter CT ₁ , that is, when a signal weaker than the reference voltage (+ 4V) is applied. The binary counter CT ₂ and the flip-flop FB, which are driven by the output of the comparator CPB, also perform the same functions.

Therefore, when any one of the output signal of the binary counter CT ₁ and the flip-flop FA or the output signal of the binary counter CT ₂ and the flip-flop FB becomes “H” level, When the output is in the "H" level state and is applied to the AND gate AN, and the reset signal RES ₁ is applied to the AND gate AN, the clock signal is applied to the seven stage counter CT ₃ to count. do.

That is, one number of noise information is inputted (see FIG. 3). This counting is performed until a reset signal RES ₂ , which is a vertical synchronization signal, is applied, and this counting is performed at the beginning of the reset signal RES ₁ . In the reset, the number of reset signals RES ₁ in which noise occurs in the next reset period is generated.

7, the counter information of the stage counter (CT ₃₎ for performing such a counting is applied to a seven-stage latch (RT ₃₎ the moment the latching applied to the reset signal (RES ₂₎ is a 7-stage latch (RT _3), controller 5 in Will be.

Therefore, the controller 5 of FIG. 1 determines how much the tuning amount is to be changed according to the amount of noise applied from the seven stage latch RT ₃ , thereby changing the division ratio N of the programmable counter 7. The output of the phase comparator 6 changes according to the change of the division ratio as in the prior art, which changes the local oscillation frequency of the local oscillator 2 through the low pass filter 12, thereby adjusting the automatic fine tuning range tuning range. If you deviate, you can get accurate tuning.

As described above, in the present invention, the frequency fluctuation within the automatic fine tuning tuning range level detects an AFT S-curve and controls the local oscillator and controller as in the prior art, so that accurate tuning is performed and the automatic fine tuning tuning tuning level is adjusted. In the case of the deviation, the horizontal synchronization signal is detected and the amount of noise that is filtered along with the synchronization signal is measured and tuned so that accurate tuning can be performed at all times. There is an effect that can sufficiently compensate for the unstable video carrier frequency due to transmission instability of personal broadcast.

Claims (2)

The RF signal is mixed with the local oscillation frequency of the local oscillator 2 in the mixer MIX, converted into an IF signal, and configured to be detected as a video signal by the video detector 3 through an IF amplifier IF. Comparator 4 detects the AFT S-curve input of the section 3 to change the division ratio of the controller 5 so that the division signal of the programmable counter 7 is changed. The divided signal of 7) is compared with the reference frequency of the counter 10 in the phase comparator 6 and the difference signal output of the phase comparator 6 is the local oscillation frequency of the local oscillator 2 through the low pass filter 12. In the automatic fine adjustment circuit for tuning and tuning, a sync separator (8) for separating the sync signal of the video signal detected by the video detector (3), and a sync signal in the sync separator (8). Counts and detects noise signal separated with A sync detector 8 to detect the noise signal separated by the sync signal from the sink separator 8, and a sync detector 9 to separate the sync signal, and counting the sync detector 9 A frequency synthesizer type automatic fine tuning circuit composed of a controller (5) which changes the division ratio according to the amount of noise. 2. The sync detector 9 detects the synchronization signal and the noise signal of the sink separator 8 so that the sync detector 9 is applied as a clock signal of the binary counter CT ₁ and CT ₂ , and the binary counter ( The output of CT ₁ ) (CT ₂ ) is applied to NAND KATE (NA) (NB) and flip-flop (FA) (FB) and the output of NAND gate (NA) (NB) and flip-flop (FA) (FB) the Iowa gate count signal of the reset signal (RES ₁₎ has seven stage counter (CT ₃₎ hanhu be applied to the clock signal of the 7 stage counter (CT ₃₎ via the AND gate (aN) which is applied after through the (OR) Is a frequency synthesizer type automatic fine tuning circuit configured to apply the reset signal RES ₂ to the controller 5 through a 7 stage latch RT ₃ applied as a clock signal.

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