KR890003769B1 - Television channel integril circuit - Google Patents

Abstract

The high-low type IC for tuning the television channel with horizontal synchronous signal and the BFT signal comprises a phase inverter (1), a low pass filter (2) for removing the high frequency noise, a synchronous signal separator (3), the first comparator (4) for comparing the output of (3) with and the refernce signal, the second comparator (5) for comparing the FBT signal with the reference signal, a constant voltage generator (6), a phase compensator (7) for compensating the output phase of (5), synchronous discriminator (8) for selecting the tuninfg signal, and a high (9) and a low (10) rectifiers for detecting the desired level frequency.

Description

TV broadcasting station integrated circuit

1 is a block diagram of an integrated circuit according to the present invention.

2 is a detailed circuit diagram of the block diagram of FIG. 1 according to the present invention;

3 is a waveform diagram of each part of FIG. 2 according to the present invention;

* Explanation of symbols for main parts of the drawings

1: phase inversion circuit 2: low frequency filter

3: synchronous separation circuit 3 'constant current generating circuit

4: first comparator 5: second comparator

6: constant current generating circuit 7: phase compensation circuit

8: Sync selection circuit 9: High detection output circuit

10: low detection output circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuned integrated circuit that distinguishes the presence or absence of television broadcasts, and more particularly, to an integrated circuit that inputs and tunes only composite video signals F, B, and T signals.

In general, the digital receiver uses a digital tuning system to change channels automatically and to distinguish channels from which broadcasts are made. The tuning signal should be input from outside.

Conventional tuning signal generation circuits mainly use inverter circuits, capacitor layers, and time constant circuits using discharges. However, in such circuits, when the tuning signal output malfunctions due to the configuration of the circuit, a change in signal occurs. There is a lot of, and in order to reduce such malfunctions, it is necessary to increase the tuning time, which gave users a tedious inconvenience.

In addition, in case of a television receiver using a horizontal synchronous signal and a circuit which is not output to the outside because a horizontal synchronous signal is necessarily used as an input signal, a separate synchronous separation circuit is required, and each set is inputted to a central processing unit (CPU). Control pulses, that is, detection output circuits for tuning, are either high or low, depending on the nature of the set. Therefore, conventional circuits are complicated by the integration of only the low type, which limits the usability of the set. As the number of processes increased, product prices also increased.

Accordingly, an object of the present invention is to provide a high and low type tuning integrated circuit capable of tuning within a short time by inputting the horizontal synchronization signal and the F, B, and T signals.

Still another object of the present invention is to provide a pre-tuned integrated circuit capable of compensating the phase difference between the horizontal synchronization signal and the F, B, and T signals.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a block diagram of a tuning circuit according to the present invention, a phase inversion circuit 1, a low frequency filter 2, a synchronous separation circuit 3, a constant current generating circuit 3 ', a first comparator 4, a second A comparator 5, a constant current generating circuit 6, a phase compensating circuit 7, a synchronous selection circuit 8, a high detection output circuit 9, and a low detection output circuit 10 are constituted.

In the figure, I _a is a composite video signal input terminal, T _i is an F, B, T signal input terminal, and O _t is a tuning signal output terminal.

The reverse composite video signal generated by the normal composite video signal output from the normal television receiver to the phase inverting circuit 1 removes the unnecessary high frequency video signal from the low frequency filter 2, and inputs the synchronization separating circuit 3 to the input. to get separated synchronizing signal is applied to the first comparator (4) compared to a reference voltage, and forward the composite video signal (I _a) and is F, B, T signal (T _i) is with the second comparator ( 5) is applied to the constant current generating circuit 6 together with the output signal of the first comparator 4 and then operated. At the same time, a constant current is generated whenever the constant current generating circuit 6 is operated and synchronized.

This current signal is compensated in the same manner as the phases of the F, B, and T signals coming from the phase compensating circuit 7 to the synchronous signal selection circuit 8 through the second comparator 5, and this signal is converted into the F, B, and T signals. A sampling signal is output from the synchronization signal line separate circuit 8 by distinguishing it from the synchronous noise signal in the broadcast-free channel, and the output tuning signal is output to the high detection output circuit 9 and the low detection output circuit 10. When applied and switched, it is input to a central processing unit (CPU) (not shown) and used as a signal source for function of channel tuning and AFC control.

The detailed circuit diagram of the present invention configured as described above is shown in FIG.

The phase inversion circuit 1 of the block diagram of FIG. 1 described above corresponds to the transistors Q ₁ -Q ₆ , the resistors R ₁ -R ₉ , and the diode D _{1 of} FIG. 2, and the low frequency filter 2 is a resistor. Corresponding to (R ₈ ) and condenser (C ₁ ), the synchronous separation circuit (3) includes transistors (Q ₇ -Q ₁₀ ) and resistors (R ₁₀ -R ₁₅ ), capacitors (C ₂ , C ₃ ) and zener diodes. QD ₁ , diodes D ₂ -D ₄ , and the first comparator 4 includes transistors Q ₁₄ , Q ₁₅ , Q ₁₅ , zener diodes QD ₂ , and resistors R ₁₄ , R _20. The second comparator 5 corresponds to the transistors Q ₁₂ and Q ₁₃ and the resistors R _{17 to} R ₁₉ , and the constant current generating circuit 6 corresponds to the transistors Q ₁₁ and Q ₁₆ . Corresponding to R ₁₆ and R ₁₆ , the phase compensating circuit 7 corresponds to a resistor R ₂₁ and a capacitor C ₄ , and the synchronous selection circuit 8 corresponds to a transistor Q ₁₇ -Q ₂₂ and a resistor ( R ₂₃ -R _27, R ₃₁₎ and a diode (D _5, D ₆₎ and corresponding to the high-output detection circuit 9 includes transistors (Q _23, Q ₂₄₎ and a resistor (R ₂₈ -R ₃₀₎ and a die De corresponding to (D _7), and a low detection output circuit 10 corresponds to the transistor (Q ₂₅₎ and a resistor (R _32).

Therefore, the high and low of the tuning signal indicated by the emitter of the transistor Q ₂₄ and the collector of the transistor Q ₂₅ are applied to the CPU.

3 (a) to 3 (k) are waveform diagrams of the respective parts of the detailed circuit diagram of FIG. 2 according to the present invention, in which time T ₁ is the original horizontal synchronizing period, and time T ₁ is phase corrected. The synchronization signal period, time T _3, is a time delayed by phase correction, and time T ₄ is a sampling period by comparing the F, B, T signals with the base voltage j of the transistor Q ₁₃ . Hereinafter, FIG. 2, which is a specific circuit diagram of the present invention, will be described in detail with reference to the waveform diagrams of FIGS. 3 (a) and 3 (k).

FIG. 3 (a) shows a horizontal synchronization signal P, a brightness signal q, a chroma signal r, and a color burst signal s as forward composite video signals.

When the forward composite video signal a as shown in FIG. 3 (a) is input to the input terminal l _a of the phase inversion dilution (1), the signal of the in phase with the forward synthesized video signal is output to the ether of the transistor Q ₁ so that the base of the transistor is output. The reverse composite video signal b reversed on the collector of this transistor Q ₂ appears at point B which is an emitter of the buffer transistors Q ₃ and Q ₄ as shown in FIG. 3 (b).

On the other hand, the circuit composed of transistors Q ₅ and Q ₆ is a constant current source that drives the Burr transistors Q ₃ and Q ₄ as constant current circuits. In the reverse composite video signal as shown in the third (b), the high frequency signal included in the video signal is removed through the low frequency filter 2 composed of the resistor R ₈ and the capacitor C ₁ , and is input to the synchronous separation circuit 3. do. The diode of the _double coupling capacitor C ₂ and the transistor Q ₇ constitutes the clamping circuit and the constant current circuit together with the transistor Q ₈ .

Then, the capacitor C is the output terminal of clamping circuit consisting of the transistor Q ₂ is C ₇ to be a constant clamping voltage of about 0.7 volts consists of a capacitor C ₂ and the transistor Q _7.

Accordingly, the backward composite video signal as shown in FIG. 3 (b) is clamped by the clamping voltage d as shown in FIG. 3 (c) to appear at the point of FIG. 2, and the clamped video signal c as shown in FIG. ) appears, the base voltage of the transistor Q _8.

의 베이스 에미터간 도통전압이 0.3볼트이므로 제3(c)도의 0.3볼트와 0.7볼트사이에 있는 수평동기신호기간 T₁동안만 트랜지스터 Q₈의 콜렉터에 전류가 흐르게 된다.Thus, transistor Q

Since the conduction voltage between the base emitters is 0.3 volts, current flows to the collector of transistor Q ₈ only during the horizontal synchronous signal period T ₁ between 0.3 volts and 0.7 volts in FIG.

Accordingly, the constant current generating circuit 3 'composed of transistors Q ₉ and Q ₁₀ is a current repeater, and current flows only in the period of the horizontal synchronization period T _{1 to} the transistor Q ₁₀ collector. by the collector synchronous current signal (e) of _10, the phase compensation capacitor C ₃ has been presented the charge during the period T _1, so during the period other than that to be discharged through the resistor R ₁₃ of the transistor Q ₁₄ base, third ( As shown in d), the base synchronous voltage signal f of the phase-compensated transistor Q ₁₄ appears.

On the other hand, is applied to the transistor Q ₁₅ base has a resistance R _17, R _18, certain transistor Q ₁₅ base comparison voltage (g) as installing the voltage dividing circuit consisting of R ₁₉ to the transistor Q ₁₅ base help claim 3 (d) do.

Accordingly, the transistors Q ₁₄ and a differential amplifier consisting of Q ₁₅ is the 3 (d) separate the transistor Q ₁₄ of the base input voltage of the phase compensation transistor Q ₁₄ base synchronization voltage signal (f) and the base input voltage of the transistor Q ₁₅ By the comparison of the comparison voltage g, the collector voltage of the transistor Q ₁₄ becomes zero volts in the phase-corrected synchronization signal period T ₂ , as shown in FIG. 3 (e), and the delayed time T ₃ is caused by the phase correction.

However, the delay time T ₃ and the phase-corrected synchronization signal period T ₂ can be changed by adjusting the capacitance value of the capacitor C ₃ connected to the external terminal of the channel integrated circuit according to the present invention. In this case, it is possible to engage T ₄ , the synchronization signal sampling period based on the T signal comparison.

On the other hand, the F, B, and T signals are signals generated by a conventional television receiver and have a wider pulse width than the horizontal synchronization signal. The F, B, T signals F, B, is input to the T ₁ of T signal input terminal is applied to the transistor Q ₁₂ via the resistor R _12, transistor Q ₁₃ base has a resistance R ₁₇ Q and R of _18, R ₁₉ The divided voltage divided by is applied.

In addition, a circuit composed of zener diodes QD ₁ and diodes D ₂ -D ₄ serves to determine the D, C offsets of the F, B, and T input signals.

No. 3 (f) turning a view showing the comparison voltage (g) in this way is applied to the base of the transistor Q ₁₂ F, B, T signal (i) the transistor Q ₁₃ of the base to be.

Therefore, when the collector voltage of the transistor Q ₁₂ and the transistor Q ₁₂ of the comparison circuit ₁₃ consisting of Q are assumed to be in the conductive and the transistor Q ₁₄ is displayed as the help 3 (g).

Therefore, as described above, the phase-corrected sync signal time T ₃ is adjusted by adjusting the capacitance value of the capacitor C ₃ to be connected to the outside, and the sync signal sampling time T is compared by F, B, and T signal in Fig. 3 (g). It enables you to cheolchi and ₄ and, thus, by the transistors it is possible to flow a collector current flowing through the transistor Q ₁₆ of the current committer consisting of Q ₁₁ and Q ₁₆ in the up new books.

Therefore, the synchronization signal sampling time which is held a horizontal synchronizing T ₄ during the transistor Q ₁₆ and the transistor to the collector, the voltage drop caused by the resistor R ₂₁ by the current flow for a time sufficient Q ₁₇ is the "on" state, the transistor Q ₁₈ , Q ₂₀ , Q ₂₁ and Q ₂₂ are turned off so that there are no output signals at the output terminals OTL and OTH.

However, when there is no horizontal synchronous signal, since no current flows in the collector of transistor Q ₁₆ , transistor Q ₁₇ is in the "off" state, and transistors Q ₁₈ , Q ₂₀ , Q ₂₁ and Q ₂₂ are in the "on" state. The output voltage signal of the channel selection function of the low and high channel is output to the output terminals OTL and OTH.

On the other hand, when the noise signal 1 as shown in FIG. 3 (h) is input to the transistor Q ₁ base, the transistor-based synchronous noise signal m as shown in FIG. 3 (i) is output, and the collector noise current signal of the transistor Q ₁₄ is As shown in FIG. 3 (j), the noise output current of the collector of transistor Q ₁₆ becomes as shown in FIG. 3 (k).

Therefore, the current output period when the video signal is proportional to T ₂ is proportional to the noise output current O output to the transistor Q ₁₆ collector by the same noise signal as the noise signal 1, so that the resistance R ₂₁ and the capacitor are relatively high. The difference in the integral voltage output of the integrating circuit composed of C ₄ increases, so that the variation of the transistor Q ₁₇ and the base voltage in broadcasting and non-broadcasting becomes much larger, and therefore the accuracy of tuning is further increased.

Second degree circuit of transistor QD _1, QD ₂ is an integrated circuit there is to operate in a zener diode of about 7.5 volts, which therefore is several orders of magnitude of the horizontal synchronizing period, vertical synchronizing period, the capacitor C ₃ is charged sufficiently the transistors QD _2, the base voltage This is to prevent the abnormal rise.

Thus, the second intermediate resistor R ₁₃ , R ₂₁ is the external resistance of the integrated circuit, and all capacitors C _1- c ₄ are also external connection capacitors.

Therefore, when the line detection output signal is of low type, the channel selection is made low when the video signal and the F, B, and T signals are all output. This high state is maintained. In addition, when the station detection output signal is a high type, the operation opposite to the above case is performed.

As described above, according to the present invention, by providing a phase compensation function, the noise margin can be improved, and the high or low detection output can be easily used selectively according to the type of the CPU (central processing unit) on the SET. Of course, it is possible to accurately tune, and even in a television receiver in which only the horizontal synchronization signal is not output to the outside, there is an advantage that stable and fast tuning is possible by a simple integrated circuit (IC) without a separate synchronous separation circuit.

Claims (2)

A broadcasting channel integrated circuit of a television receiver, comprising: a phase inversion circuit (1) for inputting a forward video signal to invert a phase, a low frequency filter (2) for removing high frequency noise of the inverted video signal, and noise A synchronous separation circuit (3) for separating synchronization from the video signal, a constant current generation circuit (') for generating a constant current according to the synchronous separation signal, and the output signal of the synchronous separation circuit (3) are compared with each other. The constant current is generated by the first comparator 4, the second comparator 5 for comparing the input F, B, and T signals with the reference signal, and the output signals of the first comparator 4 and the second comparator 5. The output signals of the constant current generating circuit 6, the phase compensating circuit 7 for compensating the phase of the output signal of the second comparator 5, and the output signals of the above-described phase compensating circuit 7 are F, B, T signals. The synchronization selecting circuit 8 for detecting the tuning signal by sampling with the High detection output circuit 9 and a low detection output telrebijyon broadcast channel selection integrated circuit, characterized in that consisting of a circuit 10 for detecting a high frequency in the call. 2. The clamping circuit of claim 1, wherein the synchronous separation circuit 3 comprises a capacitor C ₂ and a transistor Q ₇ , and the transistor Q ₇ comprises a constant current circuit simultaneously with the transistor Q ₈ . TV broadcasting station integrated circuit.

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