KR890003031A - Semiconductor device - Google Patents

Abstract

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Description

Semiconductor devices

Since this is an open matter, no full text was included.

1 is a cross-sectional view of a semiconductor device having a conventional well type structure, and FIGS. 2A to 2C are views illustrating a manufacturing process of a semiconductor device having a well type structure according to an embodiment of the present invention. .

Claims (27)

The semiconductor substrate 301, the first well region P-well-1 of the first conductivity type (P type) formed in the semiconductor substrate 301, and the first well in the semiconductor substrate 301. The second well region P-well-2 which is formed separately from the region P-well-1 and whose impurity concentration on the surface thereof is set lower than that of the first well region P-well-1. ), A memory cell structure formed in the first well region P-well-1, and a second cell formed in the second well region P-well-2, and are combined with the structure of the memory cell. A semiconductor device comprising a transistor structure provided. The third well region (N-well-2) of the second insulated type (N-type) formed in the second well region (P-well-2) separately from the semiconductor substrate (301). PN junction between the third well region (N-well-2) and the second well region (P-well-2) or the second well region (P-well-2) and the semiconductor substrate. The PN junction between 301 is reverse biased by the potential difference between the semiconductor substrate 301 and the third well region N-well-2, whereby the third well region N-well-2 is different from the well region. And electrically separated from each other, wherein at least a portion of the transistor structure is formed in the third well region N-well-2. 3. The first conductive type (P type) of claim 2, wherein the semiconductor substrate 301 is formed separately from the first well region P-well-1 and the second well region P-well-2. The fourth well region P-well-3 is provided, and the impurity concentration P + of the fourth well region P-well-3 is the impurity of the first well region P-well-1. The semiconductor device is set lower than the concentration P ++, and a second transistor structure used in combination with the memory cell structure is formed in the fourth well region P-well-3. 4. The semiconductor substrate 301 of claim 3, wherein the fifth well region N-well-1 of the second conductivity type (N type) is formed separately from the first well region P-well-1. The second well region P-well-2 and the fourth well region P-well-3 are provided, and the third transistor structure used in combination with the memory cell structure is the fifth well region N. semiconductor device formed in well-1) The impurity concentration P + of the fourth well region P-well-3 is lower than the impurity concentration P ++ of the first well region P-well-1 and the second well region. A semiconductor device characterized by being set higher than the impurity concentration P of (P-well-2). The high concentration of the first conductivity type according to any one of claims 1 to 5, wherein the impurity of the second conductivity type (N-type) is injected into the high concentration impurity (P ++) region of the first conductivity type (P type). Semiconductor devices characterized by diffusion into an impurity (P ++) region The impurity concentration N of the third well region N-well-2 is set lower than the impurity concentration N + of the fifth well region N-well-1. Semiconductor device The potential (+4 V) different from the potential (+5 V) of the fraudulent semiconductor substrate 301 is defined by the third well region (N-well-1, N-well-2). And a voltage supply means for supplying it to the semiconductor device, wherein the semiconductor substrate 301 is of a second conductivity type (N type). 9. The method of claim 8, wherein at least one second conductivity type (N-type) well region (N-well-1, N-well-2) is formed in the second well region (P-well-2). And an independent potential is applied to each of the second conductivity type well regions. 9. The semiconductor device according to claim 8, wherein a potential (+ 5V) on the semiconductor substrate 301 is applied from an external power supply Ext. VCC of a semiconductor device, and the voltage supply means supplies an output potential of the external power supply Ext. VCC. A semiconductor device comprising a voltage converting circuit for converting to another potential (+ 4V) The well region of claim 10, wherein the power supply means is formed separately from the first well region P-well-1 and the second well region P-well-2 in the semiconductor substrate 301. N-well-1), characterized in that the semiconductor device The second conductive type (N-type) well region (N-well-2) according to any one of claims 1 to 5, which is formed separately from other well regions in the semiconductor substrate (301). 1, wherein the well region P-well-1 is formed 6. The MOS transistor unit according to any one of claims 1 to 5, wherein the memory cell structure is a DRAM structure and charges and discharges the memory cell capacitor units 311 and 312 and the memory capacitor units 311 and 312. Semiconductor devices comprising 308 and 313 The semiconductor device according to claim 13, wherein said memory cell capacitors (311, 312) have a metrological cell structure. The semiconductor device according to claim 13, wherein said memory cell capacitors (311, 312) have a stacked cell structure. 14. The semiconductor device according to claim 13, wherein said memory cell capacitors (311, 312) have a deposition weight cell structure. The semiconductor device according to claim 13, wherein said memory cell capacitors (311, 312) have a flat cell structure. The semiconductor device according to any one of claims 1 to 5, wherein the memory cell structure has an SRAM structure. The impurity concentration of the second well regions P-well-2 and 102-2, which is lower than the impurity concentration of the first well region P-well-1, is of a first conductivity type (P type). Semiconductor device obtained by doping and diffusing a second conductivity type (N-type) impurity into a second well region (P-well-2) of The impurity concentration of the fourth well region P-well-3 lower than the impurity concentration of the first well region P-well-1 has a first conductivity type (P type). Semiconductor device obtained by doping and diffusing impurities of a second conductivity type (N) into a fourth well region (P-well-3) of The impurity concentration of the first well region (P-well-1, 102-1) is higher than the impurity concentration of the second well region (P-well-2, 102-2). A semiconductor device obtained by doping and diffusing impurities of a first conductivity type (P type) into a first well region (P-well-1) of type (P type) The impurity concentration of the first well region (P-well-1, 102-1) is higher than that of the fourth well region (P-well-3). A semiconductor device obtained by doping and diffusing impurities of a first conductivity type (P type) into a first well region (P-well-1) of type (P type) The semiconductor substrates 101 and 301, memory cell well regions P ++ and P-well-1 of the first conductivity type (P type) formed in the semiconductor substrates 101 and 301, and the semiconductor substrates 101 and 301. 301 is formed separately from the memory cell well regions P ++ and P-well-1, and the impurity concentration P + on the surface thereof is impurity of the memory cell well regions P ++ and P-well-1. At least one peripheral circuit well area (P +, P-well-3) set lower than P ++, RAM memory cell formed in the memory cell well area (P ++, P-well-1), and And a MOS transistor structures formed in the peripheral circuit well regions P + and P-well-3 and operating in combination with the RAM memory cell structure. 24. The semiconductor device according to claim 23, wherein the impurity of the second conductivity type (N type) is doped and diffused into the high concentration impurity (P ++) of the first conductivity type (P type). One conductivity type (N type) semiconductor substrate 301, another conductivity type (P type) memory cell well region P-well-1 formed in the semiconductor substrate 301, and this memory cell well The DRAM memory cell structure formed in the area P-well-1 and the semiconductor cell 301 are formed separately from the memory cell well area P-well-1 and have an impurity concentration P +. The first peripheral circuit well region P-well-2 of another conductivity type (P type) that is set lower than the impurity concentration P ++ of the memory cell well region P-well-1, and the memory cell structure A conductive type (N-type) internal well region (N-well-2) formed in the first peripheral circuit well region (P-well-2) to provide a first MOS transistor structure to be used in combination; The memory cell well region within the semiconductor substrate 301 to provide a second MOS transistor structure used in combination with the memory cell structure. The second peripheral circuit well region P, which is formed separately from P-well-1, and whose impurity concentration P + is set lower than the impurity concentration P ++ of the memory cell well region P-well-1, is set. -well-3) and separated from the memory cell well region P-well-1 in the semiconductor substrate 301 to provide a third MOS transistor structure to be used in combination with the memory cell structure. And a third peripheral circuit well region N-well-1, etc. The semiconductor substrate 301 of one conductivity type (N type), the first memory cell well region P-well-2 of another conductivity type (P type) formed in the semiconductor substrate 301, and One conductivity type (N-type) second memory cell well region (N-well-1) formed in one memory cell well region (P-well-2), and this second memory cell well region (N-well-). 1) a DRAM mesocell structure formed in the semiconductor substrate 301, which is formed separately from the first memory cell well region N-well-2 and whose impurity concentration N is formed in the second memory. As long as the impurity concentration (N ++) of the cell well region (N-well-1) is set lower than that of the first peripheral circuit well region (N-well-2) of the conductivity type (N type), the memory cell structure Another conductivity type (P type) internal well region (P-well-1) formed in the first peripheral circuit well region (N-well-2) to provide a first MOS transistor structure to be used, the memory Cell structure The impurity concentration (N +) is formed in the semiconductor substrate (301) separately from the first memory cell well region (P-well-2) in order to provide a second MOS transistor structure used in combination with A second peripheral circuit well region N-well-3, which is set lower than an impurity concentration N ++ of the second memory cell well region N-well-1, and a third used in combination with the memory cell structure; In order to provide a MOS transistor structure, a third peripheral circuit well region P-well-1 formed in the semiconductor substrate 301 is formed separately from the first memory cell well region P-well-2. Semiconductor device characterized in that provided One conductivity type (N type) semiconductor substrate 301, another conductivity type (P type) memory cell well region P-well-1 formed in the semiconductor substrate 301, and this memory cell well The DRAM memory cell structure formed in the regions P ++ and P-well-1, and is formed separately from the memory cell well region P-well-1 in the semiconductor substrate 301 and its impurity concentration (P +). ) Is the first peripheral circuit well region (P-well-2) of another conductivity type (P type) in which the impurity concentration (P ++) of the memory cell well region (P-well-1) is set lower than the memory cell well region (P-well-1). A conductive type (N-type) internal well region (N-well-2) formed in the first peripheral circuit well region (P-well-2) to provide a first MOS transistor structure used in combination with the structure. And the memory cell right in the semiconductor substrate 301 to provide a second MOS transistor structure used in combination with the memory cell structure. Impurity concentration of the inner well region N-well-2, which is formed separately from the region P-well-1, and whose impurity concentration is formed in the first peripheral circuit well region P-well-2. And a second peripheral circuit well region (N-well-1) set higher. ※ Note: The disclosure is based on the initial application.