KR890002325B1 - Cd-rom controling circuit - Google Patents

Abstract

The circuit interfaces the CD-ROM Driver and one or more computers. The circuit has the selecting function of the driver from the multi- driver system for processing the extra large data. The circuit comprises the 1st and 2nd gate circuits (300a, 300b) generating the function and the control signals by accepting the input output of an unit (200), an output unit (400) selecting the CD-ROM, an I/O buffer circuit (600) writing the function or instruction data for the data transmission direction, and a CD-ROM driver.

Description

CD-ROM Driver Interfacing Control Circuit

1 is a block diagram according to the present invention.

2 is a circuit diagram showing in detail the block diagram of FIG.

3 is a waveform diagram according to the present invention.

4 is a flow chart according to the present invention.

* Explanation of symbols for main parts of the drawings

100: main computer I / O channel portion 200: input portion

300a, 300b: first and second gate circuit 400: output unit

500: CD-ROM Driver 600: Buffer Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an auxiliary storage device for use in a computer system, and more particularly, to interfacing a CD-ROM driver to easily interface a compact disc (ROM) -ROM (read only memory) driver with a general-purpose personal computer. (Interfacing) control circuit.

In general, various types of auxiliary storage devices for personal computers are used. However, disk-type storage devices are referred to as floppy disk drivers (hereinafter referred to as "FDD") and hard disk drivers ("Hard Disk Driver"). HDD ") predominantly. FDD is an important peripheral of computer in that it has faster processing speed and smaller size than the reel tape using magnetic tape used in the large computer, and it is not only inexpensive but also has a large memory capacity and random access. It has been widely used as. The diskette surface, which is a recording medium in FDD, is coated with iron oxide (r-FeO5), which is a recording magnetic material, and wears out when reading and writing information by a driver head. An error occurs when the number of times of reading and writing is exceeded. This gets worse. In addition, although non-woven lines are made to remove the fine powder caused by antistatic and dust or abrasion, recorded data is often broken due to inadequate handling and storage. In addition, since the recording capacities of the inner and outer tracks of the disc are the same, a difference in recording density occurs and the disc cannot be used efficiently. In other words, because of the low stability and reliability, and the limitation of capacity, the diskettes should be used frequently in exchange. The HDD writes and reads information on the surface of the disk by magnetic iron made of MnZn ferrite, which is a magnetic material made by coating magnetic iron oxide on the surface of the disk and alloying manganese (Mn) and zinc (Zn) at a predetermined ratio. It is. In the HDD, when the head and the disk body are fixed as one and the structure is sealed from the outside air and the disk is stopped, the head is in contact with a dedicated track called a shipping zome. The head floats due to the flow of air. At this time, the contact start / stop operation is performed to accurately determine the head position to record / read the information, so the accuracy and track density are high, and the damage of the head from dust can be reduced. HDDs can handle up to tens of megabytes (MB), even if they are small, but they are vulnerable to shock and vibration and require more attention when installed and moved. The reason is that it is faster than FDD, so it is necessary to pay attention to the design of the control logic circuit in order to prevent the disk surface from becoming thick when starting / stopping, especially when the head comes in contact with the disk surface. And the inconvenience of having to back up the information of alternative sectors and the limitation of capacity which cannot meet user's expectations due to the increase of information volume, it is not economical system and disk itself Complex designs are required to be installed precisely within the main parts of the system. In recent years, when a compact disc that is applied to an audio system is used as an auxiliary memory device of a personal computer, it is called a CD-ROM. It is easy to manage disks and configures a large number of disk drivers in one computer. It can scale up to tens of times larger capacity than HDD, 540MB, and high accuracy because it can process data and detect errors by optical system. Since the surface of the compact disc is formed of a protective film made of plastic, there is no damage caused by dust or dirt, so there is no error in reading, and there is no damage to the stored information unless the disc is damaged. However, there is no suitable circuit for interfacing a CD drive driver with a computer.

Accordingly, an object of the present invention is to provide an interface circuit which can easily connect a compact disc (hereinafter referred to as "CD") driver to a computer.

Another object of the present invention is to provide a circuit capable of constructing an economical system that can be used by a plurality of computers because it can be directly interfaced without changing the conventional bus method.

It is still another object of the present invention to provide a circuit in which a driver can be easily selected in a large number of disk driver configurations and thus data processing of ultra large capacity is possible.

It is still another object of the present invention to provide a circuit which is easy to apply system software and can form a high-performance computer network that can be used in a database.

Accordingly, the present invention provides a main computer I / O (Im / Out) channel portion connected to a predetermined portion of an expansion slot of an input / output (hereinafter referred to as I / O) channel of a main computer, and the main An input unit that receives and buffers command signals of each function of the main computer only through a specific address through an input / output port of the computer I / O channel unit, and between the main computer and the CD-ROM by a signal output from the input unit. Outputs a signal for setting the data transfer direction on the data bus, and accesses the first and second gate circuits generating control logic signals according to each command and function, and the outputs of the first gate circuits. The driver selects the driver and accepts the data and status enable signals. The command write and the function are selected according to the output of the second gate circuit. An output unit for setting a address and outputting a direction setting signal of the data flow, a buffer circuit for determining the direction of data flow by the first and second gate circuits and the output unit, and an input / output terminal of the output unit and the buffer circuit And a CD-ROM driver input / output section connected to the CD-ROM driver.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram according to the present invention, in which a main computer I / O channel unit 100 having a predetermined channel so as to use a CD-ROM by allocating an unused port on the main computer I / O port side, The input unit 200 receives and receives the command signal of the main computer according to each command and function from the main computer I / O channel unit 100, and the output signal of the input unit 200 is logicalized to process and command the function. Function to select the CD-ROM to be used by the first and second gate circuits 300a and 300b generating the control signal and the output signals of the first and second gate circuits 300a and 300b and to read data contained in the disk. And an output unit 400 for writing a command data, outputting a signal for setting a direction so that the data read from the disk is transmitted to the main computer, and generating a read and status enable signal of the data; To the output signal of the output unit 400 The direction of the data flow is determined by the buffer circuit 600 for transferring data between the main computer I / O channel unit 100 and the CD-ROM, and is controlled by the output signal of the output unit 400. It consists of a CD-ROM driver 500 for inputting and outputting data to the CD-ROM through (400).

According to the exemplary embodiment of the present invention, the command signal and the function signal for driving the CD-ROM driver 500 through a predetermined channel address among the various interface channels of the main computer I / O channel unit 100 will be described. When is input to the input unit 200 is buffered in the input unit 200, a logic signal is generated to drive the CD-ROM driver 500 in the first and second gate circuit (300a, 300b), the first gate circuit ( 300a selects one CD-ROM from a CD-ROM driver 500 that can connect four CD-ROM devices to the output unit 400. The output unit 400 outputs a signal for setting the direction of data flow between the main computer and the CD-ROM driver 500, and generates an enable signal according to data read from the CD-ROM driver 500. When the read is completed, the status signal of the CD-ROM driver 500 is enabled. The second gate circuit 300b generates an enable signal so that the direction of the data flow is active, and inputs a command signal and data for designating a data read area in the selected CD-ROM driver 500. At this time, the read designated data is output to the main computer via the data bus.

; Address Enable)단이고, 제2,3입력단(20,30)은 어드레스(

; Address1, Address2)신호 입력단이며, 제4,5입력단(40,50)은 CD-ROM의 컴펙트디스크내 데이타 입출력을 리드/라이트하기 위한 명령신호(

; Input/Output Read/Write)입력단이다. 그리고 상기한 제1-5입력단(10-50)과 연결되고 데이타버스(DB0-DB7)로 도시된 부분이 제 1 도의 메인컴퓨터 I/O채널부(100)에 연결된다.2 is a detailed circuit diagram of FIG. 1 according to the present invention, in which BUF1-BUF3 is a buffer, AN1-AN2 is an AND gate, NA1-NA3 is a NAND gate, and OR1-OR3 is OR gate, LAT is latch, DB0-DB7 is data bus of main computer I / O channel part 100 side, D0-D7 is data bus of CD-ROM driver 500 side, The display of 10, 20, 30, 40, and 50 between the main computer I / O channel unit 100 and the buffer BUF1 in FIG. 2 shows a signal line connected to the main computer I / O channel unit 100 for convenience. And 2, 3, 4, and 5 input terminals, and 21, 22, 23, 24, and 25 between the CD-ROM driver 500 and the buffer BUF2 of FIG. 2 are connected to the CD-ROM driver 500 side. Signal lines are named as 6, 7, 8, 9, 10 input / output terminals for convenience, and 26, 27, 28, and 29 between the latch circuit LAT and the CD-ROM driver 500 of FIG. 2 are CD-ROM drivers. Named as the selection terminal of (500). The first input terminal 10 of the first, second, third, fourth, and fifth input terminals 10-50 of the connection lines of the main computer I / O channel unit 100 has an address enable (

; Address Enable), and the second and third input terminals 20 and 30 have an address (

; Address 1 and Address 2) signals are input terminals, and the fourth and fifth input terminals 40 and 50 are command signals for reading / writing data input / output in a compact disc of a CD-ROM.

; Input / Output Read / Write). The first and second input terminals 10-50 and the data buses DB0-DB7 are connected to the main computer I / O channel unit 100 of FIG. 1.

)와 독출신호가 입력부(200)의 버퍼(BUF1)를 지나 각각 반전되어 오아게이트(OR1)에 각각 입력되도록 연결되며, 상기 오아게이트(OR1)의 출력단에 반전게이트(N1)가 접속되고, 상기 제 4 입력단(40)을 통해 출력되는 독출신호가 버퍼(BUF1)를 통해 반전되어 앤드게이트(AN2)의 입력에 연결되며, 상기 제 5 입력단(50)을 통해 출력되는 명령신호가 버퍼(BUF1)를 통해 버퍼링되어 오아게이트(OR3)의 입력단에 연결된다. 어드레스신호의 제2,3입력단(20,30)이 버퍼(BUF1)를 통해 낸드게이트(NA3)의 입력에 연결되고, 낸드게이트(NA3)의 출력단이 반전게이트(N3)를 지나 앤드게이트(AN2)의 입력으로 반전되어 입력되도록 연결된다. 상기 낸드게이트(NA3)의 출력단과 반전게이트(N2)의 출력단이 오아게이트(OR2)의 입력단에 연결되고, 상기 오아게이트(OR2)의 출력단과 명령어 입력신호의 제 5 입력단(50)이 오아게이트(OR3)의 입력단에 연결되도록 접속한 부분이 제 1 도의 제 1 게이트회로(300a)이다.The first input unit 200 is a portion in which the first to fifth input terminals 10-50 of the main computer I / O channel unit 100 are connected to the input terminal of the buffer BUF1. Command for reading CD-ROM disk data output through the fourth and fifth input terminals 40 and 50 (

) And the read signal are inverted through the buffer BUF1 of the input unit 200 to be respectively input to the OR gate OR1, and an inverting gate N1 is connected to an output terminal of the OR gate OR1. The read signal output through the fourth input terminal 40 is inverted through the buffer BUF1 and connected to the input of the AND gate AN2, and the command signal output through the fifth input terminal 50 is the buffer BUF1. Buffered through and connected to the input terminal of the OR gate (OR3). The second and third input terminals 20 and 30 of the address signal are connected to the input of the NAND gate NA3 through the buffer BUF1, and the output terminal of the NAND gate NA3 passes through the inverted gate N3 and the AND gate AN2. Is connected to be input inverted by input of The output terminal of the NAND gate NA3 and the output terminal of the inverting gate N2 are connected to the input terminal of the OR gate OR2, and the output terminal of the OR gate OR2 and the fifth input terminal 50 of the command input signal are OR gates. The portion connected to the input terminal of the OR3 is the first gate circuit 300a of FIG.

: Date/Command)입력단자인 제 6 단자(21), 독출신호(

: Read)입력단인 제 7 단자(22), 기입신호(

: Write)입력단인 제 8 단자(23), 스테이터스(STATUS)인에이블(

: Status Enable)신호출력단인 제 9 단자(24), 데이타 인에이블(

: Date Enable)신호 출력단인 제10단자(25)를 연결하고, 래치(LAT)의 입·출력단이 CD-ROM드라이버(500)의 선택(

: Driver Selector)단(26-29)이 연결되며, 버퍼(BUF3)의 입·출력단에 데이타버스단(D0-D7)을 연결하여 구성된 부분이 CD-ROM드라이버(500)이다.The output terminal of the inverted gate N1 and the buffer BUF1 of the first gate circuit 300a described above are inverted and connected to the input terminal of the AND gate AN1 by inverting the first input terminal 10 which is the address enable input signal terminal. The output terminal of the AND gate AN1 is connected to the input terminals of the NAND gate NA1, the inverting gate N2, and the NAND gate NA2, respectively, and an output signal of the second input terminal 20, which is an address input signal terminal, is The second gate circuit 300b of FIG. 1 is a portion buffered in the buffer BUF1 and connected to the NAND gate NA1, and the output terminal of the NAND gate NA1 is input to the NAND gate NA2. The output part of FIG. 1 is connected to the output of the input unit 200 and the output terminals of the first and second gates 300a and 300b to the buffer BUF2, the 3-state buffer ST1, and the latch circuit LAT. 400. The buffer circuit 600 of FIG. 1 is formed by connecting the data bus DB0-DB7 of the main computer I / O channel unit 100 to the latch circuit LAT and the buffer BUF3 of the output unit 400. to be. A data / command signal for transmitting a signal to a CD-ROM to the buffer BUF2 input / output terminal of the output unit 400 (

: Date / Command) Input terminal 6, 21, read signal (

Input terminal, the seventh terminal 22 and the write signal (

: Write) Eighth Terminal 23, Status Enable

: 9th terminal 24, status enable), data enable

: Connect the 10th terminal 25, which is the Date Output) signal output terminal, and select the CD-ROM driver 500 as the input / output terminal of the latch (LAT).

The driver selector stages 26-29 are connected, and the portion formed by connecting the data bus terminals D0-D7 to the input / output terminals of the buffer BUF3 is the CD-ROM driver 500.

3 is an operating waveform (ah), (a'-h ') diagram of the second embodiment according to the present invention, (a) (a _c ) is a driver selection signal waveform, (b) (b') is (C) (c ') is the command input signal waveform, (d) (d') is the read signal waveform, and (e) (e ') is the wait data request signal. Waveform, (f) (f ') is a data enable signal waveform, (g) (g') is a status enable signal waveform, and (h) is for reading data of a predetermined area in a CD-ROM compact disc. The data waveform designates a block and the number of blocks according to time in a predetermined area. The (h ') waveform is a data waveform to be read.

4 is a flowchart of the present invention. Selecting a CD-ROM driver and receiving a command to check whether data is enabled or not, and if the data is not a data enable signal in the first step, inputting the command data again to determine whether or not to enable the status. A second step of checking, a third step of checking whether there is an error when the status enable process is not repeated when the data is enabled in the second step, and correcting the error when there is an error in the third step There is a fourth process of reading another block when there is no.

Therefore, when an embodiment of the present invention is described in detail with reference to FIGS. 1-4, when a user wants to read data in a CD-ROM compact disc, a command must be given to read a predetermined area. Through the main computer I / O channel unit 100, various peripheral devices (monitor, printer, FDD, HDD, modem…) installed in an expansion slot are set to use a predetermined extended channel. The sensor receives the signal through the first to fifth input terminals 10-50, and is already known, but the sensor must go to the area so that it can access the information to be read first. Input / output (I / O) for selecting a driver, i.e., a fixed address signal, is generated and specified. For example, when the instruction address data corresponds to the address of 303H, "high" is applied to the second input terminal 20, "high" is applied to the third input terminal 30, and when the 300H is input, the second input terminal 20 is " Low " and the third input terminal 30 are " low " to find a block to be accessed by the sensor as soon as the command is written. In the case of 301H, "low" is applied to the second input terminal 20 and "high" is applied to the third input terminal 30 to set the address of the passage of data to be read. At the time of reading, it becomes 302H, and "high" is applied to the 2nd input terminal 20, and "low" is applied to the 3rd input terminal 30, and it reads the data enable signal and the status enable signal which read all data simultaneously with a read command. It is. At 300H, the second input terminal 20 becomes " low " and the third input terminal 30 " low " to output data to the main computer. Specifically, according to the above-described example, since an instruction must first be written, an operation of "low" is applied to enable the address to the first input terminal 10 and the instruction input to the fifth input terminal 50. The write signal according to the above becomes an active " low ". The second and third input terminals 20 and 30 are all “high” when the 303H address signal is applied and is buffered in the buffer BUF1.

)와 3-스테이트버퍼(ST1)를 인에이블 시킴과 동시에 오아게이트(OR2)의 출력이 "로우"가 되도록 한다. 이어서 오아게이트(OR3)출력이 래치회로(LAT)의 클럭단(CK)으로 입력되어 메인컴퓨터 I/O채널부(100)측의 데이타버스(DB0-DB3)를 통해 출력되는 신호에 따라 제 3 도의 드라이버 선택 파형(a,a')과 같이 래치 인에이블 상태에서 클럭이 "로우"에서 "하이"로 변할때 CD-ROM드라이버(500) 선택단(26-29)으로 선택신호를 발생한다.At this time, the data read signal is input as "high" and is applied as "high" to the DIR terminal of the buffer BUF3 as a control signal for reading through the buffer BUF1 through the fourth input terminal 40. At this time, the direction of data flow from the main computer I / O channel section 100 to the CD-ROM driver 500 is set, and this signal is applied to the AND gate AN2. In addition, a "low" signal through the fifth input terminal 50 is buffered in the buffer BUF1 and input to the oragate OR3. On the other hand, the output of the oragate OR1 buffering the input signals of the fourth and fifth input terminals 40 and 50 in the buffer BUF1 becomes "high" and is inverted to "low" in the inversion gate N1. The signal is input to the AND gate AN1 like "low" of the first input terminal 10 through the buffer BUF1. At this time, since the input terminal of the AND gate AN1 is configured to invert the input signal, all of them are applied as "high", and the output of the AND gate AN1 becomes "high", and the "high" of this output is the NAND gate NA1. , NA2) and inverting gate (N2) input. Since both "high" of the second and third input terminals 20 and 30 are input to the NAND gate NA3 through the buffer BUF1 and output as "low", this signal is output from the oragate OR2 and the inverting gate N3. ), The output of the inverting gate (N3) is input to the AND gate (AN2). The output of the OR gate OR2 is " low " at the inversion gate N2 because of the " high " of the output of the AND gate AN1 described above, so that the output enable end of the latch circuit LAT

) And the 3-state buffer ST1 are enabled, and the output of the oragate OR2 is " low ". Subsequently, the output of the OR gate OR3 is input to the clock terminal CK of the latch circuit LAT, and according to a signal output through the data bus DB0-DB3 of the main computer I / O channel unit 100 side, the third output is performed. As shown in the driver selection waveforms (a, a ') of FIG. 1, when the clock is changed from "low" to "high" in the latch-enabled state, a selection signal is generated by the CD-ROM driver 500 selection stages 26-29.

단자를 인에이블 시키므로 메인컴퓨터 I/O채널부(100)의 데이타버스(DB0-DB7)에서 CD-ROM드라이버(500)의 데이타버스(D0-D7)로 선택된 데이타 흐름의 방향에 따라 선택된 드라이버측의 컴펙디스크에 수록된 데이타 독출을 위해 명령어가 제 6 단자(21)로 "로우"로 제 3(a) 도의 (b)와 같이 인가된다.At this time, the NAND gate NA2 output is "high", and the output of the AND gate AN2 becomes "low" by the "low" output of the NAND gate NA1, so that the output of the inverted gate N4 becomes "high". Therefore, the input and output of the buffer BUF2 cannot be opened (Isolation), and the buffer BUF3 is not opened due to the output " high " of the NAND gate NA2, so that only the designated CD-ROM driver 500 is selected. Subsequently, 300H addresses are sequentially assigned by the subroutine program, and "low" is input to the second and third input terminals 20 and 30, respectively, so that the output of the AND gate AN1 is "high" and the second input terminal 20 is output. The input is " low " input to NAND gate NA1. At this time, the output of the NAND gate NA1 is "high" and is input to the NAND gate NA2, so the output of the NAND gate NA2 is "low". At this time, the output of the AND gate AN2 is " low " because the NAND gate NA1 output is " high ". Since this signal becomes "high" through the inverting gate N4, the upper three terminals of the buffer BUF2 are activated, and the CD-ROM driver 500 passes the data command and seventh through the sixth terminal 21. A control signal for reading out to the terminal 22 and a signal for writing to the eighth terminal 23 are generated, wherein the sixth and eighth terminals 21 and 23 are applied in a "low" state. At this time, the output of the NAND gate NA2 is " low "

Since the terminal is enabled, the driver side selected according to the data flow direction selected from the data bus (DB0-DB7) of the main computer I / O channel unit 100 to the data bus (D0-D7) of the CD-ROM driver 500. A command is applied to the sixth terminal 21 "low" as shown in FIG. 3 (a) (b) to read data contained in the compact disc.

Subsequently, as shown in (c) of FIG. 3 (a), the "low" of the fifth input terminal 50 leads to the CD-ROM driver 500 through the buffers BUF1 and BUF2. That is, the signal indicating the command to the sixth terminal 21 is the waveform of (b) of FIG. 3 (a), and the waveform of (b) of the third (a) of FIG. Since the seventh terminal 23 is written, it is output as a waveform as shown in (c) of FIG. 3 (a), and the operation code (OP code) and minute ( A predetermined area in the compact disc to be read by the control unit in the CD-ROM driver 500 is placed on the required data bus of MIN, SEC, BLOCK, and N blocks. At this time, since the output of the NAND gate NA2 is "low" in the "high" state of the DIR terminal of the buffer BUF3, the command data described above from the main computer I / O channel unit 100 to the CD-ROM driver 500. Is buffered in the buffer BUF3 so that the 301H address is input as a "low" signal to the second input terminal 20 and a "high" signal to the third input terminal 30, and at this time, an output of the NAND gate NA3. Becomes " high " so that these two signals are input to the inverting gate N3 and the OR gate OR2. When the output of the inverted gate (N3) is input to the AND gate (AN2), the output of the oragate (OR2) is input to the oragate (OR3), the output of the oragate (OR3) is "high", The output of the AND gate AN2 is " low " to generate a " high " state at the inversion gate N4. Therefore, the "high" signal of the third input terminal 30 passes through the buffers BUF1 and BUF2, and the bus designation selection signal for data output is input through the sixth terminal 21 connected to the CD-ROM driver 500. The data is read out by designating the bus address using the data of the predetermined data output path designated on the compact disk of the ROM driver 500. When designating address 302H, "high" is output to the second input terminal 20 and "low" to the third input terminal 30, and "low" is output to the fourth input terminal 40 as a signal for the read command. Since the writing is completed, the fifth input terminal 50 becomes "high". Accordingly, when the signal is buffered in the buffer BUF1 and output, the read and command write signals are output in the "high" state at the OR gate OR1, and are inverted at the inversion gate N1, thereby inverting the first input terminal 10. When the input is input to the AND gate AN1 like the value output through the AND gate, “high” is output from the AND gate AN1. When this signal and the "high" signal output through the second input terminal 20 are input to the NAND gate NA1, the output of the NAND gate NA1 is output as "high" and is input to the buffer BUG2. The sixth, seventh, and eighth terminals 21, 22, and 23 of the driver 500 are blocked. On the other hand, the output of the NAND gate NA3 becomes "high". It is inverted at the inversion gate N3 and becomes "low". The read signal is buffered through the buffer BUF1 so that the NAND gate NA1 is output as "low". Subsequently, since the respective signals are input to the AND gate AN2, the output becomes "high", and then becomes "low" at the inverting gate N4, and is activated when applied to the buffer BUF2. Therefore, the lower output port of the buffer BUF2 is activated. Port control, i.e., the signal input tenth terminal 25 for enabling data on the CD-ROM driver 500 side and the status enable signal for completing data read for the block, the ninth terminal 24 has three signals. -The state is enabled in the state, and at this time, it is input as the waveform (f ') (g') of FIG. 3 (b) through the 9th and 10th terminals 24 and 25, and (h 'of FIG. 3 (b). In the example of the data shown in Fig. 2), all data of the corresponding block has been read out, and the status enable signal (g) is input from the (b ') waveform command signal "low" in FIG. 3 (b) to indicate completion of reading. By the signal, " low " is applied to the second input terminal 20 and " low " This force is the "high". Subsequently, the output of the AND gate AN2 becomes "low" while the lower output port control terminal of the buffer BUF2 is changed to the 3-state state, while the output of the NAND gate NA2 becomes "low", thereby providing the buffer BUF3. By enabling the enable end, the read data is sent to the main computer. In the above-described operation, data is read as in the flowchart shown in FIG.

As described above, data transmission is smooth and simple interfacing, so it is excellent in reliability and stability, and large data processing is possible according to driver selection, and unlike FDD or HDD, data is preserved semi-permanently unless the disk is damaged. There is a convenient advantage.

Claims (1)

In a computer system having a main computer I / O channel section 100 to which the main computer expansion slot can be connected, and a CD-ROM driver 500 for controlling a large amount of data to be stored by connecting a CD-ROM. And an input unit 200 which receives commands and function signals outputted from the main computer I / O channel unit 100 and buffers them, and receives and inputs data of the input unit 200 to select and data the CD-ROM driver 500. A first gate circuit 300a for inputting a flow direction selection signal and an enable signal in a data access state at the time of reading to generate a signal for controlling the output control terminal, and a control signal for writing commands and data for a region to be read out; Generates a signal such that the CD-ROM driver 500 is selected by the second gate circuit 300b generating the enable signal for data direction setting and the output signals of the first and second gate circuits 300a and 300b. And poison The main computer I according to an output unit 400 for generating an instruction signal of one region and an enable signal in a data access state, and outputs of the first and second gate circuits 300a and 300b and the output unit 400. Interfacing of the CD-ROM driver, characterized in that the data transfer direction between the / O channel unit 100 and the CD-ROM driver 500 is determined and buffer circuit 600 for buffering data to input and output data Control circuit.

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