KR890000805B1 - Memory space mapping system - Google Patents

Abstract

The method is for extending memory of 8bit microprocessor up to 64KB with a special register and a segment discripter memories. The logical addresses (LAB12-15) are assigned to the address of characteristic register (2) comprised by 8bit characteristic code (2a) and segment address (2b). The segment address signals (SAB0-7) are assigned to the address of a segment discripter (3) comprised by 4bit page address (3a), 16bit base address (3b), and 12bit range code (3c). The page address (PG0-3), the base address (BAB0-15), and the logical address (LAB0-11) signals are mixed in an adder (4) and converted to 20bit physical address signals (PAB0-19).

Description

Memory Space Expansion Method Using Memory

1 is a block diagram illustrating a concept of a memory space expansion method according to a conventional bank method.

2 is a conceptual diagram illustrating a memory space expansion method according to a conventional overlapping method.

3 is a block diagram illustrating a memory space expansion method using a memory of the present invention.

4 is a detailed block diagram of one embodiment according to the method of the present invention.

* Explanation of symbols for main parts of the drawings

1: microprocessor 2: characteristic register

3: segment descriptor 4: summer

5: characteristic violation detection circuit 6: segment region violation detection circuit

7: Multi-input Noah Gate 8, 9, 11: Buffer

10: multiplexer 12: bootroom

The present invention relates to a method of extending memory addressing in an 8-bit microprocessor, and in particular, a separate memory can be used to extend the maximum memory space of an 8-bit microprocessor from 64 kilobytes to the required amount of bytes. In addition, the present invention relates to each memory space expansion method by a memory partitioning method including pages.

In general, 8-bit microprocessors are used to reduce hardware overhead when there is a large amount of data, without being severely limited in processing a program. In this case, banking or overlapping to expand memory space is performed. apping) method.

로 뱅크

를 선택하여 메모리 스페이스를 확장하는 방식으로서, 일예로 뱅크(BK₀)을 선택했을 경우에는 고정뱅크(FBK)의 32키로 바이트와 뱅크0(BK₀)의 32키로 바이트가 선택되어 마이크로 프로세서의 메모리 스페이스가 확장되었다. 따라서 이 방식에 있어서는 뱅크선택신호

를 출력하는 뱅크수위치의 크기에 따라 소요되는 양의 크기로 스페이스를 확장시킬 수는 있으나, 데이타의 전송에 있어서 뱅크(BK₀-bk₇)중 임의의 뱅크의 프로그램이 다른 뱅크의 데이타를 필요로 한 경우 그 데이타를 반드시 고정뱅크(FBK)를 공통영역으로 사용하게 할 수 있으나, 이는 고정뱅크(FBK)의 양이 32키로 바이트로 한정되어 있으므로 프로그램 및 데이타의 분산처리가 어려워지는 결점이 있었다.However, in the bank method, as shown in FIG.

Low bank

In this example, when the bank BK ₀ is selected, 32 bytes of the fixed bank (FBK) and 32 bytes of the bank 0 (BK ₀ ) are selected to select the memory space of the microprocessor. The space has been expanded. Therefore, in this method, the bank selection signal

Although the space can be expanded to the required amount according to the size of the number of banks to output the data, a program in one bank of the banks (BK ₀ -bk ₇ ) needs data from another bank to transfer data. In this case, it is possible to use the fixed bank (FBK) as a common area. However, since the amount of the fixed bank (FBK) is limited to 32 kilobytes, it is difficult to distribute the program and data. .

In addition, in this method, since each bank (BK _0- BK ₇ ) is divided into 32-byte byte regions, many banks that cannot be used during the multiprocessing of the program are generated, thereby reducing the memory usage efficiency. On the other hand, since each bank (BK ₀ -BK ₇ ) has only the characteristics of a read-only area, a program area, and a data area, memory protection cannot be considered at all.

가 인가된 상태에서 중첩메모리 선택신호

가 인가된 경우에는 오아게이트(OR₂)의 출력단자에 저전위 신호가 출력되어 중첩메모리(M₁)를 인에이블 상태로 만들고, 보통 메모리 선택신호

가 인가된 경우에는 오아게이트(OR₁)의 출력단자에 저전위 신호가 출력되어 보통메모리(M₂)를 인에이블 상태로 만드는 방식으로서, 이 방식은 많은 메모리를 사용하지 않는 경우에는 적합하나, 그렇지 않는 경우에는 중첩메모리(M₁)의 용량크기에 제한을 받게되고 메모리를 보호할 수 없게되는 결점이 있었다.In addition, the overlapping method is a method of expanding a memory space of a microprocessor by accessing a memory having an overlapping address only in a specific situation as a complement of hardware. In other words, the overlapping scheme uses a specific memory selection signal as shown in FIG.

Overlap Memory Selection Signal

When is applied, a low potential signal is output to the output terminal of the OR gate (OR ₂ ) to make the overlapped memory (M ₁ ) enabled, and the normal memory selection signal

When is applied, a low potential signal is output to the output terminal of the OR gate (OR ₁ ) to make the normal memory (M ₂ ) enabled. This method is suitable when not using a lot of memory. Otherwise, there is a drawback that the capacity of the overlapped memory M ₁ is limited and the memory cannot be protected.

Accordingly, an object of the present invention is to use a specific register memory and a segment descriptor memory separately, so that the maximum memory space of the microprocessor can be extended from 64 kilobytes to the required amount without being limited by the capacity of the memory. In providing.

It is another object of the present invention to protect each memory segment by extending the memory space in a memory partitioning method including pages.

The present invention having the above object will be described in detail with reference to the accompanying drawings.

로 인가하고, 또한 상기 로지컬 어드레스신호(LAB₀-₁₁)가 세그먼트 디스크립터(3)의 최대 제한범위 코드(3a)에 기록된 제한범위 코드신호(BAB₀-₁₁)에 위반되는가를 세그먼트 영역위반 검출회로(6)에서 검출하여 마이크로 프로세서 (1)에 에어러인터럽트신호

로 인가하게 구성한 것으로, 도면의 설명중 미설명부호 7은 다입력노아게이트를 나타낸다.The third turning memory space as an expansion method block diagram shown to this, the logical address signal _{(Logical address) (LAB 12 -} 15) that is output from the microprocessor (1) using a memory of the present invention to an 8-bit attribute code (2a ) and the segment address (2b) to specify the address of a specific register (2), and the attribute register (2), segment addresses (2b) address signal (SAB ₀ output from the consisting of-page address of 4 bits to ₇₎ An address of the segment descriptor 3 composed of (3a) and a 16-bit base address (3b) and a 12-bit maximum range code (3c), and the page address (3a) and the base of the segment descriptor (3). address output from the address (3b) signal (PG ₀ - _7), 20 bits in the adder 4, the _{- - (11 LAB 0) (} BAB 0 15) and the microprocessor (1) the logical address signals output from the Physical Les (physical address) signal (PAB ₀ - ₁₉₎ combined with it will be specified the address of the external memory. In addition, the characteristic register (2) of attribute code (2a) attribute code signal that is output from-error interrupt signal (CC _{0 7)} to detect violations in the characteristic detection circuit 5, the microprocessor (1)

As is, and also the logical address signal (LAB ₀ - _11), the segment descriptor (3) up to the limit recorded in the cord (3a) the limit code signal (BAB ₀ - ₁₁₎ of the Is in violation of the segment region violation detection Detected by the circuit (6) and the air interrupt signal to the microprocessor (1)

In the drawing, reference numeral 7 denotes a multi-input NOR gate.

The process of changing the address of the present invention as described above will be described with an example of reading the contents of the memory at address 510 0h in the microprocessor 1. However, at this time, it is assumed that the value of the segment address 2b recorded at address 5 of the specific register 2 is 10h, and the content of the segment descriptor 3 corresponding to 10h is 11000FFFh.

Therefore, when a logical address signal of 5100h output from the microprocessor (1), the logical address sinhojung logical address signals (LAB ₂₂ - ₁₅₎ to specify a 5-address of the particular register 2 by a 5h (0101B) corresponding to Therefore, a 10h 8-bit segment address signal of the segment address 2b recorded at address 5 is outputted, and the 10h segment address signal is designated at the 10h address of the segment descriptor 3 because it designates a segment of the 10h address. 1h (0001B) is output from the page address 3a, and 1000h (0001 0000 0000 0000 B) is output from the base addresser 3b and applied to the summer 4. Yiettara, the logical addressable sinhojung logical address signals (LAB ₀ - ₁₁₎ received from the microprocessor (1) a page address signal output from the base addressable (3b) of the segment display clip emitter 3 to the signal 100h corresponding to 1h is further converted into an address signal of the bottom 11100h, and the signal 11100h, which is added to the 20-bit physical address signal in the summer 4, is applied to an external memory to designate its address. That is, the physical address signal 11100h designates a memory having a base address of 1000h and an offset of 100h in page 1 of the byte block with 64 keys.

As described above, the relationship between the logical address signal output from the microprocessor 1 and the physical address signal output from the summer 4 may be changed by the value of the specific register 2 or the value of the segment descriptor 3. This indicates that when there are programs or data in the memory corresponding to all physical addresses, their processing can be performed only by changing the values of the property registers 2 and the segment descriptors 3.

Next, the protection aspect of the memory will be described taking the case where data is written to the address 6300h in the microprocessor 1 as an example. However, at this time, the value of the characteristic code 2a recorded at address 6 of the specific register 2 is 80h, the value of the segment address 2b is 11h, and the value of the segment descriptor 3 corresponding to the address 11h is Assume 03000100h.

로 인가되므로 그 마이크 프로세서(1)는 외부 메모리에 데이타를 기록할 수 없게된다.Therefore, since the 6300h logical address signal is designated by the microprocessor 1, the characteristic code signal of 80h is output from the characteristic code 2a recorded at the address 6, and the segment address signal of 11h from the segment address 2b. The characteristic code signal of 80h output from the characteristic code (2a) is detected by the characteristic violation detection circuit (5), and then the error gate signal is transmitted to the microprocessor (1).

The microphone processor 1 cannot write data to the external memory because it is applied.

In this case, when the characteristic code signal of the characteristic code 2a is 00h and there is no writing violation, the segment address signal of 11h is output from the segment address 2b of the specific register 2 as described above, and the segment descriptor is outputted. Since the address of (3) is specified, a page address signal of 0h is output at the page address 3a of the segment descriptor 3, and a base address signal of 3000h is output at the base address 3b, and the maximum limit range code. In (3c), a limited range code signal of 100h is output.

로 인가되므로 외부메모리 번지의 지정을 할 수 없게된다.Accordingly, the logical address sinhojung logical address signals (LAB ₀ - ₁₁₎ received from the microprocessor (1) is 300h signal corresponding to and which exceeds the limit code signal 1000h, it in the segment region violation detection circuit 6 Error detection signal to the microprocessor 1 through the noah gate 7 after detection

Since it is applied as, the external memory address cannot be designated.

로 인가하게 하며 또한 상기 특성위반 검출회로(5) 및 세그먼트 영역위반 검출회로(6)의 위반검출신호를 에러리드신호

에 의해 버퍼(8)를 통해 마이크로 프로세서(1)의 데이타 버스(DB₀-₇)로 인가하게 하고, 또한 마이크로 프로세서(1)의 데이타 신호를 엠엠유(MMU) 라이트신호

에 의해 버퍼(9)를 통해 특성 레지스터(2)의 특성코드신호(CC₀-₇) 및 세그먼트 어드레스신호 (SAB₀-₇)와, 세그먼트 디스크립터(3)의 페이지 어드레스신호(PG₀-₃) 및 베이스 어드레스신호(BAB₀-₁₅), 제한범위 코드신호(OAB₀-₁₁)를 엠엠유리드신호

에 의해 멀티플렉서(10)를 통해 마이크로 프로세서(1)에서 읽을 수 있게 한다. 또한 마이크로 프로세서(1)에서 외부라이트(EXWR)에 의해 버퍼(11)를 통해 외부메모리에 데이타를 기록할 수 있게하고, 외부리드신호

에 의해 외부메모리의 데이타를 버퍼 (11)를 통해 읽을 수 있게한다.Specifies the address of a characteristic register (2), the fourth turning third degree exemplary detail a block diagram of a microprocessor 1, a logical address signal that is output from-logical address signal ₍₁₅ LAB ₁₂₎ of (LAB _{0 15)} that is, the attribute register (2) segment address output from the segment address (2b) signal (SAB ₀ - ₇₎ of the page address and to specify the address of a segment descriptor (3), the segment descriptor (3) ( 3a) page base address signal (PG ₀ output from said logical address signals a ₁₅₎ from the summator _{(4) (LAB 0 - -} 3) and the base address signal (BAB ₀ outputted from the base address (3b) ₁₉₎ After converting to, specify the address of the external memory. The characteristic features output from the attribute code (2a) of the register (2) code signal (CC ₀ - ₇₎ for the detection in a characteristic violation detection circuit 5 by the processor control signal (PS), and a logical address signal (LAB ₀ is input NOR gate after detecting ₁₅₎ segment violation detection circuit 6 for is contrary to - _15), the segment descriptor (3) up to the limit code (3) limits the code signal (BAB ₀ output from the Error interrupt signal to the microprocessor (1) through (7)

And the violation detection signal of the characteristic violation detection circuit 5 and the segment region violation detection circuit 6 to the error lead signal.

Through a buffer 8 by the data bus of the microprocessor (1) to be applied (DB _{0 7),} and also the MMC data signal of the microprocessor (1) u (MMU) light signal

Attribute code signal attribute register (2) through a buffer (9) by (CC ₀ - ₇₎ and the segment address signal (SAB ₀ - _7), and a page address signal of the segment descriptor _{(3) (PG 0 - 3} ) and a base address signal (BAB ₀ - _15), the limit code signal - the (OAB _{0 11)} MMC Ulead signal

To allow the microprocessor 1 to read through the multiplexer 10. In addition, the microprocessor 1 allows data to be written to the external memory through the buffer 11 by an external write signal EXWR, and an external read signal.

By this, data of the external memory can be read through the buffer 11.

또는 부트롬선택신호

에 의해 부트롬(12)을 동작시켜 시스템의 초기치를 결정할 수 있게 한 것으로, 이의 동작과정은 제3도의 동작과정과 동일하다.And power-on reset signal

Or bootrom selection signal

By operating the boot ROM 12 to determine the initial value of the system, its operation is the same as the operation of FIG.

가 플립플롭(13)의 프리세트단자

에 인가되면 그의 출력단자

에 저전위 신호가 출력되어 부트롬(12)의 인에블단자

에 인가되므로그 부트롬(12)의 내용을 읽어 시스템의 각 초기치를 결정함과 아울러 특성레지스터(2) 및 세그먼트 디스크립터(3)의 초기치를 결정하게 되고, 이후 부트오프 명령신호

가 출력되어 플립플롭(13)의 클리어단자

에 인가되면 그의 출력단자

에 고전위 신호가 출력되므로 부트롬(12)은 그의 구동을 중지하게 된다. 이때 플립플롭(13)의 출력단자

에서 출력되는 고전위 신호를 이용하여 마이크로 프로세서(1)에 리세트를 걸어주게 되면, 이때부터 마이크로 프로세서(1)는 로지컬 어드레스신호 (LAB₀-₁₅)를 출력하여 정상적인 프로그램 수행이 가능하게 된다.Power-On Reset Signal with Power Supply

Preset terminal of the flip-flop 13

When applied to his output terminal

Low potential signal is output to enable terminal of bootrom 12

Since the initial value of the system is determined by reading the contents of the boot ROM 12, the initial values of the property registers 2 and the segment descriptors 3 are determined.

Is output to the clear terminal of the flip-flop 13

When applied to his output terminal

Since the high potential signal is output to the boot ROM 12, the driving thereof is stopped. At this time, the output terminal of the flip-flop (13)

If granted by the high potential signal outputted from the walking reset the microprocessor (1), wherein the microprocessor (1) from the logical address signals, it is possible to perform a normal program and outputting (LAB _{0 15).}

에 의해 멀리플렉서(10)를 통해 마이크로 프로세서(1)에서 읽을 수 있게된다.That is, the logical address signal (LAB ₀ - ₁₅₎ from the microprocessor (1) if the output, that the logical address sinhojung logical address signals (LAB ₁₂ - ₁₅₎ is therefore to specify an address of a specific register (2), the specified address The segment address signals SAB _0-7 of the specific register 2 recorded in &_quot; ₁ " are output to designate the address of the segment descriptor 3, and accordingly the page address signal of the segment descriptor 3 stored at the designated address. PG ₀ - ₃₎ and the base address signal (BAB ₀ - ₁₅₎ is output, the signal adder 4 in the logical address signal (LAB ₀ - ₁₁₎ and haphaejyeo the 20-bit physical address signal (PAB ₀ - ₁₉ is to specify the address of the external memory after a) convert, wherein characteristic features output from the register 2 keudeu signal (CC ₀ - ₇₎ and the segment address signal (SAB ₀ - _7), and a segment descriptor (3) in Output page address signal (PG ₀ - ₃₎ and the base address signal (BAB ₀ - ₁₅₎ limits the code signal - the (OAB _{0 11)} MMC Ulead

This allows the microprocessor 1 to read through the multiplexer 10.

를 인가하면, 마이크로 프로세서(1)는 인터럽트 상태로 된 후 에러리드신호

에 의해 상기 특성위반 검출회로(5) 및 세그먼트 영역위반 검출회로 (6)의 에러위반신호를 버퍼(8)를 통해 읽어 판별하게 된다.Further, at this time attribute register (2) attribute code signal being output on the output from a segment descriptor _{(3) (CC 0 - -} 7) a characteristic violation detection circuit is detected in (5), wherein the logical address signals ₍₁₁ LAB ₀₎ limit code signal (OAB ₀ - ₁₁₎ that are then detected in the segment region violation detection circuit 6 is a violation of the error to the microprocessor 1 through the NOR gate 7, an interrupt signal

If the microprocessor 1 is applied, the microprocessor 1 enters into an interrupt state and then an error read signal.

By this, the error violation signal of the characteristic violation detection circuit 5 and the segment region violation detection circuit 6 is read through the buffer 8 and discriminated.

에 의해서는 그 지정된 번지에 기록된 데이타를 마이크로 프로세서(1)에서 버퍼(11)를 통해 읽게된다.In addition, the summer 4, a physical address signal output from the as above-buffer from a microprocessor (1) by the (PAB _{0 19)} to specify the address of the external memory, the external write signal (EXWR) to the address ( 11) Data is recorded via the external lead signal.

By reading the data recorded at the designated address from the microprocessor (1) through the buffer (11).

또는 세그먼트 선택신호

로 특성레지스터(2) 또는 세그먼트 디스크립터(3)를 선택한 후 엠엠유 라이트신호

에 의해 버퍼(9)를 통해 그 특성레지스터(2) 또는 세그먼트 디스크립터(3)의 지정된 번지에 데에타를 기록하게 된다.When the data is recorded in the characteristic register 2 and the segment descriptor 3 in the microprocessor 1, the characteristic code selection signal

Or segment selection signal

After selecting the characteristic register (2) or segment descriptor (3),

By means of the buffer 9, the data is recorded at the designated address of the property register 2 or the segment descriptor 3.

As described above, since the present invention uses a specific register memory and a segment descriptor memory separately, the maximum memory space of the microprocessor can be extended from 64 kilobytes to the required amount without being limited by the capacity of the memory. Since memory is expanded in a memory partitioning scheme including pages, there is an advantage of protecting each memory segment.

Claims (3)

Logical address signals output from the microprocessor (1) addressable in the characteristics of the 8-bit code (2a), and consisting of a segment address (2b) attribute register _{(2) (LAB 0 - -} 15) of the signal ₍₁₅ LAB ₁₂₎ to the page of a four-bit address (3a) and a 16-bit base address (3b), a 12-bit up to the limit code (3c) - the specified and, if a particular register (2) segment address signal ₍₇ SAB ₀₎ of specifies the address of the segment descriptor (3) is configured, the page address signal (PG ₀ - ₃₎ of the segment descriptor (3) and the base address signal from a summer (4) for (BAB _{0 15)} the logical address signals ( LAB ₀ - ₁₁₎ combined with the physical address signal (PAB ₀ in 20-bit - and then converted to ₁₉₎ memory space expansion method using a memory, it characterized in that it specifies the address of the external memory. The method of claim 1, wherein the characteristics of a particular register (2) code signal (CC ₀ - ₇₎ are detected in the characteristic violation detection circuit 5, an error interrupt to the microprocessor (1)

Memory space expansion method using the memory characterized in that According to claim 1, wherein the microprocessor (1) the output is a logical address signal (LAB ₀ - ₁₁₎ in a segment descriptor (3) limits the code signal (OAB ₀ - ₁₁₎ that is output from the violation happens the segment area violation detected in Error Interrupt Signal Detected by the Circuit 6 to the Microprocessor 1

Memory space expansion method using a memory, characterized in that the application.

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