KR890000509Y1 - Regular energy signal system - Google Patents

Abstract

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Description

Circuit system for supplying constant energy signal to peripheral driver

1 is a block diagram of a constant energy signal supply system of the present invention.

2 is a waveform diagram of a constant energy signal showing the principle of operation of the main controller of FIG.

3 is a waveform diagram of each part of FIG.

4A is a detailed circuit diagram of the power supply voltage detector of FIG.

4b is a detailed circuit diagram of the clock generator of FIG.

* Explanation of symbols for main parts of the drawings

1: power supply voltage detector 2: clock generator

3: main control part 5: driving part

6: peripheral driver

The present invention relates to a constant energy signal supply system, and in particular, a constant energy signal supply system capable of supplying a constant energy signal to a peripheral driver using a head mill, a solenoid head, a step motor, and a solenoid requiring a constant energy supply. It is about.

In general, in a system for controlling a peripheral driver by a microprocessor, the period and magnitude of the driving signal depend on the system clock frequency of the microprocessor. Therefore, when driving several driving circuits in a short time, the power supply voltage drops together with insufficient voltage, so that the driving part cannot operate at a certain quality. Especially, the driving part that prints or positions letters has a serious problem. There was a defect that was caused.

The present invention is designed to supply a constant energy signal to the drive unit by changing the frequency of the system clock rising to the change in accordance with the fall or rise of the power supply voltage, current, in view of such a conventional drawback.

In this paper, unlike the case where a local current compensation circuit is used, there is no need to match the signal of the main controller with the signal of the driver.

Below. The configuration, operation, and effects of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a constant energy signal supply system of the present invention, as shown therein, a power supply voltage detection unit 1 for detecting a variation in voltage and current of a power supply Vcc and outputting a corresponding voltage, and the power supply. The driver 5 generates a clock generator 2 for generating a clock signal of a predetermined cycle according to the output voltage of the voltage detector 1 and a control signal for a predetermined time according to the cycle of the clock signal output from the clock generator 2. In the description of the drawings, reference numeral 4 denotes an input unit for processing an external key signal and applying the same to the main controller 3, and 6 denotes a peripheral driver controlled by the driver 5. .

However, the energy of the signal for driving the peripheral driver 6 is the power (V) of the voltage (V) and current (I) of the power source (Vcc) and the power (Vcc) is supplied to the peripheral driver (6) It is determined by the energization time t. Accordingly, as shown in FIG. 2, the energization time t during which the power supply Vcc is supplied to the peripheral driver 6 in proportion to the change amount of the power W is changed by changing the voltage V of the power supply Vcc. By changing in the same manner, the energy Wxt of the signal for measuring the peripheral driver 6 can be made constant. That is, when a large load is applied within a short time and the voltage V of the power supply Vcc is lowered, and thus the low power W ₂ is supplied to the peripheral driver 6 as shown in FIG. By controlling the negative portion 3, the energization time t2 is lengthened, and the voltage V of the power supply Vcc is increased, thereby increasing the power supply to the control driver 6 as shown in FIG. 2 (a). When (W ₁ ) is supplied, the energy Wxt of the signal for driving the peripheral driver 6 can be made constant by shortening the energization time t _{1 under} the control of the main controller 3. .

For example, the detection of the power supply voltage detector 1 detects an appropriate line of heat generation temperature in the case of a thermal head, an appropriate torque in the case of a step motor, and an energy (Wxt) in order to generate an appropriate impact amount in the case of a solenoid. The constant energy is supplied to the peripheral driver 6 by calculating from the system clock cycle of the clock generator 2 according to the voltage, which will be described with reference to the waveform diagram of FIG.

The voltage V of the power supply Vcc is detected by the power supply voltage detection unit 1 as shown in FIG. 3 (a) and applied to the clock generator 2 as the oscillation control voltage. Therefore, when the voltage V detected by the power supply voltage detector 1 is a proper voltage V _r , the oscillation signal of a certain period is generated by the clock generator 2 and applied to the main controller 3 as a system clock. do. By the way, when the voltage V detected by the power supply voltage detector 1 is higher than the proper voltage V _r , the clock generator 2 has the proper voltage V _r as shown in FIG. Is generated, the oscillation signal of a faster period is generated and applied to the main control section 3 as a system clock, and the voltage V detected by the power supply voltage detection section 1 is greater than the voltage V proper voltage V _r . In the low case, as shown in FIG. 3B, the clock generator 2 generates an oscillation signal having a slower period than that of the proper voltage V _r , and is applied to the main controller 3 as a system clock. Accordingly, the main controller 3 controls the energization time t of the peripheral driver 6 by controlling the driving time of the bulb 5 according to the cycle of the system clock, as shown in FIG. 3 (c). The peripheral driver 6 is supplied with constant energy, that is, w ₁ t ₁ = w ₂ t _{2 =} w ₃ t _{3 =} w ₄ t ₄ .

FIG. 4A is a detailed circuit diagram of the power supply voltage detector 1. As shown therein, the power supply Vcc is divided by the resistors R _{1 and} R ₂ and applied to the non-inverting input terminal of the operational amplifier A ₁ . The output voltage of the discrete op amp A ₁ is output as the detection voltage V _m , and the detection voltage V _m is output and inverted in the inverter operational amplifier A ₂ . In this figure, reference numerals R _{3 and} R ₄ denote outputs of the detection voltage (-V _m ), and the gain of the operational amplifier A ₁ ( Resistance, and R _{5 and} R ₆ are the gains of the operational amplifier (A ₂ ) Resistance. The power source voltage detector (1) is constructed as a detection voltage (V _m) proportional to the voltage of power supply (Vcc) -, and outputs the (V _m). That is, the voltage of the power supply Vcc is divided by the resistors R ₁ and R ₂ , and then amplified in these overpath operational amplifiers A ₁ according to the resistors R _{3 and} R ₄ to the detection voltage V _m . Inverted at the operational amplifier A ₂ , the inverter outputs the detection voltage (−V _m ), and the detection voltages V _m and (−V _m ) are applied to the clock generator 2 as a generation control voltage.

The 4b turning a detailed circuit diagram of a first even clock generator (2) thereto as shown detected voltage (V _m), the power source voltage detector (1) (- V _m) of the drain are commonly connected field effect transistors ( Q ₁ ) and (Q ₂ ) are connected to the sources respectively, and the output voltage of the operational amplifier (A ₃ ) for the comparator is connected to the gate of the field effect transistors (Q ₁ ) and (Q ₂ ) through the resistor (R ₉ ). It is connected to the non-inverting input terminal of the comparator operational amplifier (A ₃ ) through an integrator composed of its operational amplifier (A ₃ ) and divided by resistors (R ₇ ) and (R ₈ ). And the drain voltages of the field effect transistors (Q ₁ ) and (Q ₂ ) are inverted inputs of the operational amplifier (A ₄ ), the resistor (R ₁₀ ), the capacitance (C ₁ ), and the operational amplifier (A ₃ ) for the voltage follower. Applied to the terminal and arranged to be applied to the main control unit 3 as a system clock. Explain the operation section.

When the output voltage Vo of the operational amplifier A _{3 for the} comparator is higher than the detection voltage V _m of the power supply voltage detector 1, the field effect transistor Q ₁ is turned off and the field effect transistor Q ₂ Since the output voltage of the operational voltage amplifier (A ₄ ) for the voltage follower is dependent on the detection voltage (-V _m ) of the power supply voltage detector 1 to form a ramp waveform, while the operational amplifier (A ₃ ) When the output voltage V _O of the output voltage V ₀ is lower than the detection voltage (−V _m ) of the voltage detector 1, the field effect transistor Q ₁ is turned on and the field effect transistor Q ₂ is turned off. The output voltage of (A ₄ ) is dependent on the detection voltage V _m of the power supply voltage detection unit 1. The output voltage of the voltage follower operational amplifier (A ₄ ) output as described above is integrated and output from an integrator composed of a resistor (R ₁₀ ), a capacity (C ₁ ), and an operational amplifier (A ₅ ). 1) detects a voltage (V _m) (a - a square wave having a predetermined frequency according to V _m) is the generation. Where frequency f is Becomes

As described in detail above, the present invention provides constant energy to the peripheral driver even if the power supply voltage changes, so that the operation quality of the peripheral driver is improved and the compensation circuit is not limited to the driver. The application is easy without changing, and the peripheral drive part has a long life.

Claims (1)

For detecting a voltage level of the power source (Vcc) detection voltage (V _m -V · _m), a detection voltage (V _m -V · _m) to be output to the power detector (1) prior to Rioja source voltage detector (1) to the output of the And a clock generator (2) for generating a clock signal of a predetermined frequency in accordance with the magnitude and applying the clock signal to the main control unit (3) as a system clock.