KR880004575A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR880004575A
KR880004575A KR1019860007505A KR860007505A KR880004575A KR 880004575 A KR880004575 A KR 880004575A KR 1019860007505 A KR1019860007505 A KR 1019860007505A KR 860007505 A KR860007505 A KR 860007505A KR 880004575 A KR880004575 A KR 880004575A
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South Korea
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semiconductor device
oxide film
film
polycrystalline silicon
deposition
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KR1019860007505A
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Korean (ko)
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KR900000827B1 (en
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이진효
채상훈
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경상현
재단법인 한국전자통신연구소
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Publication of KR900000827B1 publication Critical patent/KR900000827B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음No content

Description

반도체 장치 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 바이폴라 NPN 트랜지스터의 단면도. 제2도는 본 발명에 의한 바이폴라 NPN 트랜지스터의 제조공정을 설명하기 위한 단면도. 제3도는 종래의 다결정 실리콘 자기 정렬 바이폴라 NPN 트랜지스터의 단면도1 is a cross-sectional view of a bipolar NPN transistor according to the present invention. 2 is a cross-sectional view illustrating a manufacturing process of a bipolar NPN transistor according to the present invention. 3 is a cross-sectional view of a conventional polycrystalline silicon self-aligned bipolar NPN transistor

Claims (3)

웨이퍼 표면에 비소를 이온 주입하여 N+매입층(15)을 형성시키고 그 위에 인이 도핑된 1.4m 두께의 에피택셜층(16) 형성시키며 그 위에 500Å의 열산화막을 성장시키고 1500Å의 질화막을 저압 증차법으로 증착시킨 후 이를 마스크 물질로 사용하여 실리콘 표면을 5500Å정도 부식시키고 P+형 불순물을 이온 주입한 후 10K Å의 두께의 열 산화막(17)을 성장시켜 각 소자를 격리하는 반도체 소자의 제조방법에 있어서 보론을 이온 주입하여 트랜지스터의 베이스 영역(19)을 형성시킨 후 웨이퍼 전 부분에 걸쳐서 3000Å의 다결정 실리콘막을 저압 증착법으로 증착시킨 다음 비소를 이온 주입하여 N+형으로 만들고 그 위에 2000Å의 1차 산화막(23)과 2000의 질화막(24)을 저압 증착법으로 각각 증착시킨 후 이를 마스크 물질로 사용하여 건식 부식에 의해 다결정 실리콘층을 부식시켜 에미터(20) 및 콜렉터(21)를 정의하되 다결정 실리콘층을 완전히 제거하지 않고 500Å정도 남긴다음 습식부식에 의해 제거함으로써 비활성 베이스 영역(26)이 형성될 단결정 실리콘 표면이 손상되는 것을 방지하는 것을 특징으로하는 반도체 장치 제조방법.Arsenic is implanted into the surface of the wafer to form an N + buried layer 15, a 1.4m thick epitaxial layer 16 doped with phosphorus is formed thereon, a 500 열 thermal oxide film is grown thereon, and a 1500 Å nitride film is formed at a low pressure. After deposition by vapor deposition, using this as a mask material, the surface of the silicon is corroded to about 5500Å, ion implanted with P + type impurities, and then a thermal oxide film 17 having a thickness of 10KÅ is grown to fabricate a semiconductor device that isolates each device. In the method, the boron is ion implanted to form the base region 19 of the transistor, and then a polycrystalline silicon film of 3000 mW is deposited by low pressure deposition over the entire portion of the wafer, followed by ion implantation of arsenic to form an N + type. 2000 with primary oxide film 23 After depositing the nitride film 24 of each of the low pressure evaporation method and using it as a masking material to corrode the polycrystalline silicon layer by dry corrosion to define the emitter 20 and the collector 21, without completely removing the polycrystalline silicon layer A method of manufacturing a semiconductor device, characterized in that it prevents damage to the surface of a single crystal silicon on which the inactive base region (26) is to be formed by removing it by wet corrosion and leaving it at about 500 GPa. 제1항에 있어서 습식 부식 시간을 적당히 조정케 하므로서 다결정 실리콘층에 의한 에미터(20)의 폭을조정 가능케한 것을 특징으로 하는 반도체 장치 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the width of the emitter (20) by the polycrystalline silicon layer can be adjusted by appropriately adjusting the wet corrosion time. 제1항, 제2항에 있어서 2500Å두께의 2차 산화막(27)을 저압 증착법으로 증착한 다음 활성 이온 부식을 통해 실리콘 양쪽 측면(28)을 제외한 나머지 수평면의 2차 산화막(27)을 제거하되 1착 산화막(23)은 질화 보호막(24)으로 손상을 방지하여 개별소자 전기적 특성을 개선하여 웨이퍼 전체의 수율까지 향상시킬 수 있는 반도체 소자의 제조방법에서 3000Å의 다결정 실리콘막(29)을 저압 증착시킨 후 보론을 열 확산 혹은 이온 주입방법으로 도핑시켜 P+형으로 만들어준 다음 열 처리함으로써 저항이 낮은 P+비활성 베이스영역 (26)을 만들거나 이온 주입방법에 의해 보론을 주입하여 열 처리함으로써P+비활성 베이스 영역을 먼저 만든 다음 금속 중착에 의해 베이스 전극을 만들어 주게한 것을 특징으로하는 반도체 장치 제조방법.The secondary oxide film 27 of claim 1 or 2 is deposited by low pressure evaporation, and then the secondary oxide film 27 on the horizontal plane except for the two sides 28 of silicon is removed by active ion corrosion. The first oxide film 23 is a low-pressure deposition of a 3000 Å polycrystalline silicon film 29 in a semiconductor device manufacturing method capable of preventing damage with the nitride protective film 24 to improve individual device electrical characteristics to improve the yield of the entire wafer. After the boron is doped by heat diffusion or ion implantation to form P + , and then heat treated to form a low-resistance P + inactive base region 26 or by injecting boron by ion implantation to heat treatment. + A method of manufacturing a semiconductor device, comprising first forming an inactive base region and then making a base electrode by metal deposition. ※참고사항 ;최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the first application.
KR1019860007505A 1986-09-08 1986-09-08 Semiconductor device manufacturing method KR900000827B1 (en)

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Application Number Priority Date Filing Date Title
KR1019860007505A KR900000827B1 (en) 1986-09-08 1986-09-08 Semiconductor device manufacturing method

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Application Number Priority Date Filing Date Title
KR1019860007505A KR900000827B1 (en) 1986-09-08 1986-09-08 Semiconductor device manufacturing method

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KR880004575A true KR880004575A (en) 1988-06-07
KR900000827B1 KR900000827B1 (en) 1990-02-17

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