KR880002276A - How to make bipolar and complementary field effect transistors (BiCMOS) simultaneously - Google Patents

Abstract

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Description

How to make bipolar and complementary field effect transistors (BiCMOS) simultaneously

As this is a public information case, the full text was not included.

1 is a cross-sectional view of a semiconductor structure showing masking and doping of a substrate.

2 is a cross sectional view following the formation of the epitaxial layer.

3 is a cross sectional view after formation of a field oxide region.

* Explanation of symbols for main parts of the drawings

10 semiconductor substrate 12 p conductive impurity

15: mask 18: buried layer

21: epitaxial layer 24: N well mask

27,28: N well 30: P well

33: silicon dioxide 35: silicon nightlight

39: field oxide 40: base

45 polycrystalline silicon 48 photoresist

52 substrate tab 55 source and drain regions

58: collector 60: emitter

Claims (48)

A semiconductor structure comprising a silicon layer having an upper surface and having a first region of a first conductivity type and a second and third regions of a second conductivity type separated from each other at that surface by electric field regions of an buried insulator layer A method of manufacturing a method comprising: forming an insulating layer on a surface of a silicon layer, forming a protective layer of conductive material over the entire insulating layer except for the first portion of the third region, and forming a first conductive layer in the first portion of the third region. Form impurities are introduced, the insulating layer is removed from the surface of the silicon layer of the first portion of the third region to use the protective layer as a mask, and a conductive material is further attached onto at least the first portion of the third region, respectively. Removes the protective layer from the insulating layer except for the first portion of the first region and the first portion of the second region and the second portion of the third region, wherein the first portions of the first region are separated from the electric field region, Fabricating the semiconductor structure comprising introducing a first conductivity type impurity into the second region except where covered by the layer and a second conductivity type impurity into the first region except where covered by the protective layer Way. 2. The method of claim 1, further comprising the step of further attaching the protective material and doping the added protective material to lower its resistance. 3. The method of claim 2 including subsequently removing the protective layer and heating the structure such that some of the impurities in the conductive material diffuse into the third region. The method of claim 1, wherein forming the insulating layer consists of oxidizing a silicon layer. The method of claim 1, wherein forming the protective layer comprises forming a polycrystalline silicon layer. 6. The method of claim 5, wherein attaching additional conductive material further comprises attaching polycrystalline silicon. 6. The method of claim 5, wherein forming the protective layer consists of attaching a protective layer over the entire structure and then removing the protective layer from the first portion of the third region. The method of claim 1, wherein the semiconductor structure provides a bipolar transistor and a pair of complementary field effect transistors. 9. The method of claim 8 wherein the NMOS device is formed in the first region and the PMOS device is formed in the second region and the bipolar device is formed in the third region. 10. The method of claim 9, wherein forming an insulating layer provides a layer of insulating material to separate at least one gate electrode from an underlying substrate. The method of claim 10, wherein forming the protective layer comprises forming a gate electrode. 12. The method of claim 11, wherein introducing a first conductivity type impurity into the first portion of the third region comprises forming a base of the bipolar device. 12. The method of claim 11, wherein introducing a first conductivity type impurity into the second region and a second conductivity type impurity into the first region comprises doping the source and drain of the CMOS device. A semiconductor comprising a silicon layer having an upper surface and having a first region of a first conductivity type and a second and third regions of a second conductivity type separated from each other at that surface by an electric field region of silicon dioxide embedded in a layer. A method of fabricating a structure, comprising: forming a gate insulating layer of silicon dioxide on a surface of a silicon layer, and forming a polycrystalline silicon layer over the entire gate insulating layer except for the first portion of the third region where the base of the bipolar transistor is required. Introducing a first conductivity type impurity into the first portion of the third region to define the base, removing the gate insulating layer from the surface of the silicon layer of the first portion of the third region to use polycrystalline silicon as a mask, Attaching additional polycrystalline silicon over the first portion of the third region and over the polycrystalline silicon layer, the gate electrode of each of the first and second regions Insulation except for the first portion of the first region to define a gate electrode that is spaced apart from the electric field regions and the first portion of the second region to define a gate electrode different from the first region and the second portions of the third region to define an emitter contact. Where the polycrystalline silicon is removed from the layer, where the first conductivity type impurity is introduced in the second region except where it is covered by the protective layer to define the source and drain, and which is covered by the protective layer to define the other source and drain. A method of manufacturing the semiconductor structure comprising introducing a second conductivity type impurity into the first region except for the above. The method of claim 1, wherein the first impurity of the second conductivity type is introduced into at least one first region of the substrate, the second impurity of the second conductivity type is introduced into the first region, and an epitaxial layer is formed on the substrate. And introducing a second conductivity type impurity into at least one first region of the epitaxial layer covering the first area of the substrate, and heating the substrate such that the epitaxial layer and the second conductivity type impurity of the substrate diffuse into contact with each other. Having a top surface in a method consisting of: a first region of a first conductivity type and a second and a third region of a second conductivity type, the first, second and third regions buried in a layer Producing a silicon layer separated from each other on the surface by an electric field region of the insulating material. 16. The method of claim 15, wherein introducing a second conductivity type impurity into at least one first region of the epitaxial layer comprises forming a pair of spaced first regions of the epitaxial layer to define the first and second wells. Introducing a second conductivity type impurity such that the pair of first regions are separated by sandwiching a region of an epitaxial layer of opposite conductivity type to define a third well. 17. The method of claim 16, followed by forming an insulating material layer across the epitaxial layer. 18. The method of claim 17, followed by forming a protective layer of protective material over the entirety of the insulating material except for the first portion of the first well. 19. The method of claim 18, followed by introducing impurities of a first conductivity type into the first well through the first portion. 20. The method of claim 19, followed by removing insulation from the first portion of the first well and forming additional protective material over at least the first portion of the first well. 21. The method of claim 20, followed by removing all of the protective material from the structure surface except for the second portion of the first well, the first portion of the second well and the first portion of the third well. 22. The method of claim 21, wherein a first conductivity type impurity is introduced into the two regions of the epitaxial layer spaced by the first portion of the second well, and the two of the epitaxial layers spaced by the first portion of the third well. Said method being followed by introducing a second conductivity type impurity into the regions. 23. The method of claim 22, followed by forming electrical connections in each of the wells. A method of manufacturing a semiconductor structure on a first conductivity type substrate, comprising: introducing a first impurity of a second conductivity type into at least one first region of the substrate, and a second impurity of a second conductivity type into the first region; To form an epitaxial layer on the substrate, to introduce a second conductivity type impurity into at least one first region of the epitaxial layer overlying the first region of the substrate, and to form the epitaxial layer and the second conductivity type in the substrate. Heating the structure to cause impurities to diffuse and contact each other. 25. The method of claim 24, wherein introducing the first impurity comprises introducing phosphorus. 27. The method of claim 25, wherein introducing the second impurity comprises introducing arsenic. 27. The method of claim 26, wherein the concentration of phosphorus is approximately 3x10 ¹³ -3x10 ¹⁴ atoms per square centimeter and the concentration of arsenic is approximately 1x10 ¹⁵ -1x10 ¹⁶ atoms per square centimeter. The method of claim 27, wherein heating the structure consists of heating to a temperature of approximately 1050-1100 ° C. for approximately 1-2 hours. 25. The method of claim 24, further comprising forming a mask to form a field oxide region prior to the heating step. 30. The method of claim 29, wherein the heating step further comprises oxidizing the epitaxial layer to form a field oxide region. 25. The method of claim 24, wherein the substrate is comprised of P conductive silicon having a resistivity of 11-18 ohm centimeters. 32. The method of claim 31, wherein forming the epitaxial layer is preceded by doping the substrate with P conductivity type impurities. 33. The method of claim 32, wherein the substrate is doped with boron. 34. The method of claim 33, wherein the amount of boron is approximately 3x10 ¹² -5x10 ¹³ atoms per square centimeter. 25. The method of claim 24, wherein introducing the at least one first region is preceded by forming a mask defining the at least one first region. 36. The method of claim 35, wherein said at least one first region consists of a buried layer. 25. The method of claim 24, wherein forming an epitaxial layer consists of attaching undoped silicon. 38. The method of claim 37, wherein forming the epitaxial layer is followed by introducing a P conductivity type impurity into the epitaxial layer. 39. The method of claim 38, wherein introducing an epitaxial layer into at least one first region is followed by masking the epitaxial layer except the first region. 40. The method of claim 39, wherein the second conductivity type impurity is phosphorus and its concentration is approximately 1-2x10 ¹² atoms per square centimeter. 25. The method of claim 24, wherein introducing the first impurity into the at least one first region comprises introducing the first impurity into a pair of first regions of the substrate, wherein at least one first of the epitaxial layer Wherein introducing the second conductivity type impurity into the region comprises introducing the second conductivity type impurity into the pair of first regions of the epitaxial layer. 42. The method of claim 41, wherein the pair of first regions of the epitaxial layer comprises a first well spaced from a second well, the epitaxial layer between the first well and the second well comprises a third well, And forming a first channel type field effect transistor in a first well, a bipolar transistor in a second well, and forming a second channel type field effect transistor in a third well. 43. The method of claim 42, wherein the first channel type consists of P channels and the second channel type consists of N channels. 42. The method of claim 41, wherein the epitaxial layer comprises a first well spaced from the second well, wherein the pair of first regions comprises an epitaxial layer between the first well and the second well as a third well, And forming transistors in each of the first, second and third wells. 45. The method of claim 44, wherein forming the transistors forms a first layer of insulating material across the surface of the epitaxial layer, introduces a first conductivity type impurity in the second well to the surface of the epitaxial layer, Forming electrodes on insulating material over the first and third wells, introducing a first conductivity type impurity into the first conductivity type region of the first well and the second well, and introducing a second conductivity type impurity on the opposite side of the electrode Said method consisting of introducing into a third well. A method of fabricating a semiconductor structure that will later form both bipolar complementary field effect transistors, comprising implanting a P conductivity type impurity into the entire semiconductor substrate and a first N into the first region of the substrate where the buried layer is to be formed. Implanting a conductivity type impurity, implanting a second N conductivity type impurity having different diffusivity into the first region, attaching an epitaxial layer of semiconductor material over the substrate, and forming an epitaxial layer overlying the first region of the substrate. Implanting N conductive impurities into one region and heating the structure such that one of the first or second N conductive impurities in the substrate is in contact with the N conductive impurities in the epitaxial layer. A method of fabricating a semiconductor structure, comprising: implanting a first N conductivity type impurity into first and second spaced regions of a substrate on which first and second spaced buried layers are to be formed using a first mask, Implanting a second N conductivity type impurity into the first and second spaced apart regions, introducing a P conductive impurity into the entire semiconductor substrate, attaching an epitaxial layer on the substrate, and using a second mask to Implanting N conductivity type impurities into the first and second spaced apart regions of the epitaxial layer overlying the first and second spaced apart regions, and using a third mask to first and second the epitaxial layer Oxidizing the field regions of the epitaxial layer to separate the regions from adjacent regions of the epitaxial layer, implanting a P conductivity type impurity into the first portion of the first region of the epitaxial layer using a fourth mask, 5 mask To form electrodes on the intervening region of the epitaxial layer between each of the first and second regions of the epitaxial layer as well as on the second portion of each of the first and second regions of the epitaxial layer, The method comprising introducing an N conductivity type dopant in the vicinity of an electrode on the intervening region and in the vicinity of an electrode on the first region using a mask. 48. The method of claim 47, wherein the BiCMOS structure is formed, the first mask forms a buried layer, the second mask forms N-type wells, the third mask forms an electric field oxide, and the fourth mask forms a bipolar base. And a fifth mask to form gate electrodes, and a sixth mask to form an NMOS source and drain and a bipolar emitter. ※ Note: The disclosure is based on the initial application.