KR880001442B1 - Video frequency reduction circiut - Google Patents

Abstract

The circuit for improving the unstability of the system caused by noise comprises a pair of character generators (D1, D2) storing character data, a pair of shift resisters (F1, F2) shifting the output of the generator, a multiplexer (M) whose clock tap receives dot pulse (H1) demultiplied from high dot clock pulse, and a display (G).

Description

Video frequency reduction circuit

1 is a conventional video circuit diagram.

2 is a circuit diagram according to the present invention.

3 is a diagram for explaining a character display operation by the circuit of FIG.

4 is a diagram for explaining a character display operation by the circuit of FIG.

* Explanation of symbols for main parts of the drawings

A: Central Processing Unit B: CRT Controller

C: Video Merolibu D: Character Generator

E: attribute memory section F: shift register

G: Monitor D ₁ , D ₂ : Character generator

F ₁ , F ₂ : Shift register M: Multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video circuit relating to video frequency reduction, and more particularly, to a circuit that can divide and use a pulse applied to an output pulse terminal of a shift register.

Conventionally, in a system requiring a "high" dot clock pulse of 30 MHz or more, there is a disadvantage in that an unstable state of the system occurs due to noise due to the use of the "high" dot clock pulse.

It is therefore an object of the present invention to provide a circuit capable of distributing "high" dot clock pulses to a system to eliminate system instability due to noise.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a conventional circuit diagram in which characters are displayed on a monitor by applying a "high" dot clock pulse to the clock terminal of the shift register F. As shown in FIG.

FIG. 2 is a circuit diagram according to the present invention, wherein respective data output from the character generators D ₁ and D ₂ are applied to the multiplexer M through the respective shift resists F ₁ and F ₁ . In this case, a dot pulse H ₁ divided by two "high" dot pulses is applied to the clock terminal of the multiplexer M, so that a character is displayed on the monitor G.

3 is for explaining the character display operation by the circuit of FIG. 1, in which character data stored in the character generator D generates pulses according to the clock pulse H of the shift register F. As shown in FIG.

4 is for explaining the character display operation by the circuit of FIG. 2, wherein character data embedded in the conventional character generator D is separately stored in the character generators D ₁ and D ₂ , respectively. Is an explanatory diagram of operations in which characters are displayed on the monitor G by dot clock pulses divided by two and applied to the multiplexer M via the shift registers F ₁ and F ₂ , respectively.

Description of the conventional circuit in such a configuration will be briefly described with reference to FIG. 1 and FIG.

The data of the letter A in the character generator D is stored as shown in the table below.

TABLE 1

Therefore, as shown in the "table", the character data is applied to the monitor G by the "high" dot clock pulse H applied to the shift register F, so that 0 0 0 1 1 0 0... 0 1 0 0 0 0 1 0 is shown to represent the letter A. The circuit operation according to the present invention will be described.

In the present invention, the character generator and the shift register must be rearranged by dividing the "high" dot clock pulse by two. Therefore, the present invention stores the character data of A in the circuit character generators D ₁ and D _{2 as} shown in Table 2 below.

TABLE 2

Therefore, when the character data generated in the character generators D ₁ and D ₂ are applied to the multiplexer M through the shift registers F ₁ and F ₂ , respectively, the multiplexer M A dot clock pulse H ₁ divided into two clock terminals is applied to the character data through the shift registers F ₁ and F ₂ so that 0 0 0 1 1 0 0 0... … 0 1 0 0 0 0 1 0 is shown to represent the letter A.

As described above, according to the present invention, since the "high" dot clock pulse is divided into two and used as the dot clock pulse, there is an advantage of stabilizing the system instability due to noise.

Claims (1)

In the video circuit comprising a character generator (D) for generating characters for stored characters and a shift resist (F) for receiving high dot clock pulses and converting them into serial data, the character generators (D ₁ ), (D ₂ ) And a shift register (F ₁ ), (F ₂ ) and a multiplexer (M) to apply the two-divided dot clock pulse (FH ₁ ) of the high dot clock pulse to the clock terminal of the multiplexer (M). A video frequency reduction circuit, characterized in that the configuration.

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