KR880000162B1 - Programmable multi-frequency tone receiver - Google Patents

Abstract

Appts. filters digitally coded signal samples to detect signal energy in one or more frequency passbands. The appts. is used in a programmable multi frequency tone receiver for a pulsecode-modulation commuications system. The appts. includes a digital filter and a sequence controller for time-multiplexing the filter to perform K cascaded M-order filtering operations, K, M being variable to provide a desired passband. The filter operates asynchronously from the controller. Digital signal samples are imput to the filter.

Description

Programmable multi-frequency tone receiver

1 is a general schematic diagram of a tone receiver embodying the present invention.

2 is a schematic diagram of the dependent filter operation performed for each multi-frequency tone signal.

FIG. 3 is a detailed schematic diagram of the tone receiver of FIG. 1 including FIGS. 3A, 3B, and 3C arranged as shown in FIG. 3D.

4 is a diagram for explaining the function of each bit of the instructions stored in the microprogram ROM included in FIG. 3B.

5 is a detailed schematic diagram of the filter timing logic included in FIG. 3B.

6 is a waveform diagram of a signal provided by the filter timing logic of FIG.

FIG. 7 is a distribution diagram utilized by the signal processing microcomputer included in FIG. 1 to process output received from a digital filter.

The present invention relates to a tone receiver for a communication system, and more particularly to a multi-frequency tone receiver for a pulse code modulation (PCM) communication system.

In prior art communication systems, the tone receiver is typically of the analog type in which both the language signal and the supervisory tone signal are transmitted in the form of analog in the communication channel. Recently, communication systems such as PCM have been introduced. This digital technology provides a very good sound quality signal transmission that does not degrade over long distances. Thus, since both the verbal and supervisory tone signals are digitally encoded in such a communication system, the digital tone receiver is better than the conventional analog tone receiver.

To detect a tone in the sampled digital signal, the digital tone receiver uses a Jeffrey P. Mills published in "May 1977," GTE Automatic Electric Journal, Vol. 15, No. The Fourier spectrum technique described in the article "Digital MF Receiver Techniques," published on pages 317-325 of 7, may be used; You may use the digital filter technique described in the paper "Special Hardware for Digital Filters", published in April 1975 by Proceedings of the IEEE, Vol. 63. No. 4, pages 633-648. have. The Fourier spectral technique described in this paper requires a large number of floating point moving multiplication operations and therefore a relatively expensive and power consuming high speed multiplier. Moreover, Fourier spectral tone receivers cannot easily perform the filter operation with a large number of dependent filters, both of which are varied in number and order, under program control.

In the case of digital filter technology, a tone receiver using a digital filter is much slower than a Fourier spectral tone receiver because it requires multiple multiplication operations for each filter. For example, three multiplication operations are required for each second digital filter. Because multiplication operation is time consuming, a tone receiver using a digital filter can only receive digital signals with relatively low sampling frequencies. Moreover, such a tone receiver must have a built-in different digital filter to detect each different tone signal from which a multi-frequency tone signal can be generated. The prior art tone receivers therefore require a very large number of fast multipliers, as in the Fourier spectrum type tone receivers, or a very large number of digital filters, which require a relatively slow multiplication operation, as in a digital filter type tone receiver. Done.

It is therefore an object of the present invention to provide an improved program tone receiver that uses fewer circuits than prior art tone receivers.

It is another object of the present invention to provide an improved program tone receiver that can be programmed to provide varying number and order multiple filter operations for detecting a plurality of tone signals occurring simultaneously.

It is a further object of the present invention to provide an improved program tone receiver that can be widely modulated to receive a plurality of digital signals.

It is another object of the present invention to provide an improved program tone receiver comprising an improved process for detecting the presence of a multi-frequency tone signal in a sampled digital signal.

It is a further object of the present invention to provide an improved program tone receiver which is controlled asynchronously to adequately speed up execution.

It is a further object of the present invention to provide an improved program tone receiver which supplies a continuous control signal for controlling the filter operation and which has a branching capability of the predetermined control signal in response to the predetermined filter condition.

In practicing the present invention, the device filters digitally coded signal samples for signal energy in one or more frequency pass bands. The filter includes a digital filter and a continuous controller for time multiplying the digital filter to perform the dependent M-order filter operation of K. Here, K and M may be varied to provide a predetermined frequency passband. The digital filter operates asynchronously with the continuous controller, operated by the filter start signal from the continuous controller, and supplies the filter end signal to indicate completion of the filter operation. Digital filters also supply an output signal that measures the signal energy of a particular frequency passband.

With other features of the present invention, the filter device may be adjusted to operate as a multi-frequency tone receiver including a signal processor for processing the digital filter output signal. The signal processor indicates that a particular tone signal is present when the digital filter output signal magnitude is greater than the predetermined magnitude. Thus, two or more tone signals generated simultaneously may be detected by filtering digitally coded signal samples for signal energy within the corresponding frequency passband for each tone signal.

The tone receiver of the present invention is particularly well suited for detecting the presence of multi-frequency tone signals, such as those used for supervisory signaling in communication systems. These multi-frequency tone signals are combined in various forms into two simultaneous tone signals that can be used to encode numeric information such as dials of telephone numbers. The digital code signal sample containing the multi-frequency tone signal may be supplied from the corresponding analog signal by a sampling analog-to-digital converter or may be any suitable digital code signal sample linearly digitized. The linearly digitized digital code signal sample may be applied directly to the tone receiver, whereas the PCM sample according to U-law or A-law must be developed into a linearly encoded sample before being applied to the tone receiver.

Hereinafter, the present invention will be described with reference to the drawings.

1 shows a system communication diagram of the tone receiver 100 in accordance with the present invention. The tone receiver 100 includes a micro programmed continuous controller 101, a time multiplied digital filter 102 and a signal processing microcomputer 103. In a suitable embodiment, the tone receiver 100 is programmed to receive a multi-frequency tone signal of digital code signal samples. Multi-frequency tone signals may be used to transmit surveillance information of a communication system. For example, a multi-frequency tone signal may use a combination of two of the six tone signals possible to encode a supervisory signal. In so-called North American MF tone signaling systems, any two combinations of six tones 700Hz, 900Hz, 1100Hz, 1300Hz, 1500Hz and 1700Hz have been used to encode dial and surveillance information. The definition of these MF signals can be found in Section 5, paragraph 6 of the "Note, on Distance Dialing" study of the bell system. Different tone numbers and different frequency tones in different calling systems are described, for example, in CCITT Green Book Vol. VIREC. It can be used for supervisory signaling called MFC-R _two- tone signaling detailed in Q. 365 ,. To adjust the tone receiver of the present invention to receive other types of tone signals, only the firmware of the tone receiver needs to be changed.

This unprecedented flexibility allows the tone receiver according to the invention to be used advantageously in any case where multiple different frequency signals must be detected simultaneously.

In a suitable embodiment, the digital code signal sample is a PCM sample of a PCM communication system. This PCM communication system is the same as the pending US patent application No. 876, 955 " Radio Telephony Communication System " filed on February 13, 1978, in the name of Kevin M., Colocia et al. No. 876, 956 filed simultaneously in the name of Little et al. A device for a radiotelephone communication system is described. In these PCM communication systems, PCM samples are typically coded according to one of two coding forms: U-law and A-law. The coding and signaling provisions for such PCM communication systems are published in Q, 46 and Q, 47 of the CCITT Green Book mentioned above.

For each sample, the continuous controller 101 is programmed to supply a continuous control signal to the time multiplied digital filter 102 to perform a K dependent Mth order filter operation for each of the six MF tones. Where K and M were chosen to be 3 and 2, respectively. The specific values of K and M were chosen to comply with the regulations published in the bell system for reliable detection of MF tones, although any values of K and M can be used in the practice of the present invention. In addition, upon completion of the K dependent filter operation for each MF tone, the digital filter supplies an output signal to the signal processing microcomputer 103, i.e., an 8-bit output signal that measures the energy of power at a particular MF tone frequency. do. Thus, the signal processing microcomputer 103 analyzes the energy measurements for each MF tone to determine the presence of a particular MF tone.

Energy measurements across the entire MF signal bandwidth are also needed to remove pseudo signals on strong similar signals having frequencies outside the MF signal bandwidth, or frequencies between two MF tones, to remove pseudo tones on a single strong tone. For example, in the latter case, a strong single tone of 800 Hz can generate sufficient energy in the 700 Hz MF filter and the 900 Hz MF filter, such as the 700 Hz / 900 Hz tone. Thus, additional filter operations are performed to measure the total energy over the entire MF signal bandwidth. When a strong monotone is present at 800 Hz, the total energy measurement will be greater than the energy measurements for the 700 Hz filter and the 900 Hz filter. Therefore, the strong pseudo signal and the pseudocomponent for a single tone are simplified by comparing the total energy measurement with the MF energy measurement and removing the MF energy measurement if the total energy measurement is greater than the MF energy measurement.

FIG. 2 shows the plot of the three subordinate secondary filter operations performed for each MF tone. The first two filters are bandpass filters 201 and 202, which have a bandwidth of 10 Hz and are staggered to maintain sharp rolloff while supplying sufficient bandwidth to maintain short tone recognition time. The final filters are full-wave rectified lowpass filters 203 and 204 for supplying the output signal, which is an energy measurement of the PCM signal at each MF tone frequency. Thus, for six MF tones, eighteen secondary filter operations are performed, and an additional full-wave rectified low pass filter operation is performed to supply the total energy measurement.

Each secondary filter supplies an output signal Y (N) characterized by the following equation.

Y (N) = A ₁ X (N) + A ₂ Y (N-1) + A ₃ (N-2)

Here, X (N) is the input signal of the filter, Y (N-1) and Y (N-2) are the previous two filter output signals, and A ₁ , A ₂ and A ₃ are filter coefficients.

This formula includes terms with circulation amounts Y (N-1) and Y (N-2), and is typically used to calculate the non-circulation amounts X (N-1) and X (N-2) used in the secondary filter of the prior art. It does not include the terms that it has. Thus, the secondary filter according to the above formula has a pole and no zero, while the prior art secondary filter has a double pole and two zeros. By simplifying the equation, the number of coefficients for each filter was reduced from five to three.

According to the prior art, three separate multiplication operations are required to implement the above equation. However, by using the digital filter mechanism where successive bits of signals X (N), Y (N-1) and Y (N-2) address a single coefficient, only one multiplication filter operation performs the above equation. Is required. Accordingly, the digital filter 102 of FIG. 1 performs a single multiplication so that each filter of FIG. 2 is executed for each MF tone under the control of the continuous controller 101. In this manner, the digital filter 102 is designed. By doing so, the time required by each filter operation is greatly reduced, and the digital filter 102 can also be easily multiplied to perform different filter operations for each MF tone under program control.

The detailed operation of the tone receiver of FIG. 1 will be more readily understood with reference to the detailed schematic diagram of FIG. FIG. 3a shows the signal processing microcomputer 103 of FIG. 1 and FIG. 3b shows the micro programmed continuous controller 101 of FIG. 1 and FIG. 3c shows the time-multiplied digital filter 102 of FIG. .

Referring to FIG. 3B, the continuous controller includes an address counter 325, a micro program ROM 326, and a command register 327. Instructions for supplying a continuous control signal are continuously read from the position of the micro program ROM 326 addressed by the address counter 325. Loaded into read command register 327. Each instruction includes 24 bits, of which 16 bits are control signals and the remaining 8 bits are address signals as shown in the form of instructions in FIG. Eight of the 16 bits for the control signal supply a control signal for positioning the 16-bit data bus 390 on the received data, and eight bits supply control signals for controlling the operation of the continuous controller and the digital filter. . The remaining eight bits supply the address signal 380 to the partial result RAM 331 and the coefficient ROM 360. The partial result RAM 331 and the coefficient ROM 360 are addressed by the same address signal 380, so that these memories are all divided into regions that are related to each other. For example, the region of the partial result RAM 331 may contain partial results for a particular filter operation, and typically the addressed region of the coefficient ROM 360 contains coefficients for the same filter operation.

The micro program ROM 326 is executed with three 1024x8 bit memories or one 1024x24 bit memory. The contents of the microprogram ROM 326 for the tone receiver of the present invention are shown in Table I. The 24-bit instructions stored in each position of the microprogram ROM 326 are represented in hexadecimal notation. For example, the command 71 DD 06 is stored at the position of the address 0000, and the instruction EIFD 29 is stored at the position of the address 003F. If microprogram ROM 326 is loaded with the data shown in Table I, the tone receiver of FIG. 3 will perform three dependent filter operations for each of the six MFs for each PCM sample, in addition to the total energy. A low pass filter will be performed on the measurement. However, any predetermined filter operation can be easily programmed using the memory method shown in Table II. For example, the three dependent filters of FIG. 2 can be implemented as shown in Table III. When the storage program as shown in Table III is executed once, the storage method of each step is formed into a 24-bit instruction by appropriately encoding the logic state of each bit according to the instruction form of FIG.

TABLE I

Micro Program ROM

After the filter operation for all six MF tones is completed, the tone receiver is stopped until another PCM sample is received from a preselected PCM channel. In the paused state, flip-flop 323 is reset and stops address counter 325 via NOR gate 324. In addition, the address counter 325 is started in the zero state. The preselected PCM channel is read from the five channel address lines by reading circuit 320. When the channel address is read from the channel address line, the read circuit 320 supplies an output pulse. The output pulse from the channel readout circuit 320 sets the flip-flop 323 to actuate the address counter 325 via the NOR gate 322 and resets the FIFD 307 via the NOR gate 308. And load an 8-bit PCM sample from a preselected PCM channel into the input PCM register 328.

Once the address counter 325 is acted upon, the address counter 325 supplies a sequential address signal to sequentially read the instructions stored in the microprogram ROM 326. The instructions are read and supplied to the clock 321. The control signal supplied by the read command is essentially similar to the execution of each filter.

TABLE II

Micro program memory

TABLE III

Sample microprogram for 3-stage tuned filter network

By the present invention, the following continuous control signal is supplied for each dependent filter operation. Before operating the digital filter as the filter start signal, the X (N) register 351, the Y (N-1) register 356 and the Y (N-2) register 354 are loaded from the partial result RAM 331. do. However, for the first filter of the three dependent filters, the X (N) register 351 is loaded as the PCM samples deployed from the PCM deployment ROM 329. On the other hand, for successive filters, the X (N) register 351 is loaded from the partial result RAM 331 as the preceding filter operation output signal. Once registers 351. 356 and 354 are loaded with the appropriate input signal, the filter start signal is applied to filter timing logic 330 to actuate the digital filter. The filter timing logic 330 first shifts the signals from registers X (N) 351, Y (N-1) 356, and Y (N-2) 354 to the shift registers 352 and 357, respectively. And after loading into 355, the filter timing logic 330 is driven from coefficient ROM 360 by the series bits and tone address signal 380 received from shift registers 352,357 and 355. Operate the digital filter to perform filter operation with addressed coefficients.

The rectified signal is applied to the flip-flop 350 via the NAND gate 349 for the low pass filter so that if the signal of the X (N) register 351 is negative, the Q output of the flip-flop 350 is logically high. Set to state. When the Q output of flip-flop 350 is logically high, the shifted bits from the shift register are logically complemented by an exclusive OR gate 353. This operation provides full wave rectification by a one's complement negative signal in the X (N) register 351. Although this operation provides an ideal two's complement, the error induced by the one's complement is so small that this error is essentially negligible. For a continuous filter, the flip-flop 350 is reset by the commutation / erase signal. When the filter operation is completed, the filter end signal is applied by the filter timing logic 330, and the digital filter output signal and the previous digital filter output signal are respectively Y (N) registers 370 and Y (N-1) registers ( 358).

According to another feature of the invention, the continuous controller is configured to perform an X (N) register 351, a Y (N-1) register 356 and a Y (N-2) register 354 during the digital filter operation. Is loaded with the signal for the next filter. When the continuous controller finishes loading the registers 351, 356, and 354, a stop signal is provided to disable the address counter and wait for the filter completion signal.

According to another feature of the invention, the continuous control signal supplied by the continuous controller may be modified in response to a predetermined condition by providing a branching capability. Branching can be accomplished by changing the state of the address counter in response to conditions such as polarity or excess conditions for the accumulator output signal. In order to execute a branch, a branch instruction may be supplied using a spare bit of the instruction (see FIG. 4) to actuate gates 396 and 397. Gate 396 acts as a negative condition for the accumulator output signal, and gate 397 acts as an excess condition. Thus, if the condition is satisfied, the gate 395 is logically high, which loads the address counter 325 with the address signal 380 from the instruction. The signal loads the address counter 325 with the address signal 380 from the branch instruction, as a result, the continuous control signal is stored in the microprogram ROM 326 at the position addressed by the address signal from the branch instruction. The branching capability of the continuous controller also improves the flexibility of control throughout the operation of the digital filter.

The filter timing logic 330 of FIG. 3 is shown in more detail in the schematic diagram of FIG. Referring to FIG. 4, the filter timing logic is divided into five flip-flops 501 through 506, a sixteen division counter 507, a flip-flop 508, and a digital circuit control circuit 510 to supply digital filter control signals. 516. By using the filter timing logic of FIG. 5, the digital filter of the present invention is operated asynchronously from a continuous controller. Once acted upon by the filter start signal, the filter timing logic activates the selected MF tone filter to actuate the digital filter for filter operation. When the filter operation is completed, the filter timing logic supplies a filter end signal. Thus, according to an important feature of the present invention, the digital filter is actually driven at the fastest speed by the filter timing logic without being delayed by the continuous controller.

The operation of the filter timing logic of FIG. 5 is initiated by the reception of a filter start signal which sets the Q output of flip-flop 501 to a logically high state. The logically high state from the Q output of flip-flop 501 is sent to flip-flops 502 through 506 in accordance with successive 8 MHz clubpulses. Counter 507 is activated when the Q output of flip-flop 502 changes to a logically high state. After the sixteenth pulse of the 8 MHz clock signal, the counter 507 supplies a reset pulse to reset the flip-flop 501. The signal waveform for FIG. 5 is shown in FIG.

Once the filter timing logic is activated by the filter start signal, the digital filter performs a 16-bit multiplication filter operation using the signals loaded into the shift registers 352, 355, and 357. Each signal of the shift registers 352, 355, and 357 is represented by a 16-bit fixed point portion having a sign bit and 15 data bits. The 15 data bits provide the full range of 90 db to receive the 30 dB identification region of the PCM signal, the 36 db gain of the digital filter and the 24 db dynamic range for the MF tone signal.

Typical digital filter operations are described in detail with reference to the waveforms of FIG. 3 and FIG. First, each of the shift registers 352, 355, and 375 is from the corresponding registers 351, 354, and 356 when the register / load and the shift signal 603 are logically low. Is loaded. The bits are then serially shifted from the shift registers 352, 355, and 357 to the path register 359 when the register / load and shift signal 603 is logically high. Register / load and shift signal 603 provides sixteen shifts for registers 352, 355, and 357 and register 357 is cycled through. Registers 352 and 355 may also be cycled as needed. The path register 359 is loaded with the 5-bit tone address signal 380 from the instructions in the command register 327. The tone address signal 380 from the instruction selects the portion of the coefficient ROM 360 containing the count signal for the particular filter operation to be processed. Thus, the coefficients for a particular filter operation are read from coefficient ROM 360 by three bits received from shift registers 352, 355, and 357 and through address signal 380.

The read factor is then loaded into the path register 362 through twelve exclusive OR gates 361 (only one is shown for clarity). The read factor is logically supplemented for the sine bit position by the exclusive OR gate 361 under the control of the sine / POS signal from the filter timing logic 330. If a sign bit is present, it is logically conservative because it represents a negative number and has a negative increment factor. When the exclusive OR gate 361 is acted upon, this beta OR gate supplies a complement of one representing the read factor. Ideally, two's complement representing the reading factor should be supplied. This problem is solved by supplying a carry bit via an add / day signal to the adder 363 to add a low order to one's complement representing the read coefficient for the sine bit position. Adding the low order bits to the one's complement yields a predetermined two's complement.

Table IV shows the contents of the coefficient ROM 360 for the MF tone receiver of the present invention. Each coefficient is 12 bits, including sine and 11 data bits, and is a fixed point portion that can take values between -2 and +2. Experiments have shown that 11 data bits are adequate for proper operation of the MF tone receiver of the present invention. Referring to Table IV, coefficients stored at respective address positions of the coefficient ROM 360 are displayed in hexadecimal notation. For example, 000 is stored at address position 0000 and 05E is stored at address position 009E.

Re-referencing the operation of the digital filter, each read coefficient of the coefficient ROM 360 loaded into the path register 362 is added in an accumulator comprising a 12-bit adder 363 and a 20-bit register 364. 363 adds the read coefficient from the path register 362 and the accumulator output signal from the register 364 shifted one bit to the right. The right shift of the accumulator output signal must be multiplied before it is added to the coefficient. This accumulator accumulates 16 times for each read coefficient of the coefficient ROM 360. Thus, in order to hold 16 accumulated operation results, register 364 should ideally be a 32-bit register. However, even if only 20 bits are provided in the register 364, the accumulator output signal is not degradable enough to be detected. During the last accumulate operation, the low order bits are applied to the carry input of adder 363 by the add / work signal 606 of FIG.

Table IV

This operation converts the one's complement, which represents the reading coefficient for the sine bit position, to the two's complement as described above. The add / day signal 606 may be used to circulate the accumulator signal by supplying a carry bit for one or more accumulation operations before the final accumulate operation. Circulation of the accumulator signal is desirable to improve performance by reducing the limit period of the digital filter output signal.

If the accumulator signal is exceeded, a large limit period is required. Therefore, the excess detection circuits 365 to 369 are provided to fix the accumulator signal at the predetermined maximum positive or predetermined minimum negative number when the excess occurs. Positive or negative excess is detected by exclusive OR gates 365 and 366 which examine the three high order bits of the accumulator signal. If the three high order bits are not in the same logic state, the select input of the multiplexer 369 serves to select the A input instead of the B input. If the A input of the multiplier 369 is selected, the sine bit A of the accumulator signal is supplied as a sine bit to the Y (N) register 370, and the remaining 15 data bits are logic maintenance of the sine bit A through the conversion gate 368. Is supplied. Thus, the 16-bit output signal supplied by the multiplexer 369 is either the largest positive 16-bit signal if the sine bit is a logical zero indicating positive accumulator signal, or one of the logical ones whose sine bit indicates a negative accumulator signal. This is the largest negative 16-bit signal. Alternatively, multiplexer 369 selects the B input, which supplies the 16 bits of the 20-bit accumulator signal with the lowest order bits and truncated secondary and tertiary bits from the accumulator signal.

After the final addition operation is executed by the accumulator, the Y (N) register 370 is loaded as a 16-bit accumulator signal from the multiplexer 369 in response to the filter end signal 613 of FIG. The filter end signal 613 is also applied to the set input of the flip-flop 323 through the NOR gate 322 to reactivate the address counter 325.

Next, the continuous controller stores the digital filter result from the Y (N) register 370 and the preceding digital filter result from the Y (N-1) register 358 of the partial result RAM 331. According to another feature of the invention, prior to storing the digital filter output signal and the preceding digital filter output signal, the continuous controller may operate the digital filter to perform the next filter operation, and with the X (N) register 351. Y (N-1) register 356 and Y (N-2) register 354 are loaded with the appropriate signal during preceding digital filter operation. If the last completed digital filter operation is the final operation for the slave filter, the continuous controller supplies a FIFO load signal to load the digital filter output signal from the Y (N) register 370 into the FIFO memory 307. Once the filter operation for all six MF tones has been completed once by continuous control, a stop signal and a reset signal are supplied to reset the address counter 326 to its final state, and the FIFO memory 307 results in the filter. Is supplied to set flip-flop 30 through gates 311 and 312 to supply a FIFO data valid signal to the signal processing microcomputer of FIG. However, the FIFO data valid signal is only activated when the signal processing microcomputer requests new data by operating the NAND gate 311 as the FIFO data request signal from the PIA 306, so that the FIFO data valid signal is logically applied. When turned high, the FIFO memory 307 is loaded as six energy measurements for each MF tone and one total energy measurement. The signal processing microcomputer processes seven energy measurements stored in the FIFO memory 307, and the high measurements were generated from PCM samples. Thus, the FIFO memory 307 is the main component for connecting a high speed continuous controller and a digital filter to a late signal processing microcomputer.

The signal processing microcomputer of FIG. 3A includes a microprocessor (MPU) 303, such as the Motorola M6800 (see US Pat. No. 4,030,079, and related patent references cited therein), and a read-only memory for control program storage, such as the Motorola M6830. (ROM), peripheral connector adapter (PIA) 306, such as the Motorola M6821 (see US Patent Nos. 3, 979, 730), and microprocessor 303, to reset the tone recognition microcomputer. A watchdog timer 301 for detecting a signal and an output register 305 for connecting a tone recognition microcomputer to another computer or a microcomputer, a FIFO memory 307 and an address decode logic circuit for storing digital filter energy measurements. 304. The address decode logic circuit 304 is a microprocessor 303 for reading a predetermined address to operate the watchdog timer 301, the ROM 302, the output register 305, the FIFO memory 307 and the PIA 306. Is coupled to the address line. Each block of the signal processing microcomputer of FIG. 3A can be implemented as a conventional logic device such as installed in the M6800 microcomputer system, and arranged and connected in a conventional manner. For example, the watchdog 301 may be installed with any monostable device, such as a Motorola MC 6840 programmable timer, and is periodically reset by the microprocessor 303. If it is not periodically reset, the time of the watchdog timer 301 is stopped, which monitors the address counter 325 of the continuous controller of FIG. 3B for resetting the scheduled resume address microprocessor 303. Supply a reset signal to reset the unit to its initial state. The installation of the watchdog timer 301 ensures that the microprocessor 303 does not reach its program location, which remains indefinitely.

The microprocessor 303 receives information from the continuous control and digital filter through the PIA 306. The information sensed by the PIA 306 includes a FIFO data valid signal from the flip-flop 310, three PCM channel number signals, and five PCM channel address signals. PIA 306 supplies the output signal from microprocessor 303 to shift and inactivate FIFO memory 307 and reset flip-flop 310.

The signal processing microcomputer processes the total energy measurement and the six tone energy measurements read out from the FIFO memory 307 according to the processing shown in the flow chart of FIG. The flow chart in FIG. 7 details the processing for recognizing MF tones that are dialed telephone numbers or MF digit sequence parts representing sense signals. Each energy measurement stored in FIFO memory 307 is an 8-bit word consisting of eight high order bits of the 16-bit digital filter output signal.

The signal processing microcomputer is occupied with information processing not normally involved in tone detection. Every 2.5 ms, the signal processing microcomputer is interrupted in response to the 2.5MS interrupt signal and proceeds to process the tone energy measurement according to the flow chart in FIG. Since the signal processing microcomputer does not need a tone energy measurement until it is interrupted, the FIFO data request signal is fed into a logic 0 state which prevents the energy measurement from being loaded into the FIFO memory 307. When an interrupt occurs in response to a 2.5MS interrupt, the signal processing microcomputer supplies a logic 1 state to the FIFO data request signal to obtain a new energy measurement. Thus, new energy measurements are only read from the FIFO memory 307 every 2.5 ms.

In accordance with another feature of the invention, the signal processing microcomputer has sufficient capacity to process energy measurements from digital filters and multiple pairs of continuous controllers, thereby providing additional blocks 315 including a PIA 306; FIFO memory 307 and FIFO data validating circuits 308 to 312 are coupled to the MPU for each additional continuous controller and digital filter pair. Thus, a signal processing microcomputer can be used in essence simultaneously with multiple pairs of continuous controllers and digital filters.

Referring to block 701 of FIG. 7, the signal processing microcomputer, after being supplied with the FIFO data request signal, continuously processes the FIFO data valid signal from the flip-flop 310 for a logically high state where a new energy measurement is obtained. To detect. When the FIFO data valid signal is logically high, the microcomputer compares the newly received energy measurement for each tone to the minimum level specified in the metric, and sets it to 1 for each tone energy measurement that is greater than the specified magnitude. Increase the variable T by If the variable T is greater than or equal to 1, program control proceeds to block 702 where a 10 ms digit timer is set. The 10ms period of the digit timer is determined by counting four interrupt signals.

If the variable T is less than or equal to 1 after proceeding to block 703 in response to the newly received tone energy measurement, program control proceeds to block 704. In block 704, after the second timer is set to receive the first tone, the second tone within 7.5 ms is checked to ensure that it is detected. Thus, to return the program control to block 703, the variable T must be greater than or equal to 2 indicating the reception of the second tone before the timer time of 7.5 ms has passed. If 7.5 ms has passed, program control proceeds to block 705 where an error is indicated, after which program control loops to block 701.

If the variable T is greater than or equal to 2 and 10 ms of time in block 703 has passed, program control proceeds to block 706 where a timer of 20 ms is set. If the variable T is reduced to 1 or less in response to the newly received energy measurement for a 20 ms time interval, program control proceeds to block 707. At block 707, a 10 ms timer is set to timing the transient. If the variable T is not greater than or equal to 2 at the end of the 10 ms time interval, the program control proceeds to block 708 to indicate an error and then returns to block 701. If a transient occurs and the variable T is again greater than or equal to 2 before 10 ms has passed, program control returns to block 706. If the time of the 20ms timer of block 706 has passed, program control proceeds to block 709.

To reach block 709, two tones must be detected within 7.5 ms of each other. One lasts for at least 30ms. Then, the energy measurement of the detected tone is checked so that it is in the range of -6dbm to -24dbm or in the range of 19db. This check is performed by shifting the microcomputer three times to the left and loading the energy measurements for each tone into the working registers. On the other hand, this is also done by checking the most significant bit of the enable register after each left shift. If the most significant bit is a logic one, the energy measurements are in the appropriate range since each left shift represents a signal level reduction of 6 db.

Next, the variable T must be exactly equal to 2, indicating that only two tones exist. If there are more than two or less tones, an error is indicated at block 710 and program control then proceeds to block 701.

Next, the twist between the two detected tones is checked by verifying that the two tones are within 6 db of each other. The check is performed by a microcomputer that loads the largest energy measurement into the working register and shifts it to the right once to split this largest energy measurement by subtracting the largest energy measurement divided in two from the second largest energy measurement. do. The detected tones are within 6 db of each other when the two divided largest energy measurement subtracted from the second largest energy measurement is zero or more.

The final check is made so that all tone energy measurements are below -24 dbm. This check is similar to a microcomputer shifting three times to the left by loading an energy measurement into the working register while the most significant bit of the working register is logical zero. If these checks fail, program control proceeds to block 710 where an error is indicated and program control then returns to block 701.

If all the checks processed in block 709 are successful, then program control passes to block 711. The signal processing microcomputer waits at block 711 until the two detected tones disappear. If the variable t becomes less than or equal to 1, program control proceeds to block 712 where a 20 digit intermediate digit timer is set. The program control then proceeds to block 713 and the program control proceeds to block 714 when the 20 digit intermediate digit timer time expires. An output word is formed that points to a particular MF digit that corresponds to the pair of tones detected at block 71. The output word is loaded by the signal processing microcomputer into the output register 305 of FIG. 3A for transmission to another computer or microcomputer for other processing. For example, another computer may accumulate a series of MF digits representing dialed telephone numbers. Thus, the variable T is reset to zero and program control proceeds to block 701 for receipt of the next MF digit.

Using the flow diagram of FIG. 7 and the description above, a person skilled in programming techniques can easily code a program to execute the steps called for each distribution block in an appropriate programming language. For example, distribution is directly translated into the program phase using conventional conversational programming languages such as the BASIC programming language. A sample program coded in the BASIC programming language for the distribution diagram of FIG. 7 is attached to the appendix. Commercially available assemblies for signal processing microcomputers can be used to convert the once encoded program into the appropriate mechanical command language. For example, assemblies and other auxiliary software can be readily obtained from conventional microcomputers such as the Motorola M 6800 microcomputer.

In summary, a novel tone receiver has been described that can be used to detect a sync tone signal in a sampled digital signal. For example, the tone receiver of the present invention can be used in a PCM communication system for detecting multi-frequency tone signals in a PCM signal, as well as in any system required for the synchronous detection of two or more tone signals in an analog or digital signal. Can be used. The tone receiver also includes a signal processing microcomputer that is properly programmed to indicate that a particular multi-frequency tone pair has been detected. The tone receiver of the present invention employs a system architecture comprising a micro programmed continuous controller and a digital filter operating asynchronously with the continuous controller. Moreover, the tone receiver of the present invention may be programmed to run for each digital signal sample, and may be programmed to operate a variable order filter of variable order for a plurality of each tone signal.

Appendix

The following is a program for distribution in Figure 7, encoded in the BASIC programming language described by James S. Co., "Basic BASIC," published by Hayden Book Co., Inc., Low Shell Park, New Jersey, 1970.

Claims (1)

An input signal filtering device consisting of digitally coded samples, comprising: receiving each digitally coded sample of an input signal and performing a M-th order filtering operation selected by a selection signal when M is an integer greater than 1, and selecting M A digital filter 102 for providing a filter completion signal together with an output signal after completion of the differential filter operation, and a filter start signal for continuously applying the sample to the digital filter 102 in response to each digitally encoded sample. And generating a continuous control signal including a selection signal and disabling the digital filter 102 to perform the K-dependent M-order filter operation when K is an integer greater than 1, wherein the continuous control signal follows each filter start signal. Including a stop signal to the continuous controller 101 is disabled by the stop signal and continues to operate again by the filter completion signal. Program tone multi-frequency receiver available, characterized in that a row consisting of that controller 101.

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