KR870004254U - Bus timing correction circuit - Google Patents

Bus timing correction circuit

Info

Publication number
KR870004254U
KR870004254U KR2019850010822U KR850010822U KR870004254U KR 870004254 U KR870004254 U KR 870004254U KR 2019850010822 U KR2019850010822 U KR 2019850010822U KR 850010822 U KR850010822 U KR 850010822U KR 870004254 U KR870004254 U KR 870004254U
Authority
KR
South Korea
Prior art keywords
correction circuit
timing correction
bus timing
bus
circuit
Prior art date
Application number
KR2019850010822U
Other languages
Korean (ko)
Other versions
KR880004480Y1 (en
Inventor
김태욱
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR2019850010822U priority Critical patent/KR880004480Y1/en
Publication of KR870004254U publication Critical patent/KR870004254U/en
Application granted granted Critical
Publication of KR880004480Y1 publication Critical patent/KR880004480Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
KR2019850010822U 1985-08-24 1985-08-24 Bus timing correction circuit KR880004480Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019850010822U KR880004480Y1 (en) 1985-08-24 1985-08-24 Bus timing correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019850010822U KR880004480Y1 (en) 1985-08-24 1985-08-24 Bus timing correction circuit

Publications (2)

Publication Number Publication Date
KR870004254U true KR870004254U (en) 1987-03-31
KR880004480Y1 KR880004480Y1 (en) 1988-12-20

Family

ID=19244914

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019850010822U KR880004480Y1 (en) 1985-08-24 1985-08-24 Bus timing correction circuit

Country Status (1)

Country Link
KR (1) KR880004480Y1 (en)

Also Published As

Publication number Publication date
KR880004480Y1 (en) 1988-12-20

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19981127

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee