KR870000619B1 - An elevator - Google Patents

Abstract

This invention describes a speed reduction controller for high-rise building elevators with the function of stopping elevator at desired floor. Especially this controller pulsates as it reflects alternating output of alternating generator connected to the shaft of driving motor, and a microprocessor, counting the number of pulses, generates stop signal and stops the elevator at the desired floor. And another advantage of this mechanism is fourty-eight subdivided steps making elevator passengers more convenient in operating elevators of high- rise buildings.

Description

Deceleration Control Device of Elevator

1A is a diagram for explaining another conventional device.

2 is a circuit diagram of the device of the present invention.

3 is a data table stored in FIG. 2g.

4 is an output voltage waveform diagram.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a deceleration control device for stopping a high-rise elevator, and more particularly, to pulse an AC output of an alternating current speed generator connected to an axis of a drive motor of an elevator, thereby counting such pulses to provide an elevator stop signal. It relates to a deceleration control device of an elevator controlled by a micro processor (Micro processor) for stopping at the side.

The dividing circuit for detecting the deceleration distance used in the elevator deceleration control apparatus of the conventional relay circuit is operated as shown in FIG. 1A when the elevator travels between multiple floors but before the deceleration point of the call floor or the target floor. The decelerating distance detecting device 3 provided on the upper side of the elevating body 4 and the shielding plate 2 provided on the wall 1 of each deceleration point hoisting path is not in a mechanically opposed state, and is in an inoperative state and thus deceleration control. In device 5

In this state, since the pulse output of the waveform shaping circuit 9 supplied to the counting circuit 7 is counted and supplied to the NAND combination circuit 10, the notch resistance frame 11 is described below according to the output of the NAND combination circuit 10. The voltage supplied to the drive motor of the elevator drops step by step and eventually stops at the final destination floor. However, such a configuration usually causes a voltage drop of 12 steps so that the passenger feels the deceleration of the lifting body, especially in the case of a high-rise elevator. Due to the sudden step-down of the lifting body, passengers feel dizzy, and at the same time, the circuit configuration is complicated and the manufacturing process takes a lot of time.

The present invention breaks down the deceleration step into 12 steps to 48 steps so as to avoid such a conventional disadvantage, so that even in the case of a high-rise operation elevator, passengers do not feel the deceleration strongly, so that the passengers have comfort in using the elevator and at the same time, the elevator is simple in construction. When the present invention will be described in detail with reference to the accompanying drawings as providing a deceleration control device of the following.

First, the detailed configuration and output characteristics of the conventional apparatus will be described with reference to FIGS. 1B and C as follows.

The deceleration distance detecting device 3 mounted on the upper and lower bodies of the shielding plate 2 mounted on the wall of each floor deceleration point is not mechanically opposed to the deceleration point of the target floor where the calling floor is located while the elevator is operating multiple floors. Since the deceleration position detection relay (not shown) is in the excited state. Therefore, since the deceleration position detection relay contact 91C ₁ is open in the distance detection coefficient circuit 7, the deceleration position detection transistor Q ₁ cannot be applied to the outside of the terminal AB _{9 in the} portion of FIG. 1g. It can be conducted. Therefore, the collector output (a) terminal is maintained as a "high signal" and is simultaneously connected to the reset terminal of the counting circuit (7), so that the binary counting circuit of the counting circuit (7) is disabled. The number of pulses input in 9) cannot be counted.

When the elevator reaches the deceleration point of the target floor with the gap in the above state, when the shield plate 2 and the deceleration distance detection device 3 mounted on the wall of the deceleration point elevation of each floor are mechanically opposed, the deceleration position detecting relay ( 91C) changes from excited to open. Accordingly, the contact 91C ₁ at the terminal AB ₉ is in a closed state, and when the transistor Q ₁ conducts, the collector output terminal a changes to the "low signal" state and at the same time the binary counting of the counting circuit 7 is performed. A "low signal" is applied to the reset terminal R of the circuit so that the counting circuit 7 enters the driving state (on state), and from this point on, the pulse inputted to the first counter 701 of the counting circuit 7 part is received. Start counting.

At the same time, the AC waveform output of the AC speed generator 8, which is connected to the induction lamp for driving an elevator in the machine room and rotates in proportion to the elevator speed, is converted into a waveform shaping circuit 9

Only the output C terminal (four pulses) of the first counter 701 of the counter circuit 701 in the counter circuit 7 portion (A, B, C, D) is used as the input signal of the NAND gate combination circuit 10, and the second counter Among the outputs A, B, C, and D of 702, an output terminal A (16 pulses) and an output terminal B (32 pulses) output terminal C (64 pulses) are output. The terminal D (128 pulses) was used as the input signal of the NAND gate combination circuit 10, and the output terminal A (of the outputs A, B, C, D) of the third binary counter 703 was used. Only 256 pulses) are used as the input signal of the NAND gate combination circuit 10.

Therefore, the NAND gate combination circuit 10 combines the input pulse numbers and makes a 12-step deceleration command notch voltage as shown in FIG. 3 to stop the elevator on the target floor. In detail the deceleration notch voltage generation process, when the elevator reaches the deceleration point of the target floor in which the elevator is called, the output terminal (a), which is the collector of the transceiver (Q ₁ ), changes to the "low" state, ₁ ) is connected to the terminal (b) of the NAND combination circuit 10 so that "low" changes the "high" signal, and again the output of the first inverting element Co is inverted from "high" to "low" signal and notched. The deceleration command voltage is reduced by the resistance value of the resistor RS ₁ of the resistance group 11, and the first deceleration notch voltage is generated as much as ⓐ part of FIG. 1c.

The deceleration command reference voltage is (RS ₁ ) The first resistor (RS ₁ ) is the low output signal ₁ of the inverting element (Co).

The second deceleration notch (step) voltage signal (Vs) of the output (C) terminal (C: 64 pulses) of the second counter (702) output (A, B, C, D) of the counting circuit (7) portion signal is input to the NAND gate element (a ₁₎ of NAND gate combination circuit (10) NAND gate element (a ₁₎ the output signal is at a "low" signal the first flip-flop device of the NAND gate combination circuit (10) (B _The output signal of the inverting output terminal Q _{1 of 1} ) changes from the "low" to the "high" signal state, and at the same time, the output voltage of the second inversion element C ₁ is inverted from the "high" to the "low" signal so that the notch resistor group ( The resistance RS ₂ of 11) is grounded, and the deceleration command voltage Vs decreases by the distribution voltage of the resistance value of RS ₂ so that the elevator second deceleration notch voltage signal is generated by step ⓑ in FIG. 1c.

The third deceleration notch voltage signal is output terminal A (16 pulses) output terminal B (32 pulses) output terminal C (64) of the output of the second counter 702 of the counting circuit 7 part. When the output signal of the number of pulses) is input to the NAND gate A ₂ of the NAND gate combination circuit 10, the NAND gate (A ₂ ) element output signal is 112 pulses (16 + 32 + 64 = 112 pulse combinations). Becomes a "low" signal and the output signal of the inverted output terminal Q ₁ of the second flip-flop element B ₂ changes from a "low" to a "high" signal state and at the same time the output voltage of the third inverting element C ₂ resistance is (RS ₃₎ is ground (GND) deceleration command voltage (V _s) in the "high" is inverted to the "low" signal notch resistance 11 is reduced as the distribution voltage of the value of resistance (RS ₃₎ of claim 1c Third deceleration notch voltage by step C in the diagram

In this way, the number of binary coefficient circuit output pulses in the counting circuit 7 is converted into NAND gate elements A ₃ → A ₄ → A ₅ → A ₆ → A ₇ → A ₈ → A by the number of pulse combinations of the NAND gate combination circuit 10. ₈ → A ₉ → A ₁₀ NAND gate output signal is inverted to “low” signal so that the corresponding notch resistor of notch resistor group 11 RS ₄ → RS ₅ → RS ₆ → RS ₇ → RS ₈ → RS ₉ → RS _{When the} deceleration command voltage decreases by ₁₀ resistance values, the speed is gradually decreased by the elevator deceleration notch voltage as shown in Fig. 1c, and the final deceleration notch (step) voltage signal is output from the output of the second counter 702 of the numerical circuit 7 part. The output signal of the terminal A (16 pulses) output terminal D (128 pulses) and the output terminal (256 pulses) of the third counter 703 is the NAND gate of the NAND gate combination circuit 10. When it is input to (A ₁₀ ), the NAND gate (A ₁₀ ) output signal becomes (low) signal when 400 pulses (16 + 128 + 256 = 400 pulses) When the output voltage of the membrane inversion element C ₁₀ is inverted from "high" to "low" signal, the deceleration command reference voltage decreases by the resistance value of the notch resistance group 11 by the value of (PS ₁₂ ) to decelerate by (b) in FIG. 1c. The notch voltage is generated, the voltage decreases to almost OV, and finally the deceleration command voltage drops as much as the resistance value of the notch resistance group 11 (RS ₁₁ ), so that the elevator stops at the target floor in which the elevator is called. Therefore, the deceleration command of the conventional relay control elevator stops the elevator on the target floor to be called by a fixed deceleration pattern, and in particular, only the elements for obtaining the deceleration notch (step) voltage are used, which increases the assembly process.

Referring to FIG. 2, the present invention will be described. A waveform shaping circuit (B) and a full wave rectifying circuit (D) are connected in parallel to the output of an AC speed generator coupled to an elevator drive motor. ) Connect the counter (C) to the AC generator to convert the AC output of the speed generator into a pulse waveform so that the counter (K) counts, and connect the analog digital converter (D) to the full-wave rectifier circuit (D). Change the output voltage of the generator to the digital signal, and connect the outputs of the counter (C) and the analog / digital converter (E) to the central processing unit (H) through the input / output device (B) Connect the output of ROM (memory) stored in the deceleration reference voltage memory device to the counter (C) to compare the speed of the AC speed generator (A) currently input, and compare the RAM (I) with the input / output device (B). To flow out the deceleration command stop signal. Being Turning to the operation and effect of this configuration as a configuration to control the elements of the entire apparatus as a central processing unit (H) as follows.

The present invention relates to a deceleration distance counting circuit of a microcomputer elevator applied to an 8-bit microprocessor system control method. Each floor deceleration point hoistway in FIG. Since the shielding plate 2 mounted on the wall and the deceleration distance detecting device 3 mounted on the lifting body 4 are not mechanically opposed to each other, the center connected to the input signal of the NOR gate element of FIG. The MWR signal 31 and the element selection signal terminal CS of the processing unit CPU (a) are simultaneously held in the "low" signal state, so that the output of the NOR gate element becomes a "high" signal and the distance detection """""" _{0 7} """""""""" _{0 7 0 7} "" _{0 7 1 4 1 4} ^{0 1 6 7} _{0 7} ""

When the first elevator deceleration command voltage (Vk) is compared with the deceleration reference speed command curve 7 at the time t _{1 by} comparing the value calculated by the central processing unit H with the first stop signal as shown in FIG. 4B. If the deceleration command error correction value is a little (Vi), the error correction value is given a lot so that the deceleration command curve of the current elevator approaches the deceleration reference speed curve, and the central deceleration unit pulse (160EA) signal is applied. By comparing the value calculated from) at time (t ₂ ), calculate the error correction value according to (Vk) (Vi), approach the deceleration reference curve, and generate the deceleration stop signal by the third factor (C). Accurate error deceleration command voltage can be generated by the error correction value by making it close to the reference speed and making the deceleration stop signal pulse nearly 48 steps in this order. Can be reduced.

As described above, according to the present invention, the deceleration of the elevator is set to 48 steps so that the occupant hardly feels the deceleration, and the configuration of the device is simplified to simplify the manufacturing process.

Claims (1)

In the elevator deceleration control device, the waveform shaping circuit (B) and the full-wave rectifying circuit (L) are connected in parallel to the output of the alternating current speed generator (A) axially coupled to the elevator drive motor. To connect the AC power output of the speed generator to the pulse waveform so that the counter (C) counts, and connect the analog digital converter (D) to the full-wave rectifier circuit (D). ), The output voltage of the analog signal is converted into a digital signal, and the outputs of the counter (C) and the analog digital converter (E) are connected to the central processing unit (H) through the input / output device (B). Connect the output of ROM, which stores the deceleration reference voltage memory value, to the counter (C) to compare it with the speed value of AC speed generator (A) currently input. Stop the deceleration command by connecting A control device for deceleration of an elevator, characterized in that the signal flows out but is decelerated in 48 steps by controlling the elements of the entire apparatus as a central processing unit (h).

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