KR860003158Y1 - Divided line generation circuit for moniter screen - Google Patents

Abstract

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Description

Division line generator circuit of monitor screen

1 is a circuit diagram and a display state of a conventional embodiment.

2 is a circuit diagram of the present invention.

3 is a waveform diagram of each part according to FIG. 2.

* Explanation of symbols for main parts of the drawings

1,2,4,5,6: 4-bit binary counter 3: Delay circuit

7: parallel / serial shift register 8: circuit for data selection

9: CRT controller 10: Video RAM

11: character generator 12: video control circuit

OR1, OR2: OA gate AD1, AD2: AND gate

IV1, IV2: Inverter NR1, NR2: Noah Gate

AD1: AND gate VH, HS: vertical and horizontal synchronization signal

CLK: Character clock signal HB: Vertical blanking signal

VID: Video signal M: Monitor

MA, RA: Memory and scan line address per line

The present invention relates to a dividing line generating circuit of a monitor screen for generating a dividing line for distinguishing a portion in which data can be written on a screen of a monitor, which is an output device of a computer, and a portion displaying an operating state of the computer.

In general, a monitor, which is an output device of a computer, displays characters and figures on a screen. As shown in FIG. 1 (b), a part (X) for writing or deleting data for the user to use the entire screen and the current operating state of the computer. Can be divided into a portion (Y) and the like. However, the display of characters or figures on the screen is displayed depending on whether or not bright dots (dots) composing characters or figures are made by moving the CRT's electron beam horizontally, and the entire screen is 80 columns x 25 rows. In this case, 12 scan lines are used for one row. Therefore, in order to divide the character lines to be displayed on the monitor screen into the X portions of 1 to 24 lines and the Y portions of 25 lines, the CRT controller 9 is controlled as software by configuring as shown in FIG. 1 (a). That is, the CRT controller 9 controls the vertical / horizontal synchronization signal VS (HS), the memory address MA and the scan line address per row RA under the control of a central processing unit (not shown). And the video generator 10 and the character generator 11, respectively, and then the central processing unit assigns an address to the video RAM 10 through the address bus switching circuit and then supplies the video RAM 10 through the data interface circuit. When data is recorded at the designated address, the CRT controller 9 then assigns an address to the video RAM 10 and outputs the designated data to the character generator 11, and the character generator 11 outputs the video ( 10) be discharged from Receiving the first scan lines per row address (RA) to be sent from the data and the CRT controller 9 is supplied to the output of the character dot matrix type with video control circuit 12. Then, the video control circuit 12 receives the vertical horizontal synchronizing signal VS (HS) of the CRT controller 9 controlled by software and outputs the video signal VID and the synchronizing signals to the monitor M as output signals. In this case, the monitor (M) screen is displayed in the X and Y parts as shown in FIG. 1 (b), but this is appropriate for writing data from 1 to 24 lines in the entire screen and 25 operating state display parts. As it is not separated, it becomes the screen unit. Therefore, when data is displayed on 24 lines, it is the screen because the data of operation state and data are not distinguished. Therefore, when the data is displayed on 24 lines, the data of operation state is displayed. There was a flaw in the time confusing the distinction between data.

The present invention forms a dividing line that can distinguish between a portion that can write data on a monitor screen and a portion that indicates an operation state on a computer, by a circuit constituted by a hardware. It is an object of the present invention to provide a dividing line generating circuit of a monitor screen for preventing the data from being mistaken for 24 rows of data.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, the character clock signal CLK is connected to one input terminal of the OR gate OR1, the clock terminal of the 4-bit binary counter 1, 2, and the clock terminal of the delay circuit 3, respectively. The binary counters (1) and (2) are connected to each other, and the output stages Q1 and Q2 are connected to the NAND gate ND1 and the OR gate OR2, and the clear stage of the 4-bit binary counter 1 and 2 is connected. Connected to (CL), the output terminal Q0 of the 4-bit binary counter 2 is connected to the input terminal D of the delay circuit 3, one input terminal of the AND gate AD1, and one input terminal of the NOA gate NR1. The output terminals Q1 and Q2 of the delay circuit 3 are connected to the other input terminals of the noble gate NR1 and the AND gate AD1, respectively, so that the horizontal synchronization signal HS and the horizontal retrace signal HB are connected. Generates. In addition, the output terminal of the OR gate OR1 is connected to the CRT controller 9, and the memory and the scan line address MA (RA) of the CRT controller 9 are the video RAM 10 and the character generator 11. Connected to the vertical synchronization signal VS is connected to the cree terminal CL of the inverter IV1 and the 4-bit binary counters 4 to 6, respectively, and the 4-bit output terminal of the AND gate AD1 is sequentially connected. It is connected to the clock terminal of the binary counters 4 to 6 and the clock terminal of the shift register 7, while the output terminal of the 4-bit binary counters 4 to 6 is connected to the input terminals of the inverter IV2 and the noar gate NR2. The output terminal of the noble gate NR2 is connected to the other terminal of the OR gate OR1 and the low stage LD of the parallel / serial shift register 7 and the control terminal CR of the data selection circuit 8, respectively. As long as one input terminal of the AND gate AD2 is connected to the shift register 7 to which the signal is connected to the input terminals D1 to D4. In addition, the output terminal of the AND gate AD2 having the output terminal of the NOA gate NR1 connected to the other input terminal is connected to the input terminal of the data selection circuit 8, and the data signal having the video signal VID of the character generator 11 connected thereto. A part (1 to 288 scan lines) connected to the output terminal of the circuit 8 to generate data by dividing lines between 289 to 292 scan lines while counting 304 scan lines; Differentiating parts (293 to 304 scan lines) indicating the operation status of the computer are distinguished.

2 is a circuit diagram of the present invention, and a dividing line for distinguishing a portion (X) for writing data onto a monitor screen and a portion (Y) for indicating an operation state of a computer is provided by a circuit composed of hardware. In order to form, the CRT controller 9 generates only the vertical synchronizing signal VS and the address signal MA and RA for the image signal, while the horizontal synchronizing signal HS is generated by using the character clock signal CLK. It is generated through the bit binary counter (1) (2) and the delay circuit (3).

Then, the character clock signal CLK input to the CRT controller 9 is stopped for a predetermined time in order to form a dividing line. Therefore, the operation of the CRT controller 9 is stopped to monitor the image signal of the dividing line made by this circuit. Since the character clock signal CLK is supplied to the CRT controller 9 after being sent to the CRT controller 9, a signal as shown in FIG. 3 (l) is transmitted to the monitor M. FIG.

That is, in the present invention, the character clock signal CLK as shown in FIG. 3 (a) is applied to one input terminal of the OR gate OR1, the clock terminal of the 4-bit binary counter 1, 2, and the clock of the delay circuit 3. Since the character clock signal CLK, which is supplied to each stage and has passed through the OR gate OR1, is supplied to the character clock stage of the CRT controller 9, the memory address MA and the scan line address per row RA are provided in the video. It is supplied to the RAM 10 and the character generator 11, respectively, the character generator 11 receives the data output from the video RAM 10 and the scan line address (RA) per line transmitted from the CRT controller 9 receives an image signal (VID) is supplied to one input terminal of the data selection circuit (8). In addition, the vertical synchronizing signal (VS) transmitted from the CRT controller 9 is maintained in a high state in a normal state, and is changed to a low state when synchronized to the next change plane in one screen, and then remains high again after a predetermined time. .

At this time, the vertical synchronous signal VS of the low state is supplied to the cree stage CL of the 4-bit binary counter 4-6, and is changed to the high state through the inverter IV1 and the oragate OR2, thereby changing to 4-bit 2. Since the 4-bit binary counters (1) (2) (4-6) are creeped because they are supplied to the clear stage (CL) of the jin counter (1) (2), the vertical synchronization signal (VS) is in a high state. 4 bit binary counter (1) (2) (4 ~ 6) starts to operate. On the other hand, while the above-mentioned 4-bit binary counters 4 to 6 are cleared, the output signal is supplied to the inverter IV2 and the noar gate NR2 in a low state, that is, the 4-bit binary counter 4 and 5 (5). Output signal of the 4-bit binary counter 6 is applied to the input terminal of the NOA gate NR2 as the high state through the inverter IV2 while the output signal of the NOR is applied to the input terminal of the NOA gate NR2 as a low state. The output signal of the gate NR2 is a control signal in a low state, and one input terminal of the OR gate OR1 and the low stage LD of the parallel / serial shift register 7 and the control terminal CR of the data selection circuit 8 are output. Are each supplied.

Then, when the character clock signal CLK is supplied to the clock terminal of the 4-bit binary counter (1) (2) and the delay circuit (3), the 4-bit binary counter (1) (2) is counted as 102. The 102 coefficients are kept low for the 80-character clock signal when the output signal of the 4-bit binary counter (2) displays data on the screen at the start of the count, and then the high state is maintained for the 18-character clock signal, and then the horizontal scan signal. The count is repeated in the 4-bit binary counter (1) (2) to remain low during the 4-character clock signal, which is the return time of.

That is, if the 4-bit binary counter (1) (2) counts to 102 and then the output signal (Q1) (Q2) is supplied to the NAND gate (ND1) as a low state, the output is a high state oragate (OR2) Since the output signal of the OR gate OR2 is supplied to the cree stage CL of the 4-bit binary counter (1) (2), it is creeped, and the counters (1) (2) are numbered 1-84. After counting, the output signal Q0 of the counter 1 is held high 85 to 102 times as a high state and then changed to a low state after which the output signal Q0 of the 4-bit binary counter 2 is A waveform as shown in FIG. 3 (b) is supplied to the input terminal D of the delay circuit 3 and one input terminal of the AND gate AD1 and the NO gate NR1. Then, the outputs Q2 and Q1 of the delay circuit 3, which are delayed for a predetermined time, are delayed by the two-character clock signal CLK as shown in the third (c) and the third (d) and the AND gate AD1. Since the output signal of the AND gate AD1 is applied to the other input terminal of the NOA gate NR1, the output signal of the AND gate AD1 is changed to the waveform shown in the diagram (e) as the horizontal synchronization signal HS, so that the 4-bit binary counter 4-6 and the shift register Supplied to the clock terminal of (7), and the output signal of the no-gate NR1 is changed to a waveform such as the third (f) as the horizontal retrace signal HB, and applied to one input terminal of the AND gate AD2. .

That is, since the low state signal is applied to the AND gate AD2, its output is applied as a low state to one input terminal of the data selection paper circuit 8, whereby the signals of the third (e) and the third (f) The image signal VID through the data selection circuit 8 is supplied to the monitor M by receiving the horizontal retrace signal of the third (g) and the horizontal synchronous signals and the third (j) as listed above. The data is written in the X part of the figure.

On the other hand, the horizontal synchronizing signal HS which is the output signal of the AND gate AD1 is supplied to the clock terminal of the 4-bit binary counters 4, 5 and 6, so that the counter 4-6 is operated. The waveform as shown in FIG. 3 (g) is counted in the 4-bit binary counters 4, 5, 6 and counts up to 304. FIG. Since 304 is a horizontal line of twelve horizontal lines of 25 characters each, 304 refers to a value of 25 × 12 = 300 horizontal lines plus division lines 4.

After the vertical synchronization signal VS of the CRT controller 9 drops to a low state and then changes to a high state, the horizontal synchronization signal HS which is the instant when all 24 rows of data lines are displayed (that is, the third (g) degree) is displayed. Output signal of the 4-bit binary counter 4-6 is applied to the noar gate NR2 as a high state until a time is 24x12 = 288). When the input signal of the gate OR1 is supplied to the low stage LD of the parallel / serial shift register 7 and the control terminal CR of the data selection circuit 8, the video signal IVD is used for data selection. The circuit 8 writes data in the X part of FIG. 1 as shown in FIG.

After that, the four horizontal synchronous signals HS, which is the time when the dividing line is generated, keep the output signal of the NOA gate NR2 high until 289 to 191, and then 12 horizontal synchronous signals HS are supplied to the Y part again. Is maintained, the output signal of the NOR gate NR2 is kept low.

That is, while the output signal of the 4-bit binary counter 4 and 5 is supplied to the noar gate NR2 in a low state, the output signal of the 4-bit binary counter 6 is supplied to the inverter IV2 in a high state. Since the signal in the low state is supplied to the NOA gate NR2 as an inverted signal, its output is changed to the high state as shown in the third (h), and accordingly, the moment when the output signal of the NOA gate NR2 becomes the high state Since the other input terminal of the gate OR1 is in a high state and the character clock signal CLK is not supplied to the CRT controller 9, the CRT controller 9 stops the operation, and the split line appears on the screen. Thereafter, the output signal of the 4-bit binary counter 6 is changed from the low state to the high state and is supplied to the inverter IV2. When the inverted signal is supplied to the noar gate NR2, the output of the noar gate NR2 is supplied to the third. As shown in (h), the state is changed to the low state, and from this time, the CRT controller 9 starts operation again to display the operation state of the computer on the screen.

On the other hand, even when the output signal of the noah gate NR2 becomes high, the horizontal synchronizing signal HS and the horizontal retrace signal HB continue to be generated and parallel as shown in the third (g) and the third (j) diagrams. Since the parallel signal is loaded to the input terminals D1 to D4 of the serial shift register 7, the output signal Q is connected to the output terminal Q by the horizontal synchronization signal HS which is the output signal of the AND gate AD1. A signal shifted in series is sent out, and the third (i) diagram signal is sent out to the AND gate AD2. At this time, by changing the data loaded to the input terminals (D1 ~ D4) of the shift register (7), in the case of the (1111) signal, all four appear as a line, or if the third line appears only the third line Determines the thickness of the dividing line.

The present invention is drawn on the assumption that the data is loaded as shown in FIG. 3 (i). In this case, only two out of four appear as a dividing line, and the third (i) also shows a signal and a third ( j) also a signal is inputted to the AND gate AD2, and its output is changed to the signal of FIG. 3 (k) and supplied to one input terminal of the data selection circuit 8, wherein the control of the data selection circuit 8 is performed. Since the signal of the high state is supplied to the stage CR, the signal of the third (k) degree is supplied to the monitor M as shown in the third (l) figure.

That is, the third (k) signal, which is the output signal of the AND gate AD2, and the video signal VID transmitted from the character generator 11 under the control of the CRT controller 9 are converted into the data selection circuit 8. The third input (h), which is an output signal of the NOA gate NR2, is also supplied to the input terminal, and the input data is sorted out as the signal is supplied to the control terminal CR of the data selection channel 8. ) Will be supplied.

Therefore, when the signal (3) is supplied to the control terminal CR of the data selection circuit 8 in the low state, the video signal VID generated by the control of the CRT controller is supplied to the monitor M. (If the signal of FIG. 3 (h) is supplied in the high state, the signal of FIG. 3 (k) is supplied to the monitor M. Therefore, the three dividing lines are sandwiched between the X and Y portions shown in FIG. It is easy to distinguish between the data writing part used by the user and the part representing the operation state of the computer.

As described above, the present invention can be formed by a circuit composed of hardware that divides the part for writing data on the monitor screen and the part for displaying the operation state of the computer visually and easily. There is an advantage that the user can easily distinguish between the area that can be used by the user and the area that displays the operation state of the computer, thereby preventing visual confusion and promoting effective use.

Claims (1)

The output stages Q1 and Q2 of the 4-bit binary counter 1 and 2 for counting the character clock signal CLK during the horizontal synchronization frequency are connected to the CREE stage through NAND and OA gates ND1 and OR1. CL is connected, and the output terminal Q0 of the counter 2 is connected to the input terminal of the delay circuit 3 and the AND and NOA gates AD1 and OR1, and 4 bits are connected to the output terminal of the AND gate AD1. The clock terminal of the binary counters 4 to 6 and the parallel / serial shift register 7 is connected, while the inverter IV2 and the noar gate NR2 are connected to the output terminals Q1 to Q3. ) Is connected to the output terminal of the OR gate and the lower stage LD of the shift register 7 and the control terminal CR of the data selection circuit 8, and the shift registers to which the input terminals 1D to D4 are connected. The data selection circuit 8, to which the video signal VID is supplied, is connected to the AND gate AD2 to which the output terminal of (7) and the output terminal of the NOA gate NR1 are connected. Hayeoseo division of the display screen to the user and the dividing line between the section that displays the writing portion and the operation state of the computer data that are available that can eojil ray generating circuit.