KR860003126Y1 - Phase control synchronizing device for indulating test - Google Patents

Abstract

No content.

Description

Timer phase control synchronizer for insulation test

1 is a schematic opening diagram of a timer phase control synchronization device for insulation test according to the present invention.

2 is an opening diagram of a drive circuit of the synchronization device of FIG.

3, 4 and 5 are detailed circuit diagrams of FIG.

6 is a timing chart for explaining the registration signal detection and synchronization output signal generation according to the present invention.

7 is a state diagram for generating a trigger impulse in a state where the peak value of the synchronous AC input signal and the synchronous DC output signal of FIG. 6 are synchronized.

The present invention is a kind of insulation test of specimens such as GIS (Gas Insulation Switchgear), Circuit Breaker, and Disconnection Switch, which are ultra high and high voltage (345KV) equipment. TECHNICAL FIELD The present invention relates to an insulation test synchronous device used in a test for confirming phase by simultaneously applying an) and an impulse voltage, and more particularly, to a timer phase control synchronization device for an insulation test configured to prevent a malfunction.

In general, the timer phase control synchronization device for insulation test adjusts the phase so that the DC value becomes the negative peak when the AC value is the positive peak, and the DC value becomes the positive peak when the AC value is the negative peak. Insulation test for determining whether the above-described ultra-high voltage equipment can withstand the insulation test performed in the state of the pole (Fig. 7). This device is also used in short-circuit current tests such as transformers and switchboards to find the peak current by adjusting the phase. However, although it has not been developed in Korea yet, it depends on the foreign insulation test synchronous device, but the synchronous output signal of the foreign synchronous device detects the voltage of the synchronous power supply at the same time as the start signal input and sets the starting point. Since the trigger point is set by delaying the number, when the voltage of the synchronous power supply changes, the synchronous time also changes, and the trigger time setting itself is unstable due to the delay caused by the time constant, so it cannot be precisely triggered. Rather, there is a disadvantage of malfunction because more than 20% of the trigger.

Therefore, the object of the present invention is to detect the synchronous start point at voltage zero (Zero) as shown in FIG. 6 so as to eliminate the disadvantages described above, and to operate the external device after a predetermined set time by the timer controller. By providing a synchronous control device by control, it is always possible to trigger the insulation without fail by synchronously without changing the synchronous starting point according to the voltage change.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of the connection between the test object and the test object. Referring to the circuit configuration of the present invention, for example, the synchronous input signal detected by the input transformer 1 of the high voltage AC input 3300V may be zero. After detecting the phase zero (figure 5) of the alternating current value in the detection circuit 4, the time setting switch 5 sets the coexistence time of the synchronous device, that is, the synchronous phase signal. Synchronization time adjustment range can be adjusted from 0-99999㎳ and 0-99999㎲ (Fig. 6) according to the switch changeover. The synchronous phase signal configured here is displayed on the time display device 6 and is applied to the trigger switching circuit 2 via the drive circuit 7. Here, when the synchronization time, i.e., the phase is coincident (Fig. 7), by the adjustment of the time setting switch described above, the trigger signal is input so that the switching circuit 2 is turned on to obtain the synchronous voltage, that is, the high voltage impulse. For example, since it is applied to a GIS breaker, a disconnector, etc., it is comprised so that insulation acceptance test can be carried out in the phase to obtain.

In order to more clearly understand the configuration of the synchronization device configured as described above, the configuration of the insulation test synchronization device of FIG. 1 will be described in more detail with reference to FIG. The synchronous input signal amplifying circuit 11 amplifies the synchronous input signal detected by the instrument transformer of the input transformer to a constant voltage, and the zero detection circuit 12 obtains a voltage zero and converts it into a digital pulse and outputs it. . This output pulse is configured to generate only when rising from the voltage zero point. The pulse generated here becomes a zero detection signal, that is, a zero point detection signal (Fig. 6) of the synchronization input signal. This zero detection signal is applied to the start switch circuit 13, and 10 pulses are counted at a decimal counter in the start switch circuit 13 in synchronization with the high level signal outputted at the same time that the start switch circuit 13 is turned on. The synchronous input signal stabilization circuit 14 outputs the synchronous input signal stabilized at a high level.

On the other hand, the reference oscillator 15 is a 10 MHz oscillator and is applied to the oscillator output line switch circuit 17 through a divider 16 which generates 10 MHz oscillation output and divides the frequency. The oscillator output selection switch circuit 17 outputs a pulse of 1 MHz or 1 KHz by a switch selection of a decimal counter that outputs a pulse of 1 MHz, i.e., 1 kHz and 1 kHz, ie 1 kHz. Then, the stable synchronous input signal output from the synchronous input signal stabilization circuit 14 described above and the selected pulse of 1 MHz or 1 KHz output from the oscillator output selection switch 17 are counted by a decimal counter of the synchronous signal count circuit 18. 6 and input to the comparison circuit 19. At this time, the comparison circuit 19 operates as much as the numerical value set by the digital time setting switch circuit 20 and compares the input synchronizing signal until it is equal to the set numerical value and outputs the synchronizing signal at the coincidence time point (FIG. 6). (Fig. 7) is applied to the synchronization signal on / off control and the output amplifier circuit 21.

The synchronous signal on / off control and output amplifier circuit 21 controls and stops the operation of the reference oscillator 15, while the synchronous signal output compared in the above-described comparison circuit 19 is delayed by a timer for a predetermined time. Hold and then off.

On the other hand, since the comparison value of the comparison circuit 19 is displayed on the time table market value 22, it can be arbitrarily controlled by the digital time setting circuit 20. FIG.

The opening degree of FIG. 2 will be described in more detail with reference to the detailed circuit diagrams of FIGS. 3, 4 and 5 as follows.

First, referring to FIG. 3, when a synchronous input signal is input from the high voltage test power supply (AC) input transformer 1, a pseudo-square wave of a constant voltage is generated by the zener diodes ZD1 and ZD2 through the resistor R7. It is entered in 3. On the other hand, the terminal 2 of the comparator IC15 is applied with a voltage near the zero voltage set by the variable resistor VR1 and compared with a pseudo square wave to form a complete square wave. This shaped square wave is amplified by a constant voltage at the amplifying transistor Q1 when inputted to an input synchronous signal zero detection circuit 4 composed of transistors Q1, Q2 and Q3 condensers C3 and resistor R16, and a giraffe digital converter IC20. Phase detection is performed by transistor Q2 and the voltage zero is obtained by the differential circuit of capacitor C3 and resistor R16. Digital detection occurs only when the square wave rises at the zero potential of the square wave through transistor Q3 and digital converter IC20. The zero point is powered as in FIG.

This zero detection signal outputted through the digital converter IC20 is input to one end of the non-gate IC4 of the synchronous input signal stabilization circuit 14, at which time the start switch SW1 of the start switch circuit 13 is turned on and at the same time through the inverter IC1. When the high level signal is output from the output terminal 11 of the counter IC5 after 10 cycles, that is, 10 pulses have elapsed as shown in FIG. 6, the decimal counter IC5 is synchronized with the high level signal input to the other end of the non-gate IC4. When inverted through IC6 and a low level is input to terminal 6 of flip-flop IC7, terminal 7 outputs a high level and sends it to the non-gate IC19 while feeding back to one end of the non-gate IC2 of the synchronous input signal stabilization circuit 14. To stabilize the synchronization input signal.

On the other hand, the reference oscillator 15 is a 10MHz oscillator, the oscillation output of which is input to the first terminal of the non-gate IC12 and counted on the second terminal. off. When the high level is input from the in (Count On off In) terminal through the inverter IC22, the high level is output to the 9th terminal of the flip-flop IC17 and input to the 2nd terminal of the non-gate IC12. Shows an oscillating output of 10MHz. This oscillation output is sent to the divider 16 consisting of the decimal counters IC13, IC14, IC15 and IC16. When the 11th terminal of the decimal counter IC13 has a pulse of 1 MHz, i.e., 1 ㎲, the decimal counters IC14, IC15, And IC16 outputs a pulse of 1 KHz, that is, 1 kHz, at terminal 11 of IC16. This 1KHz output pulse is input to the 2nd terminal of NANDGATE IC9, and the 1st terminal is the 2nd terminal of NANDGATE IC8 by selecting ㎲ or ㎲ count unit by selection switch SW3 of output selection circuit 17. At the same time, the low level is input to the terminal 1 of the non-gate IC9 through the inverter IC10, and a pulse of 1 KHz is output to the terminal 2 of the non-gate IC11 through the output terminal of the IC9. On the other hand, when the output 1MHz of the 11th terminal of the decimal counter IC13 is input to the 1st terminal of the non-gate IC8, and the output of the 3rd terminal is inputted to the 1st terminal of the non-gate IC11, the 3rd end of the nondgate IC11 is 1MHz or 1KHz. The selected pulse is output.

This 1KHz output pulse is output from the 7th terminal of the flip-flop IC7 and the selected pulse of 1MHz or 1KHz is input through the NANDGATE IC19 to the count output terminal of the synchronization signal counter circuit 18. Is sent to (Count In) (figure 4).

The count input signal starts counting as shown in FIG. 6 by the decimal counters IC39, IC38, IC37, IC36, and IC35 of the synchronization signal counter circuit 18, and outputs the count to the respective output terminals QA, QB, QC, and QD. Output, the outputs are set in the switches SW8, SW9, SW10, SW11, and SW12 of the time setting switch circuit 20 and the comparators IC40, IC41, IC, 42, IC43 and IC44 of the comparison circuit 19, respectively. The pulse is continuously input until the same value is compared with the set value. At the time of coincidence, terminal 1 of the comparator IC44 becomes low level. Therefore, the low level is output from the 9th terminal of the flip-flop IC17 (Fig. 3). Since the oscillation output of 10MHz is stopped because it is applied to terminal 3 of IC12, the low repulse is also input to the diode D11 of the synchronous signal on-off control and output amplifier circuit 21 of FIG. 5 and is differentiated by the capacitor C2 and the resistor R56. Through timer IC Since the end signal is applied to 23, the timer IC23 turns off after synchronizing the output of the synchronization signal for the time set by the variable resistor. The synchronous signal output, which is output for a set time, is amplified by the amplifying transistor Q11 to trigger the switching circuit 2 of FIG. 1 as a synchronous impulse signal as shown in FIG. .

By constructing the synchronous device in this way, the instability of the synchronous point of time caused by the voltage change of the synchronous input power source is eliminated, thus preventing malfunctions during the insulation test, and by accurately triggering the condition of the insulation of the EUT, it is possible to accurately determine the state of the insulation. The practicality is enormous because it can be applied to the testing of various heavy electric equipments of ultra high pressure.

Claims (1)

The synchronous input signal amplifying circuit 11 for amplifying the synchronous input signal detected by the known input transformer 1 to a stable voltage obtains a voltage zero and outputs a converted digital pulse only when rising from the voltage zero. ), The zero detection circuit 12 is connected to the synchronous input signal stabilization circuit 14 for a predetermined time delay to stabilize the zero detection signal through the start switch circuit 13, while the reference generator 15 at 10 MHz is connected. Is connected to the oscillator output selection switch 17 to output the selected oscillation output through the divider 16, and the outputs of the synchronous input signal stabilization circuit 14 and the oscillator output selection switch 17 are synchronized signals. The counting circuit 18 starts counting after the predetermined time delay, and compares with the set value of the digital time setting switch circuit 20 to generate a trigger impulse at a point of time matched. The key is connected to the comparison circuit 19, while the comparison circuit 19 controls the synchronization signal on / off control and the output amplifier circuit 21 to control its output for controlling the reference oscillator 15 and the switch circuit 2. Timer phase control synchronization device for insulation test, characterized in that connected to the reference oscillator (15) through the trigger to switch circuit (2) through.