KR860000613B1 - Video display apparatus - Google Patents

Abstract

A multi-beam colour display minimizes the miss-convergence at less than 0.2 mm in the direction of horizontal deflection. The display system comprises a colour CRT with in-line type 3 electron guns and deflection yoke assembly, a pattern signal generator providing a digital signal for dot image, and a signal phase controller. The signal phase controller adjusts the phase of digital colour signal in response to the corresponding quantity of the miss-convergence in the direction of horizontal deflection, and provides the controlled signal to the colour CRT.

Description

Video display

1 is a schematic diagram showing an internal configuration of a CDT used in a video display device according to the present invention.

2 is a diagram showing an example of a misconvergence pattern.

3 (a) to 3 (c) are views for explaining a relationship between three color video signals and color error adjustment of a display screen in a conventional video display device.

4 (a) and 4 (b) are diagrams for explaining the relationship between three color video signals and color error of a video display device according to the present invention.

5 is a block diagram showing a configuration example of a video display device according to the present invention.

FIG. 6 is a block diagram showing the structure of an example of a figure image generating apparatus in the video display device of FIG.

7, 9 and 11 are circuit diagrams showing the structure of another example of the phase control device in the video display device of FIG.

8, 10 and 12 are diagrams for explaining various misconvergence patterns in the present invention.

* Explanation of symbols for main parts of the drawings

(2): Input terminal (4): Electron gun

(6): deflection yoke (8): shadow mask

(10): fluorescent surface 12a, (12b), (12c): electron beam

(14), (16), (18): luminance lines 22a-22g: horizontal scan lines

(24), (25), (26), (27), (28): Bright point (30a), (30b), (30c): Video signal pulse

(37): Signal generator 32a, 32b, 32c: Bright spot

(38): phase control device (34a), (34b), (34c): video signal pulse

(40): clock generator (39): multiple non-chromatic cathode ray tube (CDT)

(44a), (44b), (44c): Dot memory (46a), (46b), (46c): Parallel-to-serial converter

(50), (52), (54), (56), (58), (60): Input terminal

(62), (64), (66), (81), (83), (102), (106): delay circuit

(62a), (62b), (62c), (62d), (64a), (64b), (66a), (66b), (66c), (66d), (81a) to (81f), (83a )-(83c), (85a)-(85f), (102e), (102h), (106e)-(106h): flip-flop

(68), (70), (72), (88), (90), (92), (108), (112): multiplexer

(74): Counters 76, 96, and 116: Address memory

(78), (80), (82): amplifiers (102a)-(102d), (106a)-(106d): delay elements

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color television display, and more particularly to a video display using a cathode ray tube having an inline electron gun.

In a video display device using multiple beam color cathode ray tubes (hereinafter referred to as CDT) to display text or graphic output information based on a digital signal representing a text image or a graphic image, an electron beam emitted from three electron guns is a CDT. It is required to make sure that all the points on the fluorescent surface of? The degree of matching in such a video display device should be more precise than in the case of a conventional general color television receiver, and the amount of miscon vertex is often desired to be 0.2 mm or less. In order to realize such a small amount of misconversion, a high precision is required for CDT and deflection yoke conventionally, which has caused the cost to increase.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a main object of the present invention is to provide a video display device capable of displaying information in which the amount of misconvergence is localized despite its simple configuration. Still another object of the present invention is to provide a video display device capable of minimizing misconvergence in the horizontal deflection direction.

In order to achieve the above object, a video display device according to the present invention includes a color cathode ray tube including a deflection yoke assembly and three inline electron guns, and a dot image displayed on a display screen of the color cathode ray tube. In the horizontal deflection direction, a graphic image signal generator for generating a digital color video signal pulse and a phase-controlled signal to a color cathode ray tube in response to the input of the digital color video signal output from the graphic image signal generator A video display device comprising a phase control device which operates to shift phases of digital color video relative to each other in accordance with an amount corresponding to the amount of convergence.

The principle of the present invention will be described first with reference to FIGS. 1 to 5, and then a suitable embodiment of a video display device according to the present invention will be described in detail.

1 is a schematic cross-sectional view showing the internal structure of the CDT used in the video display device according to the present invention. In FIG. 1, in response to the color video signal input to the input terminal 2, three color electron beams 12a, 12b and 12c are emitted from the electron gun 4, and by the deflection yoke 6; After deflection, it passes through the shadow mask 8 and impinges on the fluorescent surface 10. At this time, all of the respective electron beams 12a, 12b, 12 corresponding to the three colors, ie, red, green, and blue, are simultaneously emitted from the electron gun 4 and are required to be fully converged on the fluorescent surface 10. have. Therefore, high accuracy was required for the CDT and the deflection yoke 6. In cathode ray tubes with inline electron guns, it is already well known that the misconversion is almost zero when the deflection yoke, which generates a pincushion type horizontal deflection magnetic field and a barrel vertical deflection magnetic field, respectively, is combined.

However, in reality, when the electron beam is deflected over a wide angle range, it is extremely difficult to realize a state of zero misconvergence with satisfactory reproducibility over the entire area of the display screen. This is because the amount of misconvergence at various locations on the display screen is closely related to each other during horizontal deflection, vertical deflection, and corner deflection. It is not easy to change the amount of misconvergence without it.

On the other hand, if a certain amount of residual misconvergence exists by abandoning efforts to reduce the misconvergence to zero at all positions on the display screen, the deflection magnetic field distribution is formed so that the residual misconvergence has a specific pattern of required. It is also well known that it is relatively easy to adjust.

The present invention has been made in view of this fact and uses a deflection yoke having a magnetic field distribution that generates a constant misconvergence pattern. 2 shows a residual misconvergence pattern suitable for the video display device according to the present invention. In Fig. 2, (14), (16) and (18) respectively show red, green and blue luminance lines on the CDT display screen, and misconversion in the vertical deflection direction, i.e., misses in the luminance lines in the horizontal direction. The convergence is almost zero throughout the display screen, and the misconvergence in the horizontal deflection direction, that is, the misconvergence of the luminance line in the vertical direction is almost halfway between the luminance lines of the red (14) and blue (18). It can be seen from the misconvergence pattern shown in FIG. 2 that the luminance line of green 16 exists. Further, it can be seen that there is almost no color error adjustment at the center of the display screen, and color error adjustment is increasing toward the end portion in the horizontal deflection direction. The deflection yoke generating the horizontal deflection magnetic field which becomes the pincushion magnetic field and the vertical deflection magnetic field which becomes the barrel magnetic field is installed in the color cathode ray tube, and the purpose of the magnetic field control is to install the magnet piece in the cathode ray tube and intentionally deform the magnetic field. It is generally known that a misconvergence pattern can be easily obtained when correcting coma aberration resulting.

When the misconvergence pattern shown in FIG. 2 is observed in detail, for example, the misconvergence at the position indicated by (20) is red 12a simultaneously emitted by the electron gun 4 at a time t. It is a fact that electron beams of green 12b and blue 12c reach the fluorescent surface 10 and cause color misalignment in the horizontal direction. Thus, on the contrary, the three luminance lines 14, 16 and 18 appear to overlap each other at the position 20 on the fluorescent surface 10 and as a result, the electron beams 12a and 12b of red, green and blue. If (12c) is emitted at a relatively delayed time, i.e. in the case shown the blue electron beam 12c is emitted earlier than the green red beam 12b and the red electron beam 12a is released later than the green electron beam 12b. This results in the same result as no misconvergence exists.

The above process will be described in more detail with reference to FIG. 3 (a). FIG. 3 (a) shows the display of the white letter "AN" on the screen, for example, in which three color electron beams are superimposed. In the same figure, (22a)-(22g) is a horizontal scan line, and a black point is the bright point on these horizontal scan lines 22a- (22g).

For example, conventionally, as shown in (b) (c) and (d) in FIG. 3 (b), the video signal pulses 30a, 30b and 30c are separated from the electron gun at time t ₁ . A bright spot was obtained by emitting an electron beam. That is, (b) (c) and (d) of FIG. 3 (b) are video signal pulse waveforms corresponding to red, green, and blue on the horizontal scan line 22c, respectively, and are at a high level. Electron beams are emitted in response to (30b) 30c. As is apparent from FIG. 3 (b), the video signal pulses 30a, 30b and 30c of three colors have the same phase as that by the conventional method. The waveform shown in (a) of FIG. 3 (b) represents a horizontal synchronization signal. The bright spots 24, 25, 26, 27, and 28 on the horizontal scan line 22c of FIG. 3 (a) are each time shown in (b) (c) (d) of FIG. 3 (b). It is represented by red, green and blue video signal pulses applied at (t ₁ ) (t ₂ ) (t ₃ ) (t ₄ ) (t ₅ ). In FIG. 3 (a), 3 (b) and 3 (c), the bright points corresponding to the video signal pulses are shown on the same time axis for convenience of description.

In the presence of misconvergence, the electron beam emitted simultaneously from the electron gun does not reach the same point on the fluorescent surface, for example, in three colors, red green and blue, as shown in Figure 3 (c). Corresponding electron beams form bright spots 32a, 32b and 32c on the same horizontal scan line, respectively, so that the letters " AN "

In stark contrast to the conventional method, the bright spots of the three colors generated on the fluorescent surface by applying these three color video signal pulses at different times from one another by the present invention do not change positionally with respect to each other. 4 (a) is a video signal pulse waveform according to the present invention, and in FIG. 4 (a), the horizontal synchronization signal is (a) and the video signal pulses corresponding to red, green and blue are respectively (b) (c). ) And (d). As is apparent from FIG. 4 (a), the red video signal 34a is delayed in phase, for example, one clock cycle, with respect to the green video signal 34b, and the blue video signal 34c is delayed with respect to the green signal. It is ahead of a preset phase, for example one clock cycle. As a result, the video input signal is applied to the color cathode ray tube on the fluorescent surface by registering the clock of the clock signal corresponding to each pixel and the clock signal. Accordingly, red, green and blue bright spots generated on the fluorescent surface by the electron beam emitted in response to the application of the video signal pulses 34a, 34b and 34c shown in FIG. As shown in (b), accurate convergence results in a bright spot without color misalignment. The same applies to the other bright spots, and the letter "AN" without color misalignment can be displayed clearly.

Embodiments of the video display device according to the present invention will be described in detail below based on the principles described above.

As shown in FIG. 5, a video display device according to the present invention comprises a known figure image signal generator 37 for generating a digital color video signal pulse representing a dot image displayed on a display screen, and the figure image. A phase control device 38 for controlling the phase of a digital color video signal pulse representing an image (dot image) applied from the signal generator 37, and in FIG. 1 connected to the output side of the phase control device 38; It consists of the CDT 39 as shown. As already described with reference to FIG. 2, the CDT 39 includes at least one deflection yoke generating a horizontal deflection magnetic field acting as a pincushion magnetic field and a vertical deflection magnetic field acting as a barrel magnetic field, and an intentionally deformed magnetic field. In order to correct the comer aberration caused, a magnet piece for the purpose of magnetic field control for generating residual misconvergence as shown in FIG. 2 is included.

FIG. 6 is a block diagram showing a structure of one form of the figure video signal generator 37 shown in FIG. 5, and FIG. 7 is a structure of one form of the phase control device 38 shown in FIG. A circuit diagram is shown. In FIG. 6, the clock generator 40 is used for synchronizing the digital video signal pulses, and one clock period generates the clock pulse CK which determines the interval between the image dots shown in the horizontal scanning direction. In response to the application of the clock pulse signal CK from the clock generator 40, the control circuit 42 controls the horizontal synchronizing signal HS and the vertical synchronizing to control the reading of data from the dot memories 44a to 44c. When the signal VS is generated, a read pulse signal applied to the dot memories 44a, 44b and 44c is also generated, and these dot memories 44a, 44b and 44c are respectively red, green and blue. Memorizes the digital video signal. In other words, data relating to red, green and blue of the dot image displayed on the CDT 39 are stored in the dot memories 44a, 44b and 44c corresponding to each dot. The control circuit 42 applies one read pulse for every eight clock pulses CK for each of these dot memories 44a, 44b and 44c. When such a read pulse is applied to each of the dot memories 44a, 44b and 44c, digital video signal pulses corresponding to eight adjacent dots of the horizontal scan line are simultaneously read out in response. Accordingly, the digital data corresponding to the eight dots are sequential from the dot memories 44a, 44b, 44c in response to the read pulses applied in parallel to each of the associated parallel-serial converters 46a, 46b, 46c. Will be read. In response to the clock signal CK applied from the clock generator 40, the parallel-to-serial converters 46a, 46b, and 46c serially convert the parallel digital data read out from the associated dot memories 44a, 44b, and 44c. Converted to digital video signal pulses, these serial video signal pulses correspond to a dot pattern continuous over time in the horizontal scanning direction. Therefore, video signal pulses VR (VG) (VB) corresponding to red, green, and blue are generated in each of the parallel-to-serial converters 46a, 46b, 46c in synchronization with the clock signal CK.

The figure video signal generator 37 is by no means limited to the format shown in FIG. 6, and may be any one of a common letter text image generator and a figure image generator for generating a digital color video signal.

The digital video signal VR (VG) VB generated from the figure video signal generator 37 shown in FIG. 6 is connected to the clock signal CK, the horizontal synchronization signal HS, and the vertical synchronization signal VS. Together with the phase control device 38 shown in FIG. In FIG. 7, the phase control device 38 is a delay circuit VR (VG) (VB) for delaying the red, green and blue video signals applied to the respective input terminals 50, 52 and 54. FIG. And a selection circuit such as a multiplexer (MPLX) 68, 70, 72 for selectively passing the output signals from these delay circuits 62, 64, 66, and another input terminal 56. A counter 74 for counting the clock pulses CK, an address memory 76 for controlling the selection circuit or multiplexer 68, 70, 72 according to the count value of the counter 74, and each of the multiplexers And amplifiers 78, 80, 82 for amplifying the output signals from (68), 70, 72, and applying the amplified signals R, G, and B to the CDT 39. The horizontal synchronous signal HS and the vertical synchronous signal VS are applied to the input terminals 58 and 60, respectively.

To the delay circuit 62, a red video signal VR is applied as the video signal VR through the input terminal 50, and this delay circuit is, for example, four D flip-flops 62a (connected in series). 62b) 62c and 62d. Each of these D flip-flops 62a, 62b, 62c and 62d is connected to an input terminal 56 to which a clock signal CK is applied. Therefore, the video signal pulses appearing at the flip-flops 26a, 62b, 62c, and 62d correspond to one clock period, two clock periods, three clock periods, and four with respect to the video signal VR applied to the input terminal 50, respectively. Delayed by a clock cycle. The delayed video output signal output from the flip-flops 62a-61d is applied to the multiplexer 68 together with the video signal VR applied to the input terminal 50.

In this case, the input signal R + 2 input to the multiplexer 68 in response to the red video signal VR is transmitted through the two flip-flops 62a and 62b. An input signal R + 1 input to the multiplexer 68 obtained by passing the red video signal VR through a single flip-flop is advanced by two clock cycles with respect to the input signal R ₀ obtained by passing through the input signal R ₀ . Leads one clock cycle to (R ₀ ). On the other hand, the input signal R-1 input to the multiplexer 68 obtained by passing the red video signal VR through the three lip flops 62a, 62b and 62c and the four total flip-flops 62a. The input signals R-2 input to the multiplexer 68 obtained by passing the red video signal VR through the 62b and 62c are all 1 clock period and 2 clock periods with respect to the input signal R ₀ , respectively. Delayed by.

Similarly, the blue video signal VB is applied to the delay circuit 66 through the input terminal 54. The delay circuit 66 is, for example, four flip-flops 66a, 66b, 66c connected in series. And 66d. The input signal (B ₀ ) input to the multiplexer 72 is delayed by two clock cycles with respect to the blue video signal VB. For these input signals (B ₀₎ and with the input signal (B _0), each one clock cycle and two clock cycles ahead of the input signal (B + 1), (B + 2) and each 1 for an input signal (B ₀₎ The input signals B-1 and B-2 delayed by a clock cycle and two clock cycles are both applied to the multiplexer 72.

Meanwhile, the green video signal VG is applied to the delay circuit 64 through the input terminal 52, and the delay circuit 64 is composed of two D flip flops connected in series. The green video signal VG is not directly applied to the multiplexer 70, and as a result of passing the green video signal VG through two flip-flops 64a and 64b, two clock cycles are applied to the green video signal VG. The delayed input signal G ₀ is applied to all input terminals of the multiplexer 70.

After the clock counter 74 is reset by the horizontal synchronization signal HS applied through the input terminal 58, the clock counter 74 begins to count the clock pulse CK applied through the input terminal 56. As a result of the continuous counting, an address signal ADDR indicating a continuous position counted in the horizontal scanning direction from the left end of the display screen is applied from the counter 74 to the address memory 76. The address memory 76, which provides a video display without misconvergence by controlling the position of the bright point shown on the display screen by the address signal ADDR, indicates how far to shift the phases of the corresponding color video signals. Remember and remember the data.

Referring to the misconvergence pattern shown in FIG. 2, the red luminance line 14 and the blue luminance line 18 are biased toward the left and the right with respect to the vertical luminance line of the green 16, respectively. have. Here, it is assumed that the maximum degree of deflection of the red and blue luminance lines 14 and 18 with respect to the green luminance line 16 is, for example, 2 dots. In the center area I of the display screen, the luminance lines 14 ", 16", and 18 "hardly deviate from the adjustment position. Between the center area I and the edge area III in the horizontal scanning direction In each of the region II in the middle of the region, the red luminance line 14 'is biased about 2 dots to the left with respect to the green luminance line 16', and the blue luminance line 18 'is 1 dot to the right. In each edge region III, the red luminance line 14 is deflected about 2 dots to the left with respect to the green luminance line 16, and the blue luminance line 18 is about 2 dots to the right. Incidentally, it is assumed here that one dot in the horizontal scanning direction of the display screen corresponds to one clock period. Therefore, in this case, the green luminance line 16 "in the region I is assumed. the red and the blue luminance level of the line deflection (14 ") (18") is located (P ₃₎ and the minimum, or zero, position (P ₂₎ (P ₄₎ It is about one-half dot. In region II, the minimum deflection is about 1/2 dot at position P ₂ (P ₄ ), and the maximum deflection is about 3/2 dot at position P ₁ (P ₅ ). In the region III, the minimum deflection at position P ¹ (P ₅ ) is about 3/2 dots, and the maximum deflection at position P ₀ (P ₆ ) is about 2 dots.

In the embodiment of the present invention, while scanning in the region I, red, green and blue video signals of the same phase are simultaneously applied to the CDT 39 (while scanning in the region II, while the CDT is scanning in the region II). The phase of the red video signal applied to (39) is delayed by one clock period with respect to the green video signal, and the phase of the blue video signal applied to the CDT is advanced by one clock period with respect to the green video signal. During scanning, the phase of the red video signal applied to the CDT is delayed by 2 clock cycles with respect to the green video signal, and the phase of the blue video signal applied to the CDT is advanced by 2 clock cycles with respect to the green video signal.

Therefore, when the count value of the counter 74 indicates the dot position included in the center area I of the display screen, the address memory 76 receives the input signal (applied to the multiplexers 68, 70, 72). Generates a 3-bit digital output signal to select R ₀ ) (G ₀ ) (B ₀ ), which are connected to terminals S ₀ (S ₁ ) of the multiplexers 60, 70, 72. (S ₂ ) is applied from the output terminal of the address memory 76. Thus, input signals R ₀ (G ₀ ) (B ₀ ) are selected and output from respective multiplexers 68, 70, 72. These output signals are amplified by amplifiers 78, 80, 82, respectively, and the video signals R (G) (B) for operating the electron guns are eventually output terminals 84, 86, 88, respectively. Is output from In this case, even if the corrected video signals R (G) (B) are delayed by two clock cycles with respect to the original video signals VR (VG) (VB), respectively, these signals (R) (G). (B) has no phase difference between them.

On the other hand, when the count value of the counter 74 indicates the dot position included in a certain area of the intermediate area II, the input signals R-1 (G ₀ ) applied to the multiplexers 68, 70 and 72 respectively. The 3-bit signal for selecting (B + 1) is applied from the address memory 76 to the selection terminals S ₀ (S ₁ ) (S ₂ of the multiplexers 68, 70, 72). Input signals R-1 (G ₀ ) (B + 1) are selected by multiplexers 68, 70, 72 and applied to respective amplifiers 78, 80, 82. In this case, The corrected red video signal R-1 is delayed by 1 clock period with respect to the green video signal G ₀ , and the corrected blue video signal B + 1 is 1 clock with respect to the green video signal G ₀ . Therefore, by applying these video signals to the CDT 39 to emit an electron beam from the electron gun, the relative deflection of the luminance line in the region II can be almost canceled out.

When the counter value of the counter 74 indicates a dot position in any one of the peripheral region III where the relative deflection of the luminance line is large, the input signal R-2 applied to the corresponding multiplexers 68, 70, 72, respectively. The 3-bit signal for selecting (G ₀ ) (B + 2) is transmitted from the address memory 76 to the selection terminals S ₀ (S ₁ ) (S ₂ ) of the multiplexers 68, 70, and 72. The selected input signals R-2 (G ₀ ) (B + 2) are applied to respective corresponding amplifiers 78, 80, 82. In this case, the corrected blue signal R-2 is delayed in phase by 2 clock cycles with respect to the green video signal G ₀ , and the corrected blue signal B + 2 is the green video signal G ₀ . The phase is advanced by 2 clock cycles. Therefore, by applying these video signals to the CDT 39 to emit an electron beam from the electron gun, the relative deflection of the luminance line in the region III can be canceled to almost negligible.

As can be seen from the above description of the embodiment of the present invention, the deflection yoke is formed to form a misconvergence pattern in which the luminance line is adjusted in the vertical direction, and the video signals of three colors are missed in the horizontal direction. Corresponds to the value of convergence and has an anomaly shifted relative to each other by an amount. Therefore, the present invention can provide a video display device having almost no color misalignment despite its simple configuration.

In the above-described embodiment of the present invention, the red luminance line is deflected to the left of the display screen with respect to the green luminance line, and the blue luminance line is deflected to the right of the display screen with respect to the green luminance line. When the luminance line is deflected right and left with respect to the green luminance line, respectively, the input signal R ₀ (R + 1) (R + 2) input to the multiplexer 68 and the input signal input to the multiplexer 72 ( B ₀ ) (B-1) (B-2) are used in the regions (I) (II) (III), respectively. Therefore, the D flip-flops 66c and 66d shown in FIG. 7 can be omitted in this case.

In addition, in the above-described embodiment of the present invention, the case where the relative maximum deflection between the luminance lines is two dots in the horizontal scanning direction has been described, but the present invention can be applied even when the deflection is two bits or less or two or more bits.

Hereinafter, a second embodiment of the present invention that can be applied when the maximum relative deflection between luminance lines is, for example, 3 bits in the horizontal scanning direction will be described. In the case of the first embodiment of the present invention, the relative deflection between the green luminance line and the red luminance line in the region III is 5/2 dots from 3/2 dots (corresponding to positions P ₁ and P ₅ ). (In correspondence with positions P ₀ and P ₆ ). In the second embodiment of the present invention, as shown in FIG. 8, from 3/2 dots (corresponding to positions P ₂ and P ₆ ) to 5/2 dots (corresponding to positions P ₁ and P ₇ ) Region III is defined so that relative deflections belong to the green luminance line 16 and the red and blue luminance lines 14 and 18. As shown in FIG. 8, an additional area (in the deflection region) from 5/2 dots (corresponding to positions P ₁ and P ₇ ) to 3 dots (corresponding to positions P ₀ and P ₀ ) IV).

In the second embodiment of the present invention, red, green, and blue video signals of the same phase are simultaneously applied to the CDT 39 during scanning in the region (I), while CDT (scanning) is performed during scanning in the region (II). 39 delays the phase of the blue video signal applied to the green video signal by one clock cycle, and the phase of the blue video signal applied to the CDT 39 advances by one clock cycle to the green video signal. During scanning in (III), the phase of the red video signal applied to the CDT 39 is delayed by 2 clock cycles relative to the green video signal, and the phase of the blue video signal applied to the CDT 39 is applied to the green video signal. Advance by 2 clock cycles. During scanning in the region IV, the phase of the red video signal applied to the CDT 39 is delayed by 3 clock cycles with respect to the green video signal, and the phase of the blue video signal applied to the CDT 39 is the green video signal. Advance by 3 clock cycles.

9 is a circuit diagram showing the configuration of the phase control device 38 used in the second embodiment of the present invention. In FIG. 9, the same code | symbol is attached | subjected to the part same as FIG.

In Fig. 9, six series-connected D flip-flops 81a-81f are provided in the delay circuits 81, 83, 85 for delaying the red, green, and blue video signals VR (VG) (VB). And three series-connected D flip-flops 83a-83c and six series-connected D flip-flops 85a-85f. Therefore, the input signals R + 3, R + 2, and R + 1 input to the multiplexer 88 are in phase with respect to the input signal R ₀ by 3 clock cycles, 2 clock cycles, and 1 clock cycle, respectively. On the other hand, the input signals R-3, R-2, and R-1 input to the multiplexer 88 are phased by three clock periods, two clock periods, and one clock period with respect to the input signal R ₀ , respectively. and a replay, as yet another multiplexer 92, the input signal (B + 3) input to the (B + 2) (B + 1) are each three-clock period with respect to an input signal (B _0), 2 clock cycles, and 1 The phase is delayed by a clock cycle and one clock cycle. Similarly, the same input signal G ₀ is applied to another multiplexer 90. The input signal R ₀ (G ₀ ) has the same phase.

Therefore, when the counter value of the counter 74 indicates the dot position in the center area I of the display screen, the input signals R ₀ (G ₀ ) (B ₀ ) applied to the multiplexers 88, 90, 92 are applied. ₀ ) is selected by the 3-bit digital signal applied from the address memory 96. On the other hand, when the count value of the counter 74 indicates the dot position in the first intermediate region II, the output signal from the address memory 96 is input to the respective multiplexers 88, 90 and 92, respectively. Select the input signal R-1 (G ₀ ) (B + 1). When the count value of the counter 74 indicates a dot position in the second intermediate region III where the relative degree of deflection between the luminance lines is larger than that in the region II, the output signal from the address memory 96 is respectively determined. Input signals R-2 (G ₀ ) (B + 2) input to the multiplexers 88, 90, 92 are selected. In addition, when the count value of the counter 74 indicates the dot position in the edge region IV where the relative degree of deflection between the luminance lines is the maximum, the 3-bit output signal from the address memory 96 is output to each multiplexer 88. Input signals R-3 (G ₀ ) (B + 3) input to (90) and (92) are selected.

Therefore, the relative deflection between the green luminance line and the red luminance line can be canceled to almost negligible in all areas. By adjusting the delay time of each delay circuit according to the degree of relative deflection between the luminance lines, the possibility of appearance of color error adjustment on the display screen is almost eliminated.

In each of the two embodiments of the present invention described above, the phases of the red and blue video signals may be advanced or delayed by n clock periods (n: integers) with respect to the phase of the green video signal, thereby reducing the relative deflection between the luminance lines. Reduce even more. This embodiment of the present invention will be described next.

In the third embodiment of the present invention, the phases of the red and blue video signals are advanced or delayed by n / 2 clock periods (n = 0, 1, 2, 3, 4) with respect to the green video signal. As shown in FIG. 10, in misconvergence, the maximum deflection of the red and blue luminance lines with respect to the green luminance line is about 2 dots. In FIG. 10, the display screen is divided into five regions (I, II, III, IV, and V). In the region (I), the deflection range of the red and blue luminance lines with respect to the green luminance line is from 0 to 1/4 dots (corresponding to positions P ₄ and P ₅ ). In the region (II), the deflection range is 1. From 4 dots to 3/4 dots (corresponding to positions P ₃ and P ₆ ). The deflection range in region III ranges from 3/4 dots to 5/4 dots (for positions P ₂ and P ₇ ), and the deflection range in region IV ranges from 5/4 dots to 7 / dot. It is up to 4 dots (corresponding to positions P ₁ and P ₈ ), and the deflection range in the edge region V ranges from 7/4 dots to 2 dots (corresponding to positions P ₀ and P ₉ ).

In the third embodiment of the present invention, red, green and blue video signals of the same phase are applied to the CDT 39 during scanning in the region (I), while the CDT 39 is scanned during scanning in the region (II). Phase of the red video signal is delayed by 1/2 clock period with respect to the green video signal, and the phase of the blue video signal applied to the CDT 39 is advanced by 1/2 clock period with respect to the green video signal. . During scanning in the region III, the phase of the red video signal applied to the CDT 39 is delayed by one clock period with respect to the green video signal, and the phase of the blue video signal applied to the CDT 39 is the green video signal. Advance one clock cycle with respect to. During scanning in the region IV, the phase of the red video signal applied to the CDT 39 is delayed by 3/2 clock periods with respect to the green video signal, and the phase of the blue video signal applied to the CDT 39 is green. Advance the signal by 3/2 clock cycles. During scanning in the area V, the phase of the red video signal applied to the CDT 39 is delayed by two clock cycles relative to the green video signal, and the phase of the blue video signal applied to the CDT 39 is applied to the green video signal. Advance by 2 clock cycles.

11 is a circuit diagram showing the structure of the phase control device 38 used in the third embodiment of the present invention. In FIG. 11, the same code | symbol is attached | subjected to the part same as the part shown in FIG. In FIG. 11, the delay circuits 102, 64 and 106 for delaying the red, green and blue video signals VR (VG) and VB are arranged in four series, as in the case of the structure shown in FIG. D flip flops 106a-102d connected to each other, two D flip flops 64a and 64b connected in series, and four D flip flops 106a and 106d connected in series. However, in the structure shown in Fig. 7, the input signals input to the respective flip-flops 62a-62d and 66a-66d are directly applied to the respective multiplexers 68, 72, respectively. The structure of FIG. 11 is different in that it is applied to the multiplexers 108 and 112 via the delay elements 102e-102h and 106e-106h of the multiplexers 108 and 112. These delay elements 102e-102h and 106e-106h are each inputted by 1/2 clock period (corresponding to 1/2 dot on the display screen), for example, using a CR circuit. You may make it delay. Therefore, the input signals R + 1, R + 2, R + 3, and R + 4 input to the multiplexer 108 are 1/2 clock period, 1 clock period, respectively, with respect to the input signal R ₀ . The phase is advanced by 3/2 clock cycles and 2 clock cycles, while the input signals R-1, R-2, R-3, and R-4 input to the multiplexer 108 are input signals R. _The phase is delayed by 1/2 clock period, 1 clock period, 3/2 clock period, and 2 clock periods, respectively. Similarly, 1/2 clock period and 1 clock are applied to the input signals B ₀ input to the input signals B + 1, B + 2, B + 3, and B + 4 input to the multiplexer 112. The phase is advanced by the period, 3/2 clock period and 2 clock periods, while the input signals B-1, B-2, B-3, and B-4 input to the multiplexer 112 are input signals. The phase is delayed by 1/2 clock period, 1 clock period, 3/2 clock period, and 2 clock periods for (B ₀ ), respectively.

Therefore, when the count value of the counter 74 indicates the dot position in the center area I of the display screen, the address memory 116 selects the terminals S ₀ of the respective multiplexers 108, 70, 112. Selection terminals S ₀ of respective corresponding multiplexers 108, 70, 112 to select an input signal R ₀ (G ₀ ) (B ₀ ) input to (S ₁ ) (S ₂ ). S ₁ ) (S ₂ ) applies a 3-bit digital signal. When the count value of the counter 74 indicates the dot position in the area II, the output signal from the address memory 116 is input to the respective multiplexers 108, 70 and 112, respectively. 1) Select (G ₀ () B + 1).

When the count value of the counter 74 indicates the dot position in the area III, the output signal from the address memory 116 is input to the respective multiplexers 108, 70 and 112, respectively. 2) Select (G ₀ ) (B + 2). Also, when the count value of the counter 74 indicates the dot position in the area IV, the output signal from the address memory 116 is input to the respective multiplexers 108, 70 and 112, respectively. -3) (G ₀ ) (B + 3). When the counter value of the counter 74 indicates the dot position in the area V, the output signal from the address memory 116 is input to the respective multiplexers 108, 70 and 112, respectively. 4) Select (G ₀ ) (B + 4).

Therefore, the relative deflection between the green luminance line and the red and blue luminance lines can be made much smaller than in the first and second embodiments in all areas of the display screen.

In an embodiment of the present invention, the phase of the red and blue video signals is advanced or delayed by n or n / 2 clock pulses (n: integer) with respect to the phase of the green video signal, and thus misconvergence in the horizontal scanning direction. Can be almost eliminated.

As already described in FIG. 2, the CDT used in the embodiment of the present invention is a deflection yoke that generates two types of horizontal deflection magnetic fields acting as pincushion materials and vertical deflection magnetic fields acting as barrel magnetic fields, and intentionally modified. By including a magnet piece for controlling the magnetic field to correct coma aberration due to the magnetic field, a residual misconvergence pattern is generated as shown in FIG. Assuming that the CDT 39 includes only such a deflection yoke and does not include a magnet piece, the misconvergence pattern is as shown in FIG. In FIG. 12, the degree of deflection of the red luminance line 14 with respect to the green luminance line 16 is determined in relation to the green luminance line 16 in the respective areas (I) (II) and (III) of the display screen. It can be seen that it is different from the degree of deflection of the blue luminance line 18. In detail, the deflection of the red and blue luminance lines with respect to the green luminance line at the position P ₂ (P ₅ ) in the intermediate region II is, for example, 2 dots and 1 dot, respectively, while the marginal region (III) is shown. At position P ₀ (P ₇ ), the degree of deflection of the red and blue luminance lines relative to the green luminance line is, for example, 4 dots and 2 dots, respectively. Therefore, the deflection of the red (blue) luminance line with respect to the green luminance line is 0 dots-1 dots (1/2 dots), 1 dot (1/2 dots) -3 dots (3/2 dots) and 3 dots (3 / The range of 2 dots) to 4 dots (2 dots) is defined by regions (I), (II) and (III), respectively. During scanning in the region (I), the red, green and blue video signals of the same phase are applied to the CDT 39, and during the scanning in the region (II), two clock cycles and one clock cycle are respectively applied to the green video signal. Is delayed by 4 clock cycles and 2 clock cycles with respect to the green video signal during scanning in the region (III), and the previous red and blue video signals are delayed by the CDT 39. The phase control device may be designed to apply to (39).

In the above-described embodiment, the deflection of the red and blue luminance lines with respect to the green luminance line 16 of FIG. 2 can be corrected. However, as apparent from the above description, it is also possible to select a red or blue luminance line and use it as a reference for deflection correction of other luminance lines.

Claims (4)

(Correction) a color cathode ray tube having a deflection yoke and three inline electron guns, a figure image signal generating means for generating a digital color video signal pulse representing a dot image displayed on a display screen of the color cathode ray tube, and the figure In order to apply a phase controlled signal to the color cathode ray tube in response to the application of the digital color video signal from the image signal generating means, the digital color video with respect to each other by an amount corresponding to the amount of misconvergence in the horizontal deflection direction. A video display device comprising: phase control means for shifting a phase of a signal. (Correction) The method according to claim 1, wherein the figure video signal generating means includes a clock generator for generating a clock signal to generate the digital color video signal in synchronization with a clock pulse. First and second delaying a corresponding one of the red, green, and blue video signals applied from the video signal generating means, wherein at least the first and second delay circuits have different delay times and generate a plurality of output signals; Second and third delay circuits, first, second and third selection circuits (multiplexers) for selectively generating output signals of the first second and third delay circuits, and clock signals generated from the clock generator. Selecting one of a counter for counting and a plurality of output signals of the delay circuit in response to the selection signal is applied to the first, second and third selection circuit in accordance with the count value of the counter and the misconverter And means for applying a selected output signal corresponding to the amount of distortion to the color cathode ray tube. (Correction) The apparatus of claim 2, wherein the first, second and third delay circuits comprise a plurality of flip-flops connected in series operated by a clock signal generated by the clock generator, and at least the first and the second delay circuits. The output signal from the two delay circuits is out of phase with each other by one clock period, and the input / output signal of the flip-flop composed of the first and second delay circuits is configured to be applied to an associated circuit of the selection circuit. Device. Each of the first, second and third delay circuits comprises a plurality of flip-flops connected in series operated by a clock signal generated by the clock generator, and at least the first and second delay circuits. Includes a delay element connected to each flip-flop to delay the input signal by a half clock period, and the input / output signal of each flip-flop constituting the first and second delay circuits is associated with the selection circuit. A video display device configured to be applied directly to a circuit or to an associated circuit of the selection circuit via an associated delay element of the delay element.

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