KR850008044A - Semiconductor device manufacturing process - Google Patents

Semiconductor device manufacturing process Download PDF

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KR850008044A
KR850008044A KR1019850003061A KR850003061A KR850008044A KR 850008044 A KR850008044 A KR 850008044A KR 1019850003061 A KR1019850003061 A KR 1019850003061A KR 850003061 A KR850003061 A KR 850003061A KR 850008044 A KR850008044 A KR 850008044A
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layer
metallization
insulator
etching
organic
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KR930005949B1 (en
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제이. 밸다 레이몬드 (외 2)
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빈센트 죠셉토너
모토로라 인코포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/471—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/963—Removing process residues from vertical substrate surfaces

Abstract

내용 없음No content

Description

반도체 디바이스 제조공정Semiconductor device manufacturing process

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래 기술의 구조 및 이것과 함께 부수적으로 발생하는 문제점을 도시. 제2도는 본 발명에 따른 반도체 디바이스를 제조하는 공정에서의 단계도.Figure 1 shows the structure of the prior art and the problems that arise with it. 2 is a step view in the process of manufacturing a semiconductor device according to the present invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

20,36 : 반도체기판, 40,50 : 보호용층, 52 : 포토레지스프층, 60 : 마스킹층20,36: semiconductor substrate, 40,50: protective layer, 52: photoresist layer, 60: masking layer

Claims (10)

반도체 디바이스를 제조하는 공정에 있어서, 반도체 기판(36)상에 유기체 물질인 제1층(42)을 갖는 반도체기판(36)을 제공하고, 상기 기판상에 제1금속화인 제2층(48)을 제공하고, 제1금속화인 상기 제2층(48)상에서 제1 절연물질인 제3층(50)을 형성하고, 상기 제3층(50)을 패터닝하고, 상기 제2층(48)의 나머지 부상에 놓여있는 상기 제3층(50)을 남겨두고 제1금속화인 상기 제2층(49)을 패터닝하고, 상기 제3층(50)상에서 유기체 물질인 제4층(56)을 형성하고, 유기체 물질인 상기 제4층(56)상에서 상기 제1절연물질인 제5층(58)을 형성하고, 유기체 물질인 상기 제4층의 부를 노출하기 위해서 상기 제5층(58)에서 구멍을 형성하고, 상기 제3층(50)의 부를 노출하기 위해서 상기 제5층(58)에서 상기 구멍을 형성하고 유기체 물질인 상기 제4층(56)을 리액티브이온 에칭하고, 상기 제4층(58)과 제1금속화인 상기 제2층(48)의 부를 노출시키기 위해서 유기체물질인 상기 제4층(56)을 통하여 노출된 상기 제3층(50)의 부를 동시에 에칭하는 단계를 구비하는 것을 특징으로하는 반도체 디바이스 제조 공정.In the process of manufacturing a semiconductor device, a semiconductor substrate 36 having a first layer 42 of an organic material on a semiconductor substrate 36 is provided, and a second layer 48 of first metallization on the substrate. And forming a third layer (50) of a first insulating material on the second layer (48), which is a first metallization, patterning the third layer (50), and Patterning the second layer 49, which is a first metallization, leaving the third layer 50 lying on the remaining float, and forming a fourth layer 56 of organic material on the third layer 50; In order to form the fifth layer 58 of the first insulating material on the fourth layer 56 of the organic material and to expose portions of the fourth layer of the organic material, holes are formed in the fifth layer 58. Forming a hole in the fifth layer 58 to expose a portion of the third layer 50, and reactively etching the fourth layer 56, which is an organic material, Simultaneously etching portions of the third layer 50 exposed through the fourth layer 56, which is an organic material, to expose portions of the fourth layer 58 and the second layer 48 that is the first metallization. The semiconductor device manufacturing process characterized by the above-mentioned. 제1항의 공정에 있어서, 상기 유기체 물질인 제1층(42)은 폴리마이드로 구성되는 것을 특징으로 하는 반도체 디바이스 제조 공정.The process of claim 1 wherein the first layer (42), which is the organic material, is comprised of polyamide. 제1항의 공정에 있어서, 상기 유기체 물질인 상기 제4층(56)은 폴리마이드로 구성되는 것을 특징으로하는 반도체 디바이스 제조공정.The process of claim 1 wherein the fourth layer (56), which is the organic material, is comprised of polyamide. 제3항의 공정에 있어서, 상기 리액티브 이온 에칭 단계는 산소이온으로 에칭하는 단계를 구비하는 것을 특징으로 하는 반도체 디바이스 제조공정.The process of claim 3 wherein the reactive ion etching step comprises etching with oxygen ions. 제1항의 공정에 있어서, 상기 제1 절연물질인 상기 제3층(50)은 증착된 실리콘 산화물 또는 실리콘 질화물로 구성되는 것을 특징으로하는 반도체 디바이스 제조공정.The process of claim 1, wherein said third layer (50), said first insulating material, is comprised of deposited silicon oxide or silicon nitride. 제1항의 공정에 있어서, 상기 제4층(56)상에 놓여있는 제2금속화인 제6층을 증착하고 제1금속화인 상기 제2층(48)과 선택적으로 접촉하는 단계를 구비하는 것을 특징으로 하는 반도체 디바이스 제조공정.The process of claim 1, comprising depositing a sixth layer of a second metallization on said fourth layer 56 and selectively contacting said second layer 48 of a first metallization. A semiconductor device manufacturing process. 반도체 디바이스를 제조하다 공정에 있어서, 반도체 기판(36)을 제공하고, 상기 기판상에 놓여있는 금속화인 제1층(38)을 패터닝하고, 무기절연체인 제2층(40) 및 그 다음에 유기절연체인 제3층(42)을 금속화인 상기 제1층(38)상에서 헝성하고, 무기절연체인 상기 제2층(40)의 부를 노출시키기 위해서 유기절연체인 상기 제3층(42)내의 구멍을 리액티브 이온 에칭하고, 금속화인 상기 제1층(38)의 부를 노출하기 위해서 상기 노출된 부를 에칭하고, 금속화인 제4층(48) 및 무기절연체인 제5층(50)을 유기절연체인 상기 제3층(42)상에서 증착하고 금속화인 상기 제4층(48)은 상기 구멍을 통하여 금속화인 상기 제1층(38)과 선택적으로 접촉하고, 금속화인 상기 제4층(48)의 부를 노출하기 위해서 무기절연체인 상기 제5층(50)의 부를 제거시키고, 무기절연체인 상기 제5층(50)의 나머지부에 의해 놓여진 금속화인 패턴을 남겨두기 위해서 금속화인 상기 제4층(48)의 상기 노출된 부를 제거시키고, 금속화인 상기 패턴상에 유기절연체인 제6층(56)을 제공하고, 무기절연체인 상기 제5층(50)의 부를 선택적으로 노출시키기 위해서 유기 절연체인 상기 제6층(56)을 통하여 구멍을 리액티브 이온 에칭하고, 금속화인 상기 패턴의 부를 노출하기 위해서 무기절연체인 상기 제5층(50)의 노출된 부를 에칭하는 단계를 구비하는 것을 특징으로하는 반도체 디바이스 제조공정.In the process of manufacturing a semiconductor device, a semiconductor substrate 36 is provided, the first layer 38, which is a metallization, placed on the substrate, is patterned, and the second layer 40, which is an inorganic insulator, and then organic A hole in the third layer 42, which is an organic insulator, is formed on the first layer 38, which is an insulator, to form a portion of the second layer 40, which is an inorganic insulator. Reactive ion etching and etching the exposed portions to expose portions of the first layer 38 which is metallization, and the fourth layer 48 which is metallization and the fifth layer 50 which is an inorganic insulator are organic insulators. The fourth layer 48 deposited on the third layer 42 and being metallized selectively contacts the first layer 38 which is metallized through the aperture, exposing a portion of the fourth layer 48 which is metallized. In order to remove the portion of the fifth layer 50, which is an inorganic insulator, Remove the exposed portion of the fourth layer 48 being metallized to leave the metallized pattern laid down by the rest, and provide a sixth layer 56, which is an organic insulator, on the patterned metallized, inorganic insulator Reactive ion etching a hole through the sixth layer 56, which is an organic insulator, to selectively expose portions of the fifth layer 50, which are phosphorus, and the fifth, which is an inorganic insulator, to expose portions of the pattern, which is metallization. Etching the exposed portion of the layer (50). 제7항의 공정에 있어서, 유기절연체인 상기 제3층(42) 및 유기절연체인 상기 제6층(56)은 폴리마이드로 구성되는 것을 특징으로 하는 반도체 디바이스 제조공정.8. The process of claim 7, wherein the third layer (42), which is an organic insulator, and the sixth layer (56), which is an organic insulator, are made of polyamide. 제8항의 공정에 있어서, 무기절연체인 상기 제2층(40) 및 무기절연체인 상기 제5층(50)은 증착된 실리콘 산화물 또는 실리콘 질화물로 구성되는 것을 특징으로 하는 반도체 디바이스 제조공정.The process of claim 8, wherein the second layer (40), which is an inorganic insulator, and the fifth layer (50), which is an inorganic insulator, are formed of deposited silicon oxide or silicon nitride. 반도체 디바이스를 제조하는 공정에 있어서, 반도체기판(36)을 제공하고, 상기 기판상에서 차례로 제1금속화 패턴(38), 제2보호용층(40), 폴리마이드인 제3층 (42), 금속화인 제4층(48), 제5보호용층(50) 및 폴리마이드인 제6층(56)을 형성하고, 상기 제2보호용층(40)의 부를 노출하기 위해서 폴리마이드인 상기 제3층(42)을 리액티브 이온 에칭하고, 상기 제2보호용층(40)의 상기 노출된 부를 에칭하고, 금속화인 상기 제4층(48)의 나머지 부상에 놓여진 상기 제5보호용층(50)의 나머지 부를 남겨두기 위해서 상기 제5보호용층(50) 및 금속화인 상기 제4층(48)을 패터닝하고, 상기 제5보호용층(50)증 상기 나머지부의 일부를 노출하기 위해서 폴리마이드인 상기 제6층(56)내의 구멍을 리액티브 이온 에칭하고, 상기 구멍을 통하여 노출된 제5보호용층(50)의 부를 에칭하는 것을 특징으로하는 반도체 디바이스 제조공정.In the process of manufacturing a semiconductor device, a semiconductor substrate 36 is provided, and the first metallization pattern 38, the second protective layer 40, the third layer 42 made of polyamide, and the metal are sequentially formed on the substrate. The fourth layer 48, the fifth protective layer 50, and the sixth layer 56, which is polyamide, are formed, and the third layer, which is polyamide, to expose portions of the second protective layer 40 ( 42) reactive ion etching, etching the exposed portion of the second protective layer 40, and remaining portion of the fifth protective layer 50 placed on the remaining float of the fourth layer 48 which is metallization. Patterning the fifth protective layer 50 and the fourth layer 48 which is metallization, and the sixth layer of polyamide to expose a portion of the remaining portion of the fifth protective layer 50. Reactive ion etching the holes in 56 and etching the portions of the fifth protective layer 50 exposed through the holes A semiconductor device manufacturing process according to Gong. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850003061A 1984-05-07 1985-05-06 Process for fabricating semiconductor device KR930005949B1 (en)

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Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116167A (en) * 1983-11-29 1985-06-22 Toshiba Corp Semiconductor memory and manufacture thereof
JPS60138940A (en) * 1983-12-27 1985-07-23 Toshiba Corp Manufacture of semiconductor device
JPS60176250A (en) * 1984-02-23 1985-09-10 Toshiba Corp Manufacture of semiconductor device
US4717449A (en) * 1984-04-25 1988-01-05 Honeywell Inc. Dielectric barrier material
JPS60247940A (en) * 1984-05-23 1985-12-07 Hitachi Ltd Semiconductor device and manufacture thereof
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
JPS6218755A (en) * 1985-07-18 1987-01-27 Toshiba Corp Solid-state image pickup device
JPH0652732B2 (en) * 1985-08-14 1994-07-06 三菱電機株式会社 Method for forming passivation film
FR2588417B1 (en) * 1985-10-03 1988-07-29 Bull Sa METHOD FOR FORMING A MULTI-LAYER METAL NETWORK FOR INTERCONNECTING THE COMPONENTS OF A HIGH DENSITY INTEGRATED CIRCUIT AND RESULTING INTEGRATED CIRCUIT
US4723197A (en) * 1985-12-16 1988-02-02 National Semiconductor Corporation Bonding pad interconnection structure
WO1987005441A1 (en) * 1986-03-05 1987-09-11 Sumitomo Electric Industries, Ltd. Semiconductor device and a method of producing the same
US4840923A (en) * 1986-04-30 1989-06-20 International Business Machine Corporation Simultaneous multiple level interconnection process
US4721689A (en) * 1986-08-28 1988-01-26 International Business Machines Corporation Method for simultaneously forming an interconnection level and via studs
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US4966865A (en) * 1987-02-05 1990-10-30 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US4948749A (en) * 1987-03-25 1990-08-14 Mitsubishi Denki Kabushiki Kaisha Process for forming electrodes for semiconductor devices
US4853341A (en) * 1987-03-25 1989-08-01 Mitsubishi Denki Kabushiki Kaisha Process for forming electrodes for semiconductor devices using focused ion beams
JPS63268258A (en) * 1987-04-24 1988-11-04 Nec Corp Semiconductor device
JPH0654774B2 (en) * 1987-11-30 1994-07-20 株式会社東芝 Semiconductor device and manufacturing method thereof
US4966870A (en) * 1988-04-14 1990-10-30 International Business Machines Corporation Method for making borderless contacts
JPH0797602B2 (en) * 1988-05-06 1995-10-18 日本電気株式会社 Semiconductor integrated circuit device
US5164339A (en) * 1988-09-30 1992-11-17 Siemens-Bendix Automotive Electronics L.P. Fabrication of oxynitride frontside microstructures
IT1225624B (en) * 1988-10-20 1990-11-22 Sgs Thomson Microelectronics SELF-ALIGNED METAL-SEMICONDUCTOR CONTACT PROCEDURE IN INTEGRATED DEVICES CONTAINING MISFET STRUCTURES
US5162260A (en) * 1989-06-01 1992-11-10 Hewlett-Packard Company Stacked solid via formation in integrated circuit systems
US5055425A (en) * 1989-06-01 1991-10-08 Hewlett-Packard Company Stacked solid via formation in integrated circuit systems
US5070037A (en) * 1989-08-31 1991-12-03 Delco Electronics Corporation Integrated circuit interconnect having dual dielectric intermediate layer
JP2688446B2 (en) * 1990-03-26 1997-12-10 株式会社日立製作所 Multilayer wiring board and manufacturing method thereof
EP0457449A1 (en) * 1990-04-27 1991-11-21 Fujitsu Limited Semiconductor device having via hole and method of producing the same
JP2538699B2 (en) * 1990-06-12 1996-09-25 株式会社東芝 Test element for dielectric breakdown evaluation
JP3074713B2 (en) * 1990-09-18 2000-08-07 日本電気株式会社 Method for manufacturing semiconductor device
US5139974A (en) * 1991-01-25 1992-08-18 Micron Technology, Inc. Semiconductor manufacturing process for decreasing the optical refelctivity of a metal layer
EP0534631B1 (en) * 1991-09-23 1999-01-07 STMicroelectronics, Inc. Method of forming vias structure obtained
JPH05190684A (en) * 1992-01-16 1993-07-30 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5744382A (en) * 1992-05-13 1998-04-28 Matsushita Electric Industrial Co., Ltd. Method of packaging electronic chip component and method of bonding of electrode thereof
KR950006343B1 (en) * 1992-05-16 1995-06-14 금성일렉트론주식회사 Fabricating method of semiconductor device
US5416048A (en) * 1993-04-16 1995-05-16 Micron Semiconductor, Inc. Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
US5847457A (en) * 1993-11-12 1998-12-08 Stmicroelectronics, Inc. Structure and method of forming vias
JPH08139194A (en) * 1994-04-28 1996-05-31 Texas Instr Inc <Ti> Manufacture of electrical connection onto semiconductor device and semiconductor device with electrical connection manufactured by said method
US6153501A (en) 1998-05-19 2000-11-28 Micron Technology, Inc. Method of reducing overetch during the formation of a semiconductor device
US5550405A (en) * 1994-12-21 1996-08-27 Advanced Micro Devices, Incorporated Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS
US5757077A (en) * 1995-02-03 1998-05-26 National Semiconductor Corporation Integrated circuits with borderless vias
US5858875A (en) * 1995-02-03 1999-01-12 National Semiconductor Corporation Integrated circuits with borderless vias
US5656543A (en) * 1995-02-03 1997-08-12 National Semiconductor Corporation Fabrication of integrated circuits with borderless vias
JPH09129732A (en) * 1995-10-31 1997-05-16 Nec Corp Semiconductor device manufacturing method
US6051501A (en) * 1996-10-09 2000-04-18 Micron Technology, Inc. Method of reducing overetch during the formation of a semiconductor device
US5879572A (en) * 1996-11-19 1999-03-09 Delco Electronics Corporation Method of protecting silicon wafers during wet chemical etching
US6033977A (en) * 1997-06-30 2000-03-07 Siemens Aktiengesellschaft Dual damascene structure
US6127721A (en) * 1997-09-30 2000-10-03 Siemens Aktiengesellschaft Soft passivation layer in semiconductor fabrication
KR20000071346A (en) * 1999-02-15 2000-11-25 가네꼬 히사시 Manufacturing method of semiconductor device using a dual damascene process
JP3759367B2 (en) * 2000-02-29 2006-03-22 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
US6368899B1 (en) 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
US6737283B2 (en) 2002-08-29 2004-05-18 Micron Technology, Inc. Method to isolate device layer edges through mechanical spacing
US7241696B2 (en) * 2002-12-11 2007-07-10 International Business Machines Corporation Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
TWI345312B (en) * 2004-07-26 2011-07-11 Au Optronics Corp Thin film transistor structure and method of fabricating the same
KR100602131B1 (en) * 2004-12-30 2006-07-19 동부일렉트로닉스 주식회사 Semiconductor device and method for fabricating the same
US8486285B2 (en) * 2009-08-20 2013-07-16 Western Digital (Fremont), Llc Damascene write poles produced via full film plating
US9469109B2 (en) * 2014-11-03 2016-10-18 Stmicroelectronics S.R.L. Microfluid delivery device and method for manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52156555A (en) * 1976-06-23 1977-12-27 Hitachi Ltd Production of organic resin insulated wiring
US4092442A (en) * 1976-12-30 1978-05-30 International Business Machines Corporation Method of depositing thin films utilizing a polyimide mask
US4184909A (en) * 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
US4244799A (en) * 1978-09-11 1981-01-13 Bell Telephone Laboratories, Incorporated Fabrication of integrated circuits utilizing thick high-resolution patterns
JPS561547A (en) * 1979-06-19 1981-01-09 Matsushita Electric Ind Co Ltd Semiconductor device
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4357203A (en) * 1981-12-30 1982-11-02 Rca Corporation Plasma etching of polyimide
US4444617A (en) * 1983-01-06 1984-04-24 Rockwell International Corporation Reactive ion etching of molybdenum silicide and N+ polysilicon
US4464460A (en) * 1983-06-28 1984-08-07 International Business Machines Corporation Process for making an imaged oxygen-reactive ion etch barrier
US4430153A (en) * 1983-06-30 1984-02-07 International Business Machines Corporation Method of forming an RIE etch barrier by in situ conversion of a silicon containing alkyl polyamide/polyimide

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