KR850001594A - Decryptor - Google Patents

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Publication number
KR850001594A
KR850001594A KR1019840004259A KR840004259A KR850001594A KR 850001594 A KR850001594 A KR 850001594A KR 1019840004259 A KR1019840004259 A KR 1019840004259A KR 840004259 A KR840004259 A KR 840004259A KR 850001594 A KR850001594 A KR 850001594A
Authority
KR
South Korea
Prior art keywords
channel
bits
bit
bit block
information
Prior art date
Application number
KR1019840004259A
Other languages
Korean (ko)
Other versions
KR850000954B1 (en
Inventor
안토니 임민크 코르네리스 (외 3)
Original Assignee
디. 제이. 삭커스
엔. 브이. 필립스 글로아이람 펜파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from NLAANVRAGE8004028,A external-priority patent/NL186790C/en
Priority claimed from KR1019810002526A external-priority patent/KR850000953B1/en
Application filed by 디. 제이. 삭커스, 엔. 브이. 필립스 글로아이람 펜파브리켄 filed Critical 디. 제이. 삭커스
Priority to KR1019840004259A priority Critical patent/KR850000954B1/en
Publication of KR850001594A publication Critical patent/KR850001594A/en
Application granted granted Critical
Publication of KR850000954B1 publication Critical patent/KR850000954B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

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  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음No content

Description

복호장치Decryptor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 코딩포맷의 일실시예를 설명하기 위한 비트계열들을 도시한 도면, 제2도는 직류 불평형을 감소시키는데 사용되는 채널코딩의 포맷의 다른 실시예를 도시한 도면, 제3도는 2진부호 변환방식의 일실시예에 대한 플로우챠트, 제4도는 2진부호 변환방식에 사용하기 위한 동기비트블록을 도시한 도면.FIG. 1 shows bit sequences for explaining one embodiment of a coding format, FIG. 2 shows another embodiment of a channel coding format used to reduce direct current unbalance, and FIG. 3 shows a binary code conversion. 4 is a flowchart of a synchronization bit block for use in a binary code conversion scheme.

Claims (1)

2진 데이터 비트계열을 2진 채널비트 계열로 변환하여 얻어진 채널비트를 복조하는 복호장치에 있어서, 등기 패턴을 검출하는 장치와; 채널비트 계열을 제각기(n1+n2)개의 채널비트를 갖는 채널비트 블록들로 분할하는 장치와; 상기 채널비트블록을 n1개의 정보비트를 갖는 정보비트블록과 n2개의 분리비트를 갖는 분리비트블록으로 분할하는 장치와; 상기 정보비트블록을 m개의 비트를 갖는 데이터 비트블록으로 변환하는 장치를 특징으로 하는 복호장치.A decoding device for demodulating a channel bit obtained by converting a binary data bit sequence into a binary channel bit sequence, comprising: an apparatus for detecting a registration pattern; An apparatus for dividing a channel bit sequence into channel bit blocks each having n 1 + n 2 channel bits; An apparatus for dividing the channel bit block into an information bit block having n 1 information bits and a separation bit block having n 2 separation bits; And a device for converting the information bit block into a data bit block having m bits. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019840004259A 1980-07-14 1984-07-19 Coding of information blocks KR850000954B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019840004259A KR850000954B1 (en) 1980-07-14 1984-07-19 Coding of information blocks

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
NL8004028 1980-07-14
NLAANVRAGE8004028,A NL186790C (en) 1980-07-14 1980-07-14 METHOD FOR CODING A SERIES OF BLOCKS OF BILINGUAL DATA BITS IN A SERIES OF BLOCKS OF DUAL CHANNEL BITS, AND USING MODULATOR, DEMODULATOR AND RECORD CARRIER IN THE METHOD
KR1019810002526A KR850000953B1 (en) 1980-07-14 1981-07-11 Coding of information blocks
KR1019840004259A KR850000954B1 (en) 1980-07-14 1984-07-19 Coding of information blocks

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1019810002526A Division KR850000953B1 (en) 1980-07-14 1981-07-11 Coding of information blocks

Publications (2)

Publication Number Publication Date
KR850001594A true KR850001594A (en) 1985-03-30
KR850000954B1 KR850000954B1 (en) 1985-06-29

Family

ID=27348336

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840004259A KR850000954B1 (en) 1980-07-14 1984-07-19 Coding of information blocks

Country Status (1)

Country Link
KR (1) KR850000954B1 (en)

Also Published As

Publication number Publication date
KR850000954B1 (en) 1985-06-29

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