KR850001016B1 - Buffer memory control system of the swap system - Google Patents

Abstract

A control system for a buffer memory in a swap system processes ordinary memory access only to the buffer memory, and when no data in a requested address exists in the buffer memory, moves out any one of the blocks to a main memory and moves into the buffer memory a block including the data for the requested address. In the processing of writing data in an area that is equal to or an integral multiple of the block of the buffer memory, when the detecting mechanism determines that the data corresponding to a write address does not exist in the buffer memory, the data is written directly in the replace block of the buffer memory without preforming the operation of moving into the block from the main memory.

Description

Swap Buffer Memory Control System

1 is a block diagram showing a buffer memory circuit of an embodiment according to the present invention.

FIG. 2 is a block diagram showing a data memory portion of the buffer memory circuit of FIG.

3 is a block diagram showing buffer memory write control means in an embodiment of the invention.

4 is an explanatory diagram of the control shift register illustrated in FIG.

FIG. 5 is a block diagram showing the main part of the write data control circuit used in FIG.

FIG. 6 is a block diagram showing the main part of the recording control means used in FIG.

The present invention performs normal memory access processing only for the buffer memory, and moves a block in the buffer memory to the main memory only when there is no data of any request address in the buffer memory. And a swap-type buffer memory control system for moving a block containing data of a request address from the main memory into a buffer memory, particularly when no request address data exists in the buffer memory. Is directed to a buffer memory control system that allows a written-in directly to the buffer memory under certain conditions.

In a conventional processing apparatus having a buffer memory and a main memory, when data is written-in in the buffer memory, a tag (tag = flag) is searched to determine whether or not there is data of a request address in the buffer memory. If there is data of the request address in the buffer memory, the block containing the data of the request address is read out from the buffer memory, merged with the write data, and then written back into the buffer memory. If there is no data, the block to replace the buffer memory determined by the replace circuit is sent to the main memory, and the block containing the data of the request address is read out from the main memory and combined with the write data. Then, it was written into the buffer memory. That is, whenever the data of the request address is not in the buffer memory, the block containing the data of the request address is moved from the main memory into the buffer memory. Incidentally, when the write command (block memory command) is processed for an area having the same size as the control unit of the buffer memory or an integer multiple, the entire block is rewritten so that the buffer is stored in the main memory. The block contents sent to the memory do not have any meaning. Therefore, in the processing of the write command, the time for reading the main memory becomes, for example, an invalid operation time. Such a swap system is disclosed in US Pat. Nos. 3,771,137 and 3,848,234.

It is an object of the present invention to improve the processing speed of a write command for an area of the same size as the block, which is the management unit of the above-described buffer memory, or an integer size thereof.

In summary, the present invention performs normal memory access processing only for the buffer memory, sends out a block in the buffer memory to the main memory only when there is no data of the request address in the buffer memory, and returns the request address from the main memory. In a swap type buffer memory control system for sending a block including data, means for detecting whether a block containing data of a request address exists in the buffer memory, and a replacement block for the main memory is stored in the buffer memory. And a means for detecting whether it has been changed later. In processing a write command for an area of the same size or an integer multiple of the block of the buffer memory, if it is detected that no data corresponding to the write address exists in the buffer memory, a replacement block is sent from the main memory to the buffer memory. Instead, data is written directly to the replacement block of the buffer memory.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the accompanying drawings.

1 is a block diagram of an embodiment of the present invention. Reference numerals 1-1 to 1-n denote data memory composed of management words such that 64 bytes form one block, 2-1 to 2-n correspond to tag memory, and 3-1 to 3-n correspond to data memory blocks. A change bit memory for storing whether or not there is a change in the contents of the data memory, 4 is a replacement data memory for storing information of the replacement block of the data memory, 5 is a register for setting the request address, and 6-1 to 6-6. n is a comparison circuit for comparing the contents of the lower bits and the tag memories set in the register 5, 7, 10-1 to 10-n, 11 and 21-1 to 21-n are selection circuits, and 8 is replacement control. Logic circuitry, 9 is write control means for controlling the writing of data from the data memories, 12 is an OR circuit, 13 is a gate circuit, 15 is a write data line, 16 is a read data line, 17 is a coincidence signal (FOUND) ) Is a coincidence detection signal line, 18 is a change detection signal line Mismatch-light change signal is a signal line (NF · CHF) is the output, 20 is a disparity-signal line through which the output change signal (NF · CHG), 22 is a set address line, 23 shows the internal block address line.

FIG. 2 is a block diagram specifically illustrating the data memory of FIG. 1, wherein each block 1-1 to 1-n of the data memory has a capacity of 64 bytes, and access includes 8 bytes each. Unit (B1-0 to B1-7)... (Bn-0 to Bn-7). Data is read out from the setting address line 22 according to the setting address, selected from the internal block address line 23 by the selection circuits 21-1 through 21-n in accordance with the internal block address, and thereafter, the selection circuit. Is applied to (11). The selection circuit 11 performs a selection operation according to the output signals of the selection circuits 10-1 to 10-n and provides the selected data on the read data line 16.

3 illustrates write control means of a buffer memory shown in block form, and reference numeral 30 denotes a coincidence detection signal FOUND, an inconsistency-invariant signal NF and CHG, and an inconsistency-change signal NF and CHG. A write data control circuit for receiving a control signal CONT · T (x-1) of the timing T (x-1) output from the control shift register 51 and outputting a read enable signal to the signal line 43. Example number 31 shows a data pool circuit composed of a register 47 for setting the write data input from the write data line 40 and the selection circuits 48 and 49. Example number 32 Write data register in which data is set at timing Tx, 33 are read data registers in which data is set in timing Tx, 34 are input data setting registers 35 inputted from the feed data line 41, and byte mark signal lines. Byte m from (44) A merge circuit for combining the output data of the registers 32 and 33 in response to the signal, 36 is a checkcheck circuit, 37 is a register for setting data at timing Ty, 38, 39, 45, Reference numeral 46 denotes a gate circuit, 50 denotes a data pool control circuit for inputting a read address to the selection circuits 48 and 49 through the read address line 42, 51 denotes continuous shift of the control signal from timing Ti to Tx to Ty. Control shift register.

4 is an explanatory diagram of the control shift register 51 illustrated in FIG. A valid signal V, an operation code and a sub operation code are set at timing T1 in the first stage of the shift register 51 and then transferred to the next stage, timing T2? Tx? Ty. As can be seen from the figure, at timing T (x-1), a control signal CONT T (x-1) including a valid signal and an operation code and a sub-operation code is applied to the write data control circuit 30. All. At timing Ty, the control signal CONTTy is applied to the recording control means 9. In the case of the sending operation, the sub operation code MO is "ON", and in the case of the sending operation, the sub operation code MI is "ON", and in the case of the tag sending operation, the sub operation code TMI is "On"

FIG. 5 shows a write data control circuit 30 in the buffer memory write control means of FIG. Example number 52 is a decoder for decoding the operation code (OPC), 53-60 is a gate circuit. The valid signals V, the sending signal MO, the sending signal MI, and the tag sending signal TMI of the control signal CONT · T (x-1) are applied to the gate circuits 59 and 60, and if only the valid signal V is "1", the gate circuit 59 and 60 are applied. The output of (59) becomes "1". When the valid signal V and the feed signal MI are "1", the output of the gate circuit 60 becomes "1". The outputs STR and BSTR of the decoder 52 are memory signals and block memory signals, respectively, and the read enable signal is output to the signal line 43.

FIG. 6 shows the main part of the write control means 9 in FIG. 1 in the form of a block, with reference numerals 61-76 designating a gate circuit and 80-81 designating a decoder. The gate circuits 69 and 70 have control signals CONT. The valid signal V of Ty, the sending signal MO, the sending signal MI, and the tag sending signal TMI are supplied. The decoder 80 decodes the operation code OPC of the control signal CONT.Ty and outputs a storage signal STR, a rockable memory signal BSTR, or an instruction fetch signal FCH. The decoder 81 decodes an internal block address from the address line 23 and writes B1-0 to Bn-0 to the block of the data memory. B1-7 to Bn-7 are specified. For example, if the 3-bit inner block address is "10", B1-2 to Bn-2 are assigned to the block. The outputs of the gate circuits 71-76 are write enable signals WE1-0 to WE1-7 corresponding to each other in the blocks of the data memory, respectively. (WEn-0) to (WEn-7). The example letters VT1 to VTn denote output signals of the selection circuits 10-1 to 10-n in FIG.

The operation of the present invention will be described below.

In the control shift register 51, sub-operation codes, operation codes, and valid signals of operation information executed at the time of a memory access request are set. In normal read processing, the operation code instructs instruction drawing and the valid signal V is "1". The request address REQA is set in the register 5.

The first flow includes (a) tag memories 2-1 to 2-n to detect whether the data of the request address exists in the data memories 1-1 to 1-n. (B) read the replacement data memory 4 for determining the replacement block or updating the contents of the replacement data memory 4, and (c) a change bit if the data of the request address does not exist in the buffer memory. The memories 3-1 to 3-n are read out, and (d) the read data is set in the register 37. Then, according to the conditions in the first flow, the sub operation code is set in the control shift register 51 and the operation proceeds to the delivery flow, the delivery flow and the tag delivery flow.

In normal read processing, the contents read from the tag memories 2-1 to 2-n and the request address selected in the register 5 are compared with the comparison circuits 6-1 to 6-n. Are compared, and if the data of the request address does not exist in the data memories 1-1 to 1-n, any one of the comparison circuits 6-1 to 6-n outputs " 1 " Thus, the coincidence detection signal FOUND on the signal line 17 becomes "1" by this signal. Furthermore, any one of the outputs of the selection circuits 10-1 to 10-n becomes "1", which is supplied to the selection circuit 11 and the write control means 9.

According to the setting address of the request address REQA, data is read from the data memories 1-1 to 1-n, and the selection circuits 21-1 to 21-n are respectively set according to the internal block address. Read data of a part of the designated block is supplied to the selection circuit 11. If any one of the selection circuits 10-1 to 10-n outputs " 1 ", then the selection circuit 11 has the same setting as that selected by the selection circuits 21-1 to 21-n. A part of read data of a block of an address is selected and a part of read data of one block is output on the read data line 16.

If the data of the request address does not exist in the data memories 1-1 to 1-n, the coincidence detection signal FOUND becomes " 0 ". In that case, the replacement data memory 4 is read out to determine the replacement block in the replacement control logic circuit 8. Further, if the change bit memories 3-1 to 3-n are read out and no bit change is detected, the inconsistent unchangeable signal NF-CHG becomes "1" on the signal line 19, and if the bit change is detected. When the mismatch-change signal NF-CHG on the signal line becomes " 1 "

The feeding operation will be described below.

If NF CHG = "1", the operation proceeds to the feed flow. That is, the operation code indicates instruction fetch, and the input signal MI of the sub operation code becomes "1". In the feed flow, since 64 bytes of data are recorded, a block is fed into the data memory by causing the shift register 51 to process the feed flow in units of 8 bytes continuously. In the feed flow, data read from the main memory is set in the feed data setting register 34 through the feed data line 41 and set in the read data register 33 through the gate circuit 46 at timing Tx. do. If the byte mark signals from the signal line 44 are all "0", the merge circuit 35 outputs the contents of the read data register 33, and the contents are output through the error check circuit 36 at timing Ty. It is set in the register 37. Therefore, the data set in the register 37 is outputted to the write data line 15, stored in the replacement blocks of the data memories 1-1 to 1-n, and supplied as read data to the access request terminal.

The delivery operation will be described below.

If NF CHG = "1", the operation proceeds to a delivery flow. Since 64 bytes of data are input to the main memory during transmission, a block is sent out to the main memory by the shift register 51 so as to continuously process the 8-byte sending procedure 8 times. In this delivery flow, the replacement target blocks of the data memories 1-1 to 1-n are sent out, and then the operation proceeds to the delivery flow. The operation of the feed flow is as described above.

The tag flow follows the feed flow. In the tag feed flow, an address is registered in the tag memory, the contents of the replacement data memory 4 are updated, and " 0 " is recorded in the change bit memory.

Processing for writing data of a part of the block is performed in the same manner as the read processing described above. That is, the tag memories 2-1 to (2-n) are read out, and it is detected by the comparison result of the comparison circuits 6-1 to (6-n) whether or not the data of the request address exists. .

If the coincidence detection signal FOUND is " 1 ", " 1 " is stored in the change bit memories 3-1 to 3-n, and the block containing the data of the request address is read out from the data memory. The read data on the read data line 16 and the write data on the write data line 40 are supplied to the merge circuit 35, and the combined data in accordance with the byte mark signal on the signal line 44 is used as an error check circuit ( Is checked by 36). In this case, if no error is detected, the data is set in the register 37 and output to the write data line 15.

The data output to the write data line 15 is input to the data memories 1-1 to 1-n to write write signals WE (WE1-0 to 1) which are outputs of the internal block address and the write control means 9. Data is recorded in one part of the block determined by WE1-7… WEn-0 to WEn-7).

The replacement target block is determined by the contents read from the replacement data memory 4 in which the data of the request address does not exist, and any bits are read by the contents read from the change bit memories 3-1 to (3-n). When no change is detected, the feed data and the write data are combined together, and the combined data is input to the data memory as write data and written in the designated block as in the above case. Thus, the request address is stored in the tag memory and " 1 " is written in the change bit memory. If a bit change is detected, the replacement object block is sent out, and then the write data is operated by the above operation.

The operation is substantially the same as that used in the swap system. The present invention has the advantage of the is-warp system for block memory processing. First, a description will be given regarding the case where the data of the request address REQA exists in the buffer memory. In this case, the coincidence detection signal FOUND becomes " 1 " and the operation code OPC of the control signal CONT.T (x-1) output from the shift register 51 at timing T (x-1) is It is decoded by the decoder 52, so that the block memory signal becomes " 1 ". Moreover, since only the valid signal V of the sub-operation code becomes "1", the gate circuit 56 outputs "1" and the read enable signal on the signal line 43 becomes "1".

The write data are set in the register 47 of the data pool circuit 31 from the write data line 40, and since the read enable signal is " 1 ", the data are selected in the selection circuits 48 and 49 at the timing Tx. And in the write information register 32 via the gate circuits 38 and 39. In this case the byte mark signals are all "1".

Since the byte mark signals from the signal line 44 are all "1", the merge circuit 35 writes the data register 32 to the error check circuit 36 regardless of the read data of the read data register 33. The write data of the data is supplied, and the data applied to the error check circuit 36 is set in the register 37 at timing Ty.

Control signal CONT. Ty's operation code (OPC) is decoded by the decoder 80 at timing Ty, and the block memory signal BSTR becomes "1". Furthermore, since the valid signal V of the sub operation code is "1", the gate circuit 64 outputs "1".

In block storage, the shift register 51 is executed eight times (8 bytes x 8 = 64 bytes) in the first flow in the eight-byte unit in which the block memory signal BSTR is "1" and the valid signal V is processed at "1". All data is written to one block of the data memory by inputting to. For example, in the first first flow, the internal block address on the address line 23 is decoded to the decoder 81, and the write enable signal WE1-0 is selected circuits 10-1 to (10-n). The output write data of the register 37, which is set to "1" by the output signals VT1 to VTn and inputs to the data memories 1-1 to 1-n via the write data line 15, is stored in the data memory 1 -1) is written to block B1-0. After that, if the second to eighth first flows of the block storage section continue to be inputted to the shift register 51, the internal block address of the address line 23 becomes the address line if the first flow continues to be inputted to the shift register 51. The internal block address of (23) is set to a value obtained by adding 1 to the value in the first flow, and the write enable lines WE1-1 to WE1-7 become "1" by understanding, and the data memory 1 In blocks B1-1 to B1-7 of -1), data is recorded in continuous order. Furthermore, "1" is written to the position of the corresponding block of the change bit memory.

If the data of the request address does not exist in the buffer memory and the contents of the replacement block do not change after the replacement block is stored from the main memory to the buffer memory, the coincidence detection signal FOUND is "0", and the signal line 19 The mismatch-invariant signal NF-CHG is "1". In this case, data is written to the data memories 1-1 to 1-n in the same manner as when the coincidence detection signal FOUND is " 1 ". In other words, no sending of the replacement block and sending to the block containing the data of the request address from the main memory occurs. The write data is set in the register 32 at timing Tx. Since the byte mark signals are all "1", the data in the register 32 is set in the register 37 at timing Ty regardless of the data in the register 33, and the setting data in the register 32 is written to the write data line ( 15) and the control signal CNOT. Data is written into the data memory by a write enable signal output in accordance with Ty and the internal block address.

When the contents of the replacement block are changed after the replacement block is stored in the main memory in the buffer memory, the inconsistency-change signal NF-CHG " 1 " In this case, the operation of the delivery flow proceeds. That is, the operation code instructs block memory and the transmission signal MO of the sub-operation code becomes "1". As a result, the replacement block is sent out. Then, the feeding operation proceeds. That is, the operation code instructs block storage and the feed signal MI of the sub-operation code becomes "1". The control signal CONT. Since T (x-1) becomes V = "1", MI = "1", MO = "0", and TMT = "0", the gate circuit 60 outputs "1" and the decoder 52 The block memory signal BSTR derived from the " 1 " Since NF · CHG = "1", the output of the gate circuit 58 is "1", and the read enable signal of the signal line 43 is "1".

The write data pooled in the data pool circuit 31 is set in the write data register 32 via the gate circuits 38 and 39 at timing Tx, and the byte microphone signals of the signal line 44 are all " 1 " The merge circuit 35 writes the data register 32 in the register 37 via the error check circuit 36 at timing Ty regardless of the data in the register 33 in which the transfer data of the register 34 is set. Set only the content of.

The control signal CONT.Ty is inputted to the write control means 9 at timing Ty so that the outputs of the gate circuits 70 and 66 become "1", and the decoder 81 and the selection circuit 10-1. Data is written to the data memory by the write enable signal determined by the outputs of "-" (10-n).

Next, it is transferred to the operation of the tag input flow. In the block storage instruction, when NF · CHG = " 1 ", that is, when the data of the request address is not in the data memories 1-1 to 1-n, and the block is the data memories 1-1 to 1 If the contents of the replacement block do not change after being stored as -n), as described above, the direct data is recorded in the replacement block without the operation of the sending and receiving flow. Therefore, if the block storage instruction continues, the invalid operation time is removed from the recording process and the advanced processing is allowed. In particular, in the case of handling a large amount of data, the data is written by a block storage instruction in the same size area or an integer multiple of the blocks of the buffer memory. Therefore, the output of the buffer memory can be greatly improved by eliminating the sending and sending operations.

It will be apparent that various modifications and changes may be made without departing from the scope of the basic concepts of the invention.

Claims (1)

A buffer memory control system which can be connected before operation to a processing device for generating a request signal, recording data and input data in a main memory, wherein the data is selectively output and generated by the processing device according to the status of the request signal. And data memory (1-1) to (1-n) operatively connected to the main memory and the processing apparatus for storing data used, and indicating whether data processed by the processing apparatus is stored in the data memory. Tag memories (2-1) to (2-n) connected before operation to the processing apparatus for storing a tag signal, and a change bit signal indicating whether or not data stored in the data memory has been changed by the processing apparatus. Change bit memories (3-1) to (3-n) operatively connected to the processing apparatus for storing the data, and the data stored in the data memory A replacement data memory 4 operatively connected to the processing device for storing replacement signals indicative of replacement, and stored in the data memory according to the status of the request signal, tag signal, change signal, and replacement signal; Write control means 9 operatively connected to the tag memory, a replacement data memory, a data memory, operatively connected to the processing apparatus, and operatively connected to the processing apparatus for controlling data; Operatively connected to said change bit memory, replacement data memory, data memory, and write control means for controlling the storage of the feed data of said data memory in accordance with the state of a signal, a change signal and a replacement signal; And a buffer memory write control circuit (FIG. 3) operatively connected to the memory. The tag signal indicates that the data requested by the processing device is not in the data memory and the replacement signal indicates that the data stored in the data memory can be replaced, and the data stored in the data memory The change signal indicates that there is no change, and when the data stored in the data memory by the processing device has the same size or an integer multiple of one block, the write data is transferred from the main memory to the block in the buffer memory. And the tag signal, the replacement signal, and the change bit signal are generated in parallel by each of the tag memo, the replacement data memory, and the change bit memory.

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