KR840006105A - Extraction and Demodulation FIR Filters - Google Patents

Abstract

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Description

Extraction and Demodulation FIR Filters

As this is a public information case, the full text was not included.

1 and 2 are block diagrams of portions of digital TV processing circuitry showing FIR filters used in two methods by the present invention.

4 is a block diagram of a parallel register bandpass filter according to the present invention, which is the same as that of the filter in FIG.

Claims (12)

The data input signal is sampled at a given sample rate to extract the filtered continuous output sample, and a plurality of weight circuits for weight signal samples having input and output terminals, respectively, and connected to the output terminal of the weight circuit are generated by the weight circuit. A sample data filter having an addition circuit for generating a sum of weighted signal samples, the sample data filter comprising a signal sample delay stage that is cascaded and has an output tap and is less than the given speed (f _c ) (1 / 3f _c ) A plurality of mobile registers clocked at < RTI ID = 0.0 > and < / RTI > And a means (DEMUX) for selectively inputting the movement register to the moving register. In the sample data FIR filter according to claim 1, the means for connecting the input terminal of the weight circuit to the axial force tap alternately selects the weight circuits (K _2, K ₄ , K _6, K ₈ ) and the output tap ( Extracting and demodulating filter comprising multiplexing means (110) for connecting to P ₂ , M ₁ ; P ₄ , M ₃ ; P ₄ , M ₅ ). The sample data FIR filter according to claim 1 or 2, wherein the input signal (video sample) is a video signal in which the + E, + Q, -I, and -Q signal samples are repeated. Are two (Pi, Mi), where -I and + Q input samples are applied to the first register Pi of the two shift registers, and -I and -Q input samples are applied to the second register Mi. Extraction and demodulation filter, characterized in that applied. 4. The sample data FIR filter according to claim 3, wherein the first (Pi) and second (Mi) shift registers have the same number (5) of cascaded delay stages, with each stage of each register represented by one. And the hole means P ₁ , P ₃ , P _{5 of} the first register Pi having an output tap are connected directly to the plurality of weight circuits K ₁ , K ₂ , K _9, respectively. Pairing means (M ₂ , M ₄ ) of the second register (Hi) having each are connected to the plurality of different weight circuits (K ₃ , K ₇ ), where pairing means of the first register having output taps (P ₂ , P ₄ ) and the hole means M ₁ , M ₃ , M ₅ of the second register with output taps alternately comprise the plurality of other weight circuits K | ₂ , K ₄ , K ₆ , K ₈ Extraction and demodulation FIR filter, characterized in that it is connected to). A sample data FIR filter according to claim 4, wherein each of the first (Pi) and second (Mi) shift registers has five cascaded delay stages, each stage having an output tap, wherein 109) is 11, each of the first five (K ₁ , K ₅ , K ₉ , K | ₃ , K ₇ ) of the weight circuit is the first (Pi), the third ( P ₃ ), the fifth (P ₅ ) stage and the second (M ₂ ), fourth (M ₄ ) stage of the second register (Hi) directly connected to the output tap, the sixth weight circuit (K ₄ ) alternately And the first and third stages of the first and second registers, respectively, and the seventh (K ₂ ) weight cycles are alternately connected to the first and second stages of the first and second registers, respectively. The first weight circuit K ₆ is alternately connected to the third and fourth stages of the first and second resistors, respectively, and the ninth weight circuit K ₈ is alternately the fourth of the first and second registers. Extraction and demodulation FIR filter, characterized in that connected to each of the fifth stage. In the sample data filter of claim 1, wherein the input signal INPUT SAMPLES is composed of repeated continuous insertion samples (+ I, + Q, -I, -Q) generated at a given sample rate (4f _sc ), The plurality of mobile registers 40 and 41 store information that is continuously moved between consecutive stages. With R parallel shift registers clocked at a given speed of 2f _sc , where R is their order or divisor including the number of input samples inserted. The circuit 42 Extracting and demodulating the FIR filter, characterized in that it provides a copy of the particular sample of the inserted sample at a given rate of. In the sample data filter according to claim 6, the inserted continuous signal sample is a video sample of + I, + Q, -I, -Q, and the number of R is two and the input selection means is + I and + Q input samples. An extraction and demodulation FIR filter, characterized in that the first register (40) is operated so that the -I and -Q input samples are applied to the second register (41). In the sample data FIR filter according to claim ₇ , the weight circuits C ₁ -C ₇ supply only the filtered samples of + I and + Q sampled (2f _sc ) at 1/1 of the given speed 4f _sc . Extraction and demodulation FIR filter, characterized in that connected to the first (40) and second (41) resist output tap by a weight sample by a filter. The sample data FIR filter according to claim 7 or 8, wherein the input selecting means comprises first (44), second (45), and third (3) having a sample data input terminal, a control terminal and a sample data output terminal, respectively. 49) and the fourth (48) AND gate circuits, the first and second sample data input terminals, and the first (43) and second (50) OR gate circuits having sample data output terminals, and the sample data input terminals. First and second latch circuits having a clock input terminal and a sample data output terminal, and sample data input terminals of the first and third AND gates, and sample data input terminals of the first and second latch circuits. Means for connecting the sample data input signal source 59 to the inserted sample data input signal source 59, the sample data input terminals of the second and fourth AND gates to the sample data output terminals of the first and second latch circuits, respectively; Means for connecting the sample data output terminals of the first and second AND gates to the first and second sample data input terminals of the first OR gate. Means for connecting the sample data input terminals of the first and fourth AND gates, the means for connecting the sample data output terminals of the first and second OR gates to the first (40) and second (41) moving registers; Means for applying a first clock signal fsc generated at a quarter of the given speed 4fsc to the control input terminals of the first and fourth AND gates, and a second clock signal which is a complement of the clock signal. means for applying (fsc) to the control input terminals of the second and third AND gates, and the third clock signal Q _CL generated when a + Q insertion input sample is generated, the clock input of the first latch circuit. And means for applying to the clock input terminal of the second latch circuit a means for applying to the terminal and a fourth clock signal Q _CL generated when a -Q inserting input sample occurs. Demodulation FIR filter. In the sample data FIR filter according to claim 7 or 8, the first register 40 comprises eleven stages having output taps in the first, third, fifth, seventh, ninth, and eleventh stages. Extraction and demodulation FIR filter having A1-A11) and said second moving register (41) having six stages (B1-B6) having output taps at the sixth stage. In the sample data FIR filter according to claim 10, the weight circuit (C1-C7) is a component. Connected to the first, third, fifth, seventh, ninth, and eleventh stages of the first) travel resistor weight sample, the weight circuit being configured by component (1/2) of the second resistor weight sample. Extraction and demodulation FIR filter, characterized in that connected to the first stage. In the sample data FIR filter according to claim 7 or 8, the demultiplexing circuits LI and LQ are connected to the summation circuit 42 so as to filter the filtered continuous samples of + t and + Q of + t and + Q. Extraction and demodulation filter, characterized in that separated by the filtered sample output signal. ※ Note: The disclosure is based on the initial application.