KR840001462B1 - Semiconductor memory circuit - Google Patents

Abstract

A semiconductor memory circuit, comprising memory cells; word lines, hold lines and bit lines connected to respective memory cells; and a hold-current controlling circuit. The hold-current controlling circuit comprises identical controlling circuit elements connected to respective hold lines and a constant-current source commonly connected to the controlling circuit elements. Each of the controlling circuit respective hold lines, when corresponding word lines change from a selection status to a non-selection status, until the voltage level of the hold line reaches a full "L" or "H" level, and means for blocking a flow of electric charges from the hold line.

Description

Semiconductor memory circuit

1 is a schematic diagram showing an arrangement of a semiconductor memory circuit of a servant.

FIG. 2A is a partial circuit diagram of a semiconductor memory circuit including a conventional first type holding current control circuit. FIG.

2B is a partial circuit diagram of a semiconductor memory device including a conventional second type holding current control circuit.

2C is a partial circuit diagram of a semiconductor memory circuit including a holding current control circuit according to the present invention.

FIG. 3a is a time graph showing the operation of the circuit shown in FIG. 2a.

FIG. 3b is a time graph showing the operation of the circuit shown in FIG. 2b.

FIG. 3c is a time graph showing the operation of the circuit shown in FIG. 2b.

4A, B, and C are circuit diagrams showing the stepwise operation of the retention control circuit shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory circuits, and more particularly to a hold-current control circuit mounted in this circuit.

In general, a semiconductor memory circuit mainly includes a large capacity memory device. The memory element is arranged at the intersection of a word line and a bit line. The desired memory elements are selected at their ends by both a word decoder connected to the word line and a bit decoder connected to the bit line.

The data to be read out is generated from the other end of the corresponding bit line to which the selected memory device is connected after the data to be written is supplied to the memory device. Each memory element is generally connected to a hold line as well as a word line through which the above-mentioned holding current flows. This holding current functions to hold data stored in the memory device. This holding current is absorbed by the holding current source. Note that the holding current source absorbs the discharge current.

This discharge current is generated by the charges retained in the parasitic capacitor and the stray capacitor distributed in the word line of the memory element. The more the discharge current is absorbed by the holding current, the higher the access speed of the memory element becomes.

Therefore, the holding current control circuit as described above has been proposed to absorb the discharge current very quickly.

The holding current control circuit is interlocked with the holding current source and absorbs the above-mentioned discharge current calculated by the charge held in the capacitor as well as the holding current.

Many forms of such holding current control circuits have been proposed and used in practice. However, all of these holding current control circuits according to the prior art, although each of these holding current control circuits effectively performs the fast accessing operation on the word line that changes from the selected state to the non-selected state, the holding current circuit is non-operational. It has the same disadvantage that it is not possible to effectively perform the high speed accessing operation for the word line that changes from the selected state to the selected state. Herein, the term of selection state means the condition under which the word line is selected by the word decoder, while the term of non-selection state means that the word line is not selected by the word decoder.

Thus, an object of the present invention is to provide a holding current control circuit for effectively performing a high speed accessing operation for both a word line that changes from a selected state to a non-selected state and a word line that changes from a non-selected state to a selected state in a semiconductor memory circuit. To provide. The present invention will be described in detail below with reference to the accompanying drawings.

1 is a schematic diagram showing an arrangement of a conventional semiconductor memory circuit, in which reference numeral 11 denotes a memory element array composed of, for example, 2n × 2m memory elements. One desired memory device from the plurality of memory devices is a word decoder 12W corresponding to address data A ₀ to A _n-1 and address data A _n to A _{n + m-1,} respectively. And the bit decoder 12B.

The word line 13 extends from the word decoder 12W in the direction of the array 11, and the bit line 14 extends from the bit decoder 12B into the array 11. The data Dout to be read out is calculated by the sense amplifier 19 via the corresponding bit line among the bit lines and the pre-se-nse amplifier 18.

The memory element array 11 is connected to the holding current source 16 via the hold line 15. The holding current flows through the hold wire 15 and is absorbed by the current source 16. This current source 16 is also usefully used to absorb the discharge current generated by the charges held in the parasitic capacitors and the stray capacitors distributed along the word lines of the memory element.

In this case, the discharge current must be absorbed very quickly in order to perform the fast accessing operation of the memory device. In order to perform this high speed accessing operation, a holding current control circuit 17 is used for the semiconductor memory element. In particular, it should be understood that the present invention focuses on the holding current control circuit 17.

In the prior art, two types of holding current control circuits have been proposed. One form of the holding current control circuit of the prior art is shown in FIG. 2A and the second form is shown in FIG. 2B. Further, the holding current control circuit according to the present invention is depicted in FIG. 2C.

3a, b, and c are time graphs showing the circuit operation shown in FIGS. 2a, b, and c, respectively. In FIG. 2A, the memory element array 11 includes a large number of memory elements. In FIG. 2A only four memory elements 21-11, 21-1m, 21-n1, 21-nm are shown. Since the memory elements are all arranged in the same circuit, only the memory elements 21-11 are shown in detail.

As the memory elements 21-11 are understood in the figure, each of the memory elements basically constitutes a flip flop including a pair of multi-emitter transistors. One emitter of each transistor is connected to a pair of bit lines 14-1, and the other emitter of each transistor is connected to a hold line 15-1. As a result, the flip flop of the memory device is connected between each word line and hold line. In the example of FIG. 2, the memory elements 21-11, 21-1m, 21-n1, 21nm are connected between the word line 13-1 and the hold line 15-1. The word line 13-1 is connected to the word drive transistor 22-1. The remaining word line is connected to each word driving transistor.

These word drive transistors 22-1 to 22-n are included in the word decoder 12W (see FIG. 1).

On the other hand, the hold lines 15-1 to 15-n are connected to the holding current source 16 (see FIG. 1), and the holding current sources 16 are connected to the hold lines 15-1 to 15-n, respectively. Constant current sources 23-1 to 23-n. Each of the current sources 23-1 to 23-n absorbs a constant current Ih. The constant current sources 23-1 to 23-n interlock with the holding current control circuit 210. This circuit 210 includes diodes 211-1 to 211-n. Each of the diodes 211-1 to 211-n is connected to a constant current source 212 whose anodes are connected to the hold lines 15-1 to 15-n, respectively, and the cathode absorbs a constant current ΔIh. It is connected in common.

For example, if the memory element 21-11 is accessed by the address data of the word decoder 12W (FIG. 1) and the bit decoder 12B (FIG. 1), the word line 13- 1) is driven by the word drive transistor 22-1.

Therefore, the word line 13-1 is held in the selected state. In this case, the voltage level V _W of the word line 13-1 is the "H" level (concerned bell), as understood in FIG. 3A. In FIG. 3A, curves 30SN and 30NS by dotted lines are obtained when the circuit 210 is not used, and thick lines 31SN and 31NS are obtained when the circuit 210 is used. Curves 30SN and 31SN are obtained when the word line changes from the selected state to the unselected state. Curves 30NS and 31NS are obtained when another word line changes from the unselected state N to the selected state S. FIG. As an example of the above-mentioned case, when the word line 13-1 changes from the selected state to the unselected state (the state corresponding to the curve 30SN or 31SN in FIG. 3A), the word line 13-n (FIG. 2A) It changes from a non-selection state to a selection state (corresponding to curve 30NS or 31NS in FIG. 3A). When the circuit 210 of FIG. 2a is not used, the intersection between the curves 30SN and 30NS is generated at time to as shown in FIG. 3a.

Note that data switching occurs after one time from one of the memory elements of the word line 13-1 to one of the memory elements of the word line 13-n. Therefore, in order to achieve the high speed access of the memory device which desires this time, it must be moved to the left in FIG. 3a. The holding current control circuit 210 is useful for shifting from time to time t1.

The reason is as follows. When the word line 13-1 is in the selected state, the voltage level of the word line 13-1 is at the "H" level. Therefore, the voltage level of the hold line 15-1 is also at the "H" level. In this case, the charge is retained in the drift capacitors distributed along the word line 13-1, and also in the parasitic capacitors formed in the memory elements 21-11 to 21-1 m. Thereafter, the word line 13-1 is selected. When changing from to the non-selected state, the charge held in the above-mentioned capacitor must be discharged very quickly via the hold line 15-1. Without the circuit 210, the discharge current is only absorbed by the current source 23-1. However, if the circuit 210 is used, only the diode 211-1 is conducting and the discharge current can be absorbed by the current source 212 of the circuit 210 as well as the current source 23-1. A steep slope of the curve 31SN of 3 degrees can be obtained.

However, the circuit 210 has the following disadvantages. The disadvantage will be apparent with reference to Figure 3a. That is, although it is more preferable that the slope of the curve 31NS is steep, the corresponding portion of the curve 31NS becomes a gradual curve because of the circuit 210. This is further caused by the constant current source 212 via the diode 211-n in which the charging current for charging the above-mentioned capacitor is in the conduction state when the word line 15-n changes from the non-selected state to the selected state. Because it is absorbed. This can be referred to the current ΔIh in FIG. 3a.

It should be noted that, in order to shift the time to the left (as in FIG. 3a) as far as possible, the slope of the curve 30SN should be very urgent, and at the same time the slope of the curve 30NS should be very urgent. FIG. 2B is a partial circuit diagram of a semiconductor memory circuit including the holding current control circuit 220 of the second aspect of the prior art.

The memory circuit using the holding current control circuit 220 can improve the memory access specification in comparison with the memory circuit using the circuit 210 described above in FIG. 2A.

This improvement will be apparent with reference to Figure 3b. The intersection between the curves 32SN and 32NS in FIG. 3B occurs at a time t _{2 which} is faster than the time to in FIG. 3A because of the circuit 220. This is because the current Ih + ΔIh absorbed by the constant current source 23-1 and the current source 221-1 flows to a time t ₂ following the time t ₂ .

Since the current In + ΔIh continues to flow after the time t ₂ , the slope of the curve 32SN is steeper than the curve 31SN of FIG. 3A. However, the curve 32NS was not improved compared to the curve 31NS of FIG. 3A.

One of the holding current control circuits 220, in particular the current sources 221-1 to 221-n, is described in the 1979 IEEE International Solid-State Circuits Conference (ISSSCC), published February 15, 1979.

The operation of these current sources 221-1 to 221-n will be described with reference to FIG. 2B.

When the voltage level of the word line 13-1 is at the "H" level, the voltage level at the points A and B is also at the "H" level. Then, when the word line 13-1 changes from the selected state to the non-selected state, the voltage level at point A decreases to the "L" (low) level. However, the voltage level at point B maintains the “H” level because of the charge retained in capacitor C ₂ . At that time, the charge of the capacitor C ₂ is discharged to the time constant c ₂ × r ₂ through the resistor R ₂ .

Here, the symbol c ₂ (r ₂ ) represents the capacitance of the capacitor C ₂ and the resistance of the resistor R _2, respectively. During the time when the voltage level at point B decreases to the "L" level, transistor T ₃ is in a conductive state. Therefore, the current ΔIh continues to flow after time t _{2 in} FIG. 3b.

At the same time, the word line 13-n changes from the non-selected state to the selected state. In this case, the current source 221-n operates as follows. Since the circuit arrangement of the circuit 221-n is the same as the circuit arrangement of the circuit 221-1, the following description will be made with reference to the circuit elements of the circuit 221-1 as shown in FIG. 2B. When the word line 13-n is in the unselected state, the voltage level at points A and B is at the "L" level.

Thereafter, when the line 13-n changes from the non-selected state to the selected state, the voltage level at the point B increases to the "H" level. Thus, transistor T ₂ is conductive. The capacitor C ₂ is then charged and the voltage level at point B increases to the "H" level. Thus, transistor T ₃ is conducted immediately after transistor T ₂ is conducted. Therefore, the current ΔIh continues to flow through the transistor T ₃ after the time t ₂ . It will be understood with reference to the current ΔIh in FIG. 3b. As a result, the slope of the curve 32NS (FIG. 3B) is a gradual slope as compared with the curve 30NS. The transistor T ₁ is applied with a reference voltage Vref at its base to supply a set voltage level to the point A.

2C shows a partial circuit diagram of the semiconductor memory circuit including the holding current control circuit 230 of the present invention. The memory circuit using the holding current control circuit 230 can improve the memory accessing characteristics as compared with the memory circuit using the circuit 220 of FIG. 2B and the circuit 210 of FIG. 2A. This improvement will be apparent with reference to FIG. 3C.

The intersection between the curves 33SN and 33NS in FIG. 3C occurs at a time t ₃ earlier than the time t ₂ in FIG. 3B because of the circuit 230. This is due to flow through the constant current source (23-1) and the time (t ₃ ') following a current (Ih + ΔIh) absorbed by the circuit 230, the time (t _3).

Since the current Ih + ΔIh continuously flows after the time t ₃ , the slope of the curve 33SN becomes more steep than the curve 31SN of FIG. 3a. Moreover, the slope of the curve 33NS is more urgent than the curve 31NS of FIG. 3A and the curve 32NS of FIG. 3B. In other words, the inclination of the curve 33NS is substantially the same as the desired curve 30NS.

The reason for the abovementioned improvement in accordance with the invention stems from the fact that the current Ih does not start flowing from time t3 but from time t3 ″. When the corresponding word line 13-n changes from the non-selected state to the selected state, since the current Ih is not absorbed from the hold line 15-n, both of the above-mentioned parasitic capacitors and drift capacitors are connected to the word lines ( 13-n) and a storage element of this word line 13-n, and is very rapidly charged by the current supplied from the word driving transistor 22-n as shown in FIG. Can lose.

The time t3 " may be freely preset by appropriately selecting the capacitance values of the capacitors C ₁₁ to C _{n1 of} FIG. 2C and the resistance values of the resistors R ₁₁ to R _n of FIG. 2C. In FIG. 2C, each of the parallel circuits of the capacitors C ₁₁ to C _n1 and the resistors R ₁₁ to R _n1 are connected to Schottky transistors ST ₁₁ to ST _n1 , respectively.

The emitters of the transistors ST ₁₁ to ST _n1 are commonly connected to the constant current source 212 (see also FIG. 2A). As understood from FIG. 2C, the circuit 230 of the present invention is very simple in structure compared to the circuit 220 of FIG. 2B, which is another benefit of the present invention.

In particular, the number of capacitors and transistors is half the number used for the circuit 220. The operation of this holding current control circuit 230 will be described with reference to FIGS. 4A, b, and C. FIG. First, referring to FIG. 4A, when the word line 13-1 is in the selected state, the voltage level at the base of the transistor 22-1 is at the "H" level, and the line 13-1 and the line 15-1. The voltage level at is also the "H" level. Therefore, the Schottky diode SD ₁₁ is reverse biased.

Since the Schottky diode is included in the Schottky transistor, if the Schottky diode SD ₁₁ is not shown in Fig. 2c, and if the transistor of the circuit 230 is composed of a normal transistor, then that general diode is a common transistor. It can be understood that it is inserted between the base and the collector.

In this case, the Schottky diode SD ₁₁ is in a non-conductive state, and the voltage level at the point C becomes the "H" level. This "H" level is defined as the reference voltage (Vref). Since the voltage level at point C is at the "H" level, the Schottky transistor SD ₁₁ is conducted. Therefore, the current of the entire ΔIh is absorbed by the constant current source 212.

At the same time, the base voltage level of the transistor 22-n becomes the "L" level, and the voltage levels of the lines 13-1 and 15-1 also become the "L" level. In this case, the Schottky diode SD _n1 is forward biased, and a current Δi flows from the voltage source Vref through the resistor R _n1 and the diode SD _n1 . Therefore, the voltage level of the point D becomes the "L" level, and thus the Schottky transistor ST _n1 is nonconductive.

Since the current Δi flows through the resistor R _n1 , the magnitude of the current Δi is much lower than the current ΔIh. Referring to FIG. 4, when the word line 13-1 is changed from the selected state to the non-selected state, the word line 13-n is changed from the non-selected state to the selected state at the same time. In this case, the base voltage level of the transistor 22-1 changes from the "H" to the "L" level, and thus the voltage level of the lines 13-1 and 15-1 changes from the "H" to the "L" level.

Contrary to the above, the base voltage level of the transistor 22-n changes from the "L" to the "H" level, so that the voltage levels of the lines 13-n and 15-n are "L" to "H". Change to level. In this case, the diode SD ₁₁ changes from the reverse bias type to the forward bias type, while the diode SD _n1 changes from the forward bias type to the reverse bias type.

The following facts are very important. That is, when the voltage level of the line 15-1 changes from the "H" to the "L" level, the diode SD ₁₁ is conducted during the period. In other words, the diode SD ₁₁ preferentially becomes in a conductive state after the voltage level of the line 15-1 is reduced to a completely "L" level. This is because the level of the reference voltage Vref is selected to be slightly larger than the forward voltage of the diode and the full L level.

For example, if the full “L” level is -1.6V and the forward voltage is 0.4V, then the reference voltage (Vref) is -1.1. As a result, in FIG. 3C, the current Ih + ΔIh flows up to the time t3 ', which causes the curve 33SN to steeply slope. On the other hand, with respect to the diode SD _n1 , when the voltage level of the line 15-n changes from the "L" to the "H" level, the diode SD _n1 does not change rapidly from the conducting state to the non-conductive state. This is because the voltage level at point D changes very slowly from “H” to “L” level due to the presence of capacitor C _n1 and resistor R _n1 . Therefore, in Fig. 3c, the current? Ih is not absorbed by the line 15-n (Fig. 2c) during the time t3 to the time t3 ". This creates a curve 33NS as a substantially curved slope with the desired curve 30NS. The period t3-t3 " (the length can be freely determined by appropriately selecting the time constant determined by both the capacitors C ₁₁ to C _n1 and the resistors R ₁₁ to R _n1 ).

Finally, FIG. 4C shows the completion of data switching from the memory element of line 13-1 to the memory element of line 13-n. In this step, the current ΔIh flows through the transistor ST _n1 and the current Δi flows through the diode SD ₁₁ .

The voltage level at that point is indicated by the “H” or “L” level in FIG. 4C, which is the opposite of that shown in FIG. 4A.

By the above-mentioned in accordance with the present invention, a high speed memory accessing operation can be achieved.

Claims (1)

10. A semiconductor memory circuit comprising: a memory element, word lines, hold lines, and bit lines connected to respective memory elements; a first constant current source connected to the hold lines; and a holding current control circuit connected to the first constant current source. The holding current control circuit includes a parallel circuit composed of a resistor and a capacitor, a base connected to a first end of the parallel circuit, a first output terminal connected to each hold line, and a second output terminal connected to the second constant current source. And the same control circuit elements composed of a diode connected between the first output terminal and the base of the transistor and a reference voltage Vref applied to the parallel circuit and the second terminal and connected to respective hold lines. It is composed of a second constant current source commonly connected to the same control circuit elements, so that when the corresponding word line changes from the selected state to the unselected state, The charge is absorbed from each hold line until the level reaches a complete " L " (low) level. And interrupting the flow of electric charges from the respective hold lines for a predetermined interval after the data switching is executed.

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