KR830004720A - Signal conversion circuit - Google Patents

Signal conversion circuit Download PDF

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Publication number
KR830004720A
KR830004720A KR1019800003926A KR800003926A KR830004720A KR 830004720 A KR830004720 A KR 830004720A KR 1019800003926 A KR1019800003926 A KR 1019800003926A KR 800003926 A KR800003926 A KR 800003926A KR 830004720 A KR830004720 A KR 830004720A
Authority
KR
South Korea
Prior art keywords
transistor
collector
point
diode element
base
Prior art date
Application number
KR1019800003926A
Other languages
Korean (ko)
Other versions
KR850000581B1 (en
Inventor
쓰도무 니이무라
교오이찌 무라가미
아끼라 야마고시
Original Assignee
이와마 가즈오
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이와마 가즈오, 소니 가부시끼 가이샤 filed Critical 이와마 가즈오
Priority to KR1019800003926A priority Critical patent/KR850000581B1/en
Publication of KR830004720A publication Critical patent/KR830004720A/en
Application granted granted Critical
Publication of KR850000581B1 publication Critical patent/KR850000581B1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32Modifications of amplifiers to reduce non-linear distortion

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

내용 없음No content

Description

신호 변환회로Signal conversion circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명을 이득제어회로에 적용한 한 실시예의 접속도. 제6도 및 제7도는 본 발명의 한 실시예의 설명에 이용되는 접속도.5 is a connection diagram of one embodiment in which the present invention is applied to a gain control circuit. 6 and 7 are connection diagrams used in describing one embodiment of the present invention.

Claims (1)

제1다이오드 소자와 제1트랜지스터의 콜렉터. 에미터 통로의 직렬접속이 정전류 공급점 및 기준 전위점의 사이에 삽입되고, 제2다이오드 소자와 제2트랜지스터의 콜렉터. 에미터 통로와 제3다이오드 소자의 직렬접속이 상기 정전류 공급점 및 기준전위점의 사이에 삽입되며, 제1트랜지스터의 콜렉터와 제2트랜지스터의 베이스가 접속됨과 동시에, 제1트랜지스터의 베이스와 제2트랜지스터의 에미터가 접속되고, 제1트랜지스터의 콜렉터와 제2트랜지스터의 베이스의 접속점이 신호전류 공급단으로 되며, 제1다이오드 소자 및 제1트랜지스터의 콜렉터의 베이스의 접속점이 신호전류 공급단으로 되며, 제1다이오드 소자 및 제1트랜지스터의 점속점과 제2다이오드 소자 및 제2트랜지스터의 콜렉터의 접속점의 각각에 제3 및 제4트랜지스터의 베이스가 접속되고, 제3 및 제4트랜지스터의 에미터에 정전류원이 접속되며, 제3 및 제4트랜지스터의 각각의 에미터 또는 콜렉터로부터 출력을 취출하도록 한 신호변환회로.The collector of the first diode element and the first transistor. The series connection of the emitter passage is inserted between the constant current supply point and the reference potential point, and the collector of the second diode element and the second transistor. A series connection of the emitter passage and the third diode element is inserted between the constant current supply point and the reference potential point, and the collector of the first transistor and the base of the second transistor are connected, and the base and the second of the first transistor are connected. The emitter of the transistor is connected, the connection point of the collector of the first transistor and the base of the second transistor is the signal current supply terminal, and the connection point of the base of the collector of the first diode element and the first transistor is the signal current supply terminal. And the bases of the third and fourth transistors are connected to the point-of-point of the first diode element and the first transistor and the connection point of the collector of the second diode element and the second transistor, and the emitters of the third and fourth transistors are connected. A signal conversion circuit connected to a constant current source so as to take output from each emitter or collector of the third and fourth transistors. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019800003926A 1980-10-13 1980-10-13 Circuit for converting single-ended input signals to a pair of differential output signals KR850000581B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019800003926A KR850000581B1 (en) 1980-10-13 1980-10-13 Circuit for converting single-ended input signals to a pair of differential output signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019800003926A KR850000581B1 (en) 1980-10-13 1980-10-13 Circuit for converting single-ended input signals to a pair of differential output signals

Publications (2)

Publication Number Publication Date
KR830004720A true KR830004720A (en) 1983-07-16
KR850000581B1 KR850000581B1 (en) 1985-04-29

Family

ID=19217940

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019800003926A KR850000581B1 (en) 1980-10-13 1980-10-13 Circuit for converting single-ended input signals to a pair of differential output signals

Country Status (1)

Country Link
KR (1) KR850000581B1 (en)

Also Published As

Publication number Publication date
KR850000581B1 (en) 1985-04-29

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