KR830001930B1 - Electrode Structure of Semiconductor Device - Google Patents

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Description

Electrode Structure of Semiconductor Device

1 is a cross-sectional view showing an example of a conventional electrode structure used in a semiconductor device.

FIG. 2 is a table for explaining energy levels through the semiconductor device of FIG.

3 is a cross-sectional view of an electrode structure according to the present invention.

4 is an energy level diagram through the semiconductor device of FIG.

5 is an exemplary diagram of various P ⁺ -N ⁺ mosaic pattern layers.

6 is a cross-sectional view of another embodiment of the present invention.

7 is an energy level diagram through the semiconductor device of FIG.

8 is a cross-sectional view of a P-N junction diode according to the present invention.

FIG. 9 is a chart showing forward voltage versus forward current density characteristics of the diode shown in FIG.

FIG. 10 is a chart showing the forward current density versus recovery time constant characteristics of the diode shown in FIG.

11 is a cross sectional view of a P-i-N junction diode according to the present invention;

12 is a cross-sectional view of a PNPN thyristor according to the present invention.

13 is a cross-sectional view of an electrostatic induction thyristors according to the present invention.

14 and 15 are cross sectional views of the P-N junction diode according to the present invention, respectively.

The present invention relates to an electrode structure of a semiconductor device.

Conventionally, the electrode structure has been designed and determined in consideration of the behavior of majority carriers without considering minority carriers having a great influence on the characteristics of semiconductor devices. For example, in the conventional PN junction type diode (see Article 1), the diode has a high impurity concentration P ⁺ semiconductor layer 11, a low impurity concentration P ⁻ semiconductor region 12, and a high concentration N-type impurity. N ⁺ semiconductor layer 13 containing and the three metal layers above and the metal bacteria 14, 16 surrounding the upper and lower sides.

When forward voltage is applied to the electrode, the majority carrier (in this case, the hole is freed in a valence band, P ^- semiconductor region 12, P ⁺ semiconductor through the layer 11 and the metal electrode 14, however, N ⁺ from the semiconductor layer (13) P ^- is introduced into the semiconductor layer 12 (inject) P ^- metal electrode 14 from the semiconductor layer 12 The minority carriers (electrons in this case) that move toward the current have a limited current conduction and thus a large forward voltage drop resulting in a high junction between the P ⁻ semiconductor layer 12 and the P ⁺ semiconductor layer 11. Reflects and accumulates by the potential barrier ø. Another disadvantage of conventional PN diodes is the low speed recovery resulting from the minority carrier accumulation by high junctions. This phenomenon is J V. Vegan's "specific semiconductor junction properties and carrier axis About it is described in a technical paper called "

In order to solve the above problem, a method of removing the P ⁺ region 11 may be considered, but the P ⁻ region 12 has a low impurity lower than 10 ¹¹ / cm 3 to obtain a sufficient reverse blocking voltage. Such a method is not practical because it must have a concentration. At such low impurity concentrations, extremely high contact resistance is generated between the semiconductor and the metal electrode, causing a large forward voltage drop. In order to prevent such a contact resistance problem, it is conventionally required that the P ⁺ region has an impurity concentration of 10 ¹⁸ / cm 3 or more.

For this reason, the conventional semiconductor diode has a relatively high forward voltage drop, which inevitably causes a large power loss. Further, as described above, minority carriers accumulate in the P ⁻ semiconductor layer 12 and the reverse recovery time constant is increased, thereby causing reverse recovery.

The above problem is related not only to the electrode structure of the diode but also to the electrode structure of other semiconductor devices such as thyristors, transistors, and the like.

Therefore, the main object of this disclosure is to provide an electrode structure from which a semiconductor device with low loss is obtained, which electrode is formed between a semiconductor layer, a conductive layer formed on one side of the surface of the semiconductor layer, a semiconductor layer and a conductive layer. A first region serving as a passage of minority carriers and a second region serving as a passage of the first carrier having the same structure as that of the first carrier, and the first region and the third region are alternately formed adjacent to each other on the semiconductor layer.

In the electrode structure as described above, the passage of the minority carrier is formed between the conductive layer and the semiconductor layer so as to be adjacent to the passage of the multiple carriers and the free movement of the minority carrier and the multiple carriers is not limited at all. No potential barrier is formed for multiple carriers. At the same time, the electrode can effectively absorb minority carriers from the semiconductor layer.

The invention is described in detail by the accompanying drawings as follows.

3 shows an example of a semiconductor device electrode structure according to the present invention. The P ⁻ semiconductor layer 20 has a P-type impurity or boron concentration of 10 ¹⁵ / cm 3 and is arranged on the P ⁺ region 21 and the N ⁺ region 22 side by side. The P ⁺ region 21 contains P-type impurities or boron gallium sulfide having a surface impurity concentration of about 5 × 10 ¹⁸ / cm 3, and the N ⁺ region 22 has a concentration of 5 × 10 ¹⁹ / cm 3. A conductive layer 23 containing N-type impurities, phosphorus or arsenic, and made of a metal such as chromium, nickel, molybdenum, aluminum, or the like is formed on the P ⁺ N ⁺ pattern region 24.

Due to the above structure, the P ⁺ region 21 plays a role in moving the majority carriers and holes from the conductive layer 23 to the semiconductor layer 20 or in the opposite direction (the same as the conventional one). The N ⁺ region 22 between the P ⁺ regions on both sides plays a role in moving minority carriers from the semiconductor layer 20 to the conductive layer 23.

The national structure will be described in detail in terms of energy levels in FIG.

As in the conventional case, the majority carriers or holes can pass through the valence bonds through the conductive layer 23 -P ⁺ region 21 semiconductor layer 20 or vice versa.

On the other hand, the minority carriers or electrons contained in the semiconductor layer 20 are present on the conduction band of the P ⁻ region, which is also the same as the conventional case. The conduction band of the P ⁺ region 21 has a higher energy level than the P ⁻ region and a potential barrier ø between the P ⁺ region and the P ⁻ region. However, according to this invention, the N ⁺ region 22 is formed to be adjacent to the P ⁺ region with the conduction band is P ^- will have a lower energy level than the conduction band of the region 20, as a result, P ^- region 20 Electrons on the conduction band of may move to the low conduction bandbell (dotted line) of the N ⁺ region 22 to reach the conductive layer 23. In other words, the minority carriers and the majority carriers respectively move through the course given to them, so the voltage drop is greatly reduced to prevent unnecessary loss, which is inevitable in the conventional electrode structure due to the above structure. It works smoothly.

In addition, the electrode structure of the present invention allows the semiconductor device to have an electrode structure that satisfactorily operates at a sufficiently high speed, thereby almost eliminating the accumulation of minority carriers, which has caused a serious problem in the conventional device, and the P ⁺ -N ⁺ mosaic pattern. It is to be noted that since only the passage for each carrier is required, no special accuracy is required to form the mosaic pattern 24. Thus, there is no need for correct mask alignment, and even minor defects of the mosaic pattern can be tolerated.

5 (a) to 5 (d) show various embodiments of the mosaic pattern 24. In this embodiment, the P ⁺ region and the N ⁺ region may be interchanged. The area ratio of the P ⁺ region to the N ⁺ region should be determined to achieve smooth conduction of the multiple carriers. For example, the variation range of the following formula is preferable.

When determining the above area range, the impurity concentration and depth of each layer should be considered together.

6, which shows another embodiment of the present invention, differs from FIG. 3 in that the minority carrier passages from the P ^- semiconductor layer 20 to the conductive layer 23 have a schottky barrier region 27. It is formed using).

In this structure, the P ⁺ region 21 is formed to be dispersed on the P ⁻ semiconductor layer 20 in order to create a plurality of carrier passages between the semiconductor layer 20 and the conductive layer 23.

A metal layer as an electrode 23 is then formed over the P ⁺ region 21 and the P ⁻ portion 28 where the P ⁺ region is not formed using chromium, nickel, molybdenum and aluminum, and consequently the P ⁺ region 21. This unformed P ⁻ portion 28 is in direct contact with the metal conductive layer 23 via a Schottky barrier 27 formed between it and the conductive layer 23.

With the above structure, the minority carrier passage is made by the Schottky barrier region 27, while the majority carrier passage between the semiconductor layer 20 and the conductive layer 23 has the same impurities as the semiconductor layer 20. It is formed by the P ⁺ region 21 applied at a high concentration. This fact can be understood in more detail from the energy level diagram (Fig. 7) through the structure shown in Fig. 6. The majority carriers or holes pass through valence bonds that have no potential barrier as described with respect to the first embodiment of this invention. On the other hand, electrons on the conductive band of the semiconductor layer 20 are moved to the conductive layer 23 via the Schottky barrier region 27 which is slightly lower in energy level than the conductive band of the semiconductor region 20.

In the mosaic pattern drawn by the various P ⁺ regions 21 and the Schottky barrier region 27 on the semiconductor region 20, the patterns already described in FIGS. 5A to 5D can be used. The mosaic pattern 24a can be made by replacing the N ⁺ region in FIG. 5 with the Schottky barrier region 27.

As already described with respect to FIG. 3, the above-described electrode structure makes the movement of both the majority carrier and the minority carrier extremely smooth, the voltage drop is greatly improved to reduce the loss, and the accumulation of minority carriers is extremely small. It is possible to make a semiconductor device with improved high speed operation.

Moreover, the Schottky barrier region used in such an electrode structure is used only to make a passage of minority carriers, and does not need to have a large reverse blocking voltage, so that it can be easily made without any special forming method.

The electrode structure mentioned so far is formed by the following steps.

Assuming that has to make the impurity concentration of 10 ¹⁹ / ㎤ the first step and the P ⁺ diffusion region having a depth of about 1 micron P ^{- -} is a semiconductor layer to create an electrode structure conductivity type P on the surface of the semiconductor region P ^- to diffuse-type impurity, or boron, or gallium. The second step is to diffuse either N-type impurities, or phosphorus or arsenic, to make an N ⁺ region with an impurity concentration of 10 ²⁰ / cm 3 and a depth deeper than the P ⁺ region, for example 1.2 microns, and the third stage. Is the coating of aluminum-like metal over the entire surface of the P ⁺ -N ⁺ mosaic pattern.

In addition to the above method, the same result can be obtained as follows.

First, deeper than N ⁺ layers of N-type impurities or phosphorous or arsenic, such as 1.5 microns, to have a concentration of 5x10 ¹⁸ / cm 3 and a depth of about 1 micron by means of the Vapor Phase epitaxy. Diffuse either P-type impurities or boron in the already formed N ⁺ layer to create a P ⁺ region with a depth of.

After that, metal is coated over the entire surface where the P ⁺ -N ⁺ mosaic pattern is formed.

The third method of making the electrode of this invention is as follows.

Diffusion of either P-type impurity or boron over the P ^- semiconductor region to produce an impurity concentration of 5 x 10 ¹⁹ / cm 3 and a P ⁺ region of about 1 micron depth, N of 10 ¹⁹ / cm 3 and a concentration of 0.5 microns deep ^In order to form the ⁺ region outside the P ⁺ region that has already been formed, N-type impurities, phosphorus or arsenic are diffused or ion implanted into the entire surface including the P ⁺ region, and ohmic contact on the surface is performed. The metal layer is coated to form a. N-type impurity in this case, the P ⁺ region in the diffusion or implantation, but P ⁺ region because of the impurity concentration is formed high enough in this N-type impurity density does not matter.

The fourth method of making the electrode of this invention is as follows.

To diffuse either P-type impurities or boron on the surface of the P ⁻ region to form a P ⁺ region with an impurity concentration of 5 × 10 ¹⁹ / cm 3 and a depth of about 1 micron and to form a negative contact in the P ⁺ region And a layer of metal or nickel is formed to form a Schottky contact on the P ⁻ surface where the P ⁺ region is not formed.

The application of this invention to various semiconductor devices will now be described.

8 shows a cross-sectional view of a PN assembly rectifier diode to which the present invention is applied. The diode indicated by numeral 31 in FIG. 8 is composed of an N-type semiconductor substrate 33, an r-semiconductor layer 34, a mosaic pattern layer 38, and nickel electrodes 32, 39. The type semiconductor substrate 33 has an antimony concentration of 5 x 10 ¹⁸ / cm 3 (specific resistance 0.01 Ωcm) and a thickness of about 300 microns, and one surface thereof is in contact with the nickel electrode 32, and the P-semiconductor layer 34 is It is formed on the opposite side of the nickel electrode of the semiconductor substrate 33 by a vapor deposition process in the vapor phase, and has a boron concentration of 5 × 10 ¹⁵ / cm 3 and a thickness of about 10 microns, and the mosaic pattern 38 is formed of a P ^- semiconductor layer ( 34) is formed on the other side of the N-type semiconductor substrate (33) P ⁺ region 36 and region it consists of a (37) P ⁺ region 36 has a surface boron concentration is 5 × 10 ¹⁸ and micron depth 1 The N ⁺ region 37 has a surface concentration of 5 × 10 ²⁰ / cm 3 and a thickness of 1 micron, and is in contact with the Nickel National 39.

9 and 10 show forward current density characteristics, forward current density versus reverse recovery time constant characteristics of the diode in the forward voltage described above. These properties were measured at a temperature of 25 ° C, where line segment b is the diode of FIG. 8 except that the mosaic pattern layer 38 is replaced with a P ⁺ layer having a boron density of 5x10 ¹⁸ / cm 3 and a depth of 1 micron. The characteristics of the conventional diode having the same structure as (31) are shown. Comparing the characteristics indicated by the lines a and b, it can be seen that the forward voltage drop (VF) at the forward current density of 1 cA / cm 2 is about 0.63 volts for the diode according to the present invention, while about 0.78 volts for the conventional diode. When the current density is 100 A / cm 2, the forward voltage drop of the diode according to the present invention is 0.71 volts and the conventional diode is 0.83 volts. As is apparent from this characteristic difference, the diode 31 of FIG. Compared with diodes, the forward voltage drop is significantly lower for constant current density, resulting in a significant benefit of reduced losses. Also, as can be seen from the diode characteristics indicated by the line segments a and b of FIG. 10, the reverse recovery time constant tr of the conventional diode is about 290 nS (nanosecond) at a forward current density of 10 A / cm 2. The tr of the diode is 4.5nS and 95nS and 3.5nS at the current density of 100A / cm 2, respectively.

From the above results, it becomes clear that the reverse recovery time constant by this invention is much smaller than that of conventional diodes, and it is concluded from this fact that the storage charge is also very small, which is the diode of this invention. This means that it is possible to meet much higher speed operation requirements than conventional diodes.

Figure 11 shows an application of this invention to a p-i-N structure true diode.

Unlike the case of FIG. 8, the N ⁻ semiconductor layer 40 is formed between the P semiconductor layer 34 and the N ⁺ semiconductor layer 33. The N ⁻ semiconductor layer 46 has a high specific resistance in the reverse direction. In order to improve the reverse voltage, the same effects and benefits as in the case of FIG. 8 can be obtained. In FIG. 11, the N ⁺ region 37 can be replaced with the Schottky barrier region shown in FIG.

12 is a cross-sectional view of a PNPN type thyristor to which the present invention is applied.

PNPN type thyristors are three-port type semiconductor devices, and are widely used for electronic control purposes requiring minimizing losses and improving switching speed. In FIG. 12, the thyristor 45 includes an N ⁻ semiconductor layer 47, a P type semiconductor layer 48, an N ⁺ semiconductor region 51, and a cathode electrode 53 formed on the N ⁺ region 51, P ^−. It consists of a semiconductor region 55, a mosaic pattern layer 58, and an electrode 59 overlying a mocha pattern layer, where N ^- semiconductor layer 47 has an impurity concentration of 5 x 10 ¹⁴ / cm 3 and a thickness Is about 50 microns, the P-type semiconductor layer 48 has an impurity concentration of 5 x 10 ¹⁸ / cm 3 and a thickness of about 10 microns, and is used as a gate region (gate electrode (gate eleetrode) is P-type). Formed on the semiconductor layer), the N ⁺ semiconductor region 51 has a surface impurity concentration of 2 x 10 ¹ ₆ / cm 3 and a length of about 5 microns and is used as a cathode region, and a P ^- semiconductor region. 55 has an impurity concentration of 4x10 ¹⁶ / cm 3 and a thickness of about 5 microns and is used as an anode region, and the mosaic pattern layer 58 is about It is composed of several P ⁺ regions 56 and N ⁺ regions 57 having impurity concentrations of 10 / cm 3 and 5 × 10 ¹⁹ / cm 3, respectively, as a thickness of 2 microns.

Comparing and reviewing the conventional thyristor and the conventional thyristor having the above structure, the result shown in Table 1 is obtained. At this time, the conventional diester has the same structure as the diester 45 of FIG. 12 except that the mosaic pattern layer 58 is replaced with the P ⁺ layer.

TABLE 1

(Note) 1. The measured value about this invention compared with the thing of the conventional measured value of the thyristors.

2. Measured at current density of 100A / ㎠.

As can be seen from Table 1, it is apparent that the thyristor to which the present invention is applied is greatly improved in both loss prevention and fast switching operation.

13 shows a case where the present invention is applied to an electrostatic induction thyristor.

This is a field controlled thyristor with a number of good properties, for example gate turn off, faster switching than conventional ones, small forward voltage drop, large di / Not only does it have dt and dv / dt capability, it can also operate satisfactorily under high temperature conditions. The thyristor 61 of FIG. 13 has an N ⁺ semiconductor region 63 formed on one surface of the N ⁻ semiconductor layer 62 having an impurity concentration of 5 × 10 ¹⁴ / cm 3 and a thickness of about 60 microns and N ^+. The semiconductor region 63 has a surface impurity concentration of 2 × 10 ¹⁹ / cm 3 and a thickness of 2 microns, and is used as a cathode region formed of the negative electrode 64. In addition, the thyristor 61 is composed of a P ⁺ semiconductor region 66, a P ⁻ semiconductor layer 69, a mosaic pattern layer 72, and an anode electrode 73 formed on an upper surface of the mosaic pattern layer.

The P ⁺ semiconductor region 66 is formed as a gate region on the surface of the N ⁻ layer 62 around the N ⁺ region 63 and has an impurity concentration of 5 × 10 ¹⁸ / cm 3 and a depth of 10 microns thereon. The electrode 67 is formed. P ^- semiconductor layer is 4x1. The impurity concentration of ¹⁶ / cm 3 and the thickness of about 5 microns, the mosaic pattern layer 72 has several P ⁺ regions 70 and N having impurity concentrations of 10 ¹⁹ / cm 3 and 5x10 ¹⁹ / cm 3, respectively. ^It consists of a ⁺ region 71 and is 2 microns thick.

Comparing the conventional thyristor 61 with the above structure, the following data is obtained. The conditions under which such a comparison was made are as shown in FIG. 12, and the current density is 100 A / cm < 2 >

TABLE 2

In the above table, it can be easily seen that the electrostatically-induced thyristors using the present invention have been greatly improved in achieving the loss minimizing high speed switch operation.

The mosaic pattern layer used in the various embodiments of the present invention mentioned above is the same as that shown in FIG. Of course, other types of mosaic pattern layers may be used in this embodiment. For example, as shown in FIG. 6, a mosaic pattern layer consisting of a P ⁺ region and a Schottky barrier region can be used. In the description of the embodiment shown in FIG. 3, the conductive layer 23 is made of metal, but may be replaced with a semiconductor layer or a P ⁺ layer doped at a high concentration. In this case, the P ⁺ layer and the N ⁺ region 22 as the conductive layer 23 should be doped at a high concentration, preferably at an impurity concentration of 5 × 10 ¹⁹ / cm 3 or more, and the concentration should be equal to the P ⁺ layer 23. It is necessary to provide electrical conduction by the tunneling effect between the N ⁺ regions 22, and it is also possible to make the conductive layer 23 using a painfully doped N ⁺ semiconductor layer. Do. Fig. 14 is a cross sectional view of a PN junction diode in which the conductive layer is modified in this way, wherein the PN junction diode is an N ⁺ semiconductor layer 76 and a metal electrode 77 formed on one surface of the N ⁺ semiconductor layer. P ^- semiconductor layer 78, mosaic pattern layer 81 and polysilicon layer 82, N ⁺ semiconductor layer 76 has an impurity concentration of 5 × 10 ¹⁸ / cm 3 and a thickness of about 300 microns, The P ⁻ semiconductor layer 78 has an impurity concentration of 5 × 10 ¹⁵ / cm 3 and a thickness of about 10 microns, and the mosaic pattern layer 81 is composed of several P ⁺ regions 79 and N ⁺ regions 80. The P ⁺ region 79 has an impurity concentration of 10 ¹⁹ / cm 3 and a depth of 1 micron, the N ⁺ layer has an impurity concentration of 2 x 10 ²⁰ / cm 3 and a depth of 0.5 micron, respectively. 3 × 10 ²⁰ / cm 3 and about 2 microns, respectively.

In this structure, minority carriers from the P ⁻ region 78, in this case electrons, reach the silicon layer 82 through the N ⁺ region 80, while the majority carriers from the P ⁺ region 78 are formed. Holes in this case reach the silicon layer 82 through the P ⁺ region 79. Therefore, the loss of the diode 75 is smaller than that of the conventional diode, and the storage charge and recovery time constant are also smaller, so that high speed operation can be obtained.

It should be noted that in FIG. 14 a metal layer 83, such as an aluminum layer, may be added to the P ⁺ polysilicon layer if necessary.

In the embodiments shown in FIGS. 3 and 4, the N ⁺ region or the Schottky barrier region is used as a means for passing minority carriers or electrons, instead it is used as a passage for the majority carriers or holes while constructing a mosaic pattern. The same effect can be obtained by separately forming a region having a lower conduction band energy level than the P ⁺ region. In other words, by making a mosaic layer consisting of a p ⁻ region and a P ⁺ region, the same effects and advantages obtained by the various embodiments described above can be achieved. In this case, it is natural that the p ⁻ region has a lower impurity concentration than the P ⁺ region, and the P ⁻ region and the P ⁺ region are arranged in the same shape as in the other embodiments, and the area ratio of the P ⁻ region and the P ⁺ region is C. It may have a range of 5 to 50.

FIG. 15 shows a PN junction diode having such a content.

The diode 85 includes an N ⁺ semiconductor layer 86, a metal electrode 87 on the N ⁺ layer, a P ⁻ (or N ⁻ ) semiconductor layer 88, a mosaic pattern layer 91, and a p ⁺ polycrystalline silicon layer. consists of a (92), N ^- is 5 × 10 semiconductor layer 88 semiconductor layer 86 is 5 × 10 / ㎤ of the impurity concentration and may have a thickness of about 300 microns, P ^{- -} (or N) ^{It has} an impurity concentration of ¹⁴ / cm 2 and a thickness of about 15 microns, and the mosaic pattern layer is formed by contacting each other and using a plurality of P ⁺ regions 89 and P ⁻ regions 90 that are alternately arranged side by side. And p ⁺ region 89 and P ⁻ region 90 are each 10 ¹ ₆ / cm 3. An impurity concentration of 10 ¹⁷ / cm 3 and a thickness of about 1 micron and 0.8 micron, respectively, a silicon layer 92 nationwide is formed on the mosaic pattern layer 91 and doped with an impurity concentration of 3 × 10 ²⁰ / cm 3.

In this case, the silicon layer 92 serves to absorb electrons introduced into the P ⁻ region 90 from the P ⁻ or N ⁻ layer 88 through a recombinatien process. Therefore, since the single crystal silicon cannot produce the above effects, the silicon layer 92 should be a polycrystalline silicon layer, not a single crystal silicon layer, and the silicon layer 92 may be replaced with a metal layer.

It can be seen that having the structure shown in FIG. 15 can obtain the same effects and advantages as those obtained by the other embodiments, and if necessary, a metal electrode can be formed on the silicon layer 92 above.

This invention is not limited to the various embodiments described above and can be modified in various ways. For example, the P-type conductive layer or the P-type conductive region and the N-type conductive layer (or region) may be completely replaced, in which case the majority carrier changes from hole to electron or vice versa and minority carriers also change in electrons. It turns into a hole or vice versa. Further changing this invention, a highly doped semiconductor layer, such as highly doped polysilicon, may be used as the conductive layer of FIG.

In the above description, the present invention has been described with respect to diodes and thyristors, but the present invention can also be used for other semiconductor devices such as bipolar transistors and field effect transistors.

Claims (1)

The semiconductor layer, the conductive layer arrange | positioned on one surface of a semiconductor layer, the 1st area | region which is located between the said semiconductor layer and a conductive layer, and becomes a main path which sends a minority carrier from a semiconductor layer to a conductive layer, and a semiconductor layer and a conductive An electrode structure of a semiconductor device having a second region or the like serving as a main passage for carrying a plurality of carriers between layers, wherein the first region and the second region are alternately formed on the semiconductor layer adjacent to each other with respect to the current passage.

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