KR830000625B1 - Time data processing device - Google Patents

Abstract

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Description

Time data processing device

1A and 1B are block diagrams showing an embodiment of the present invention.

FIG. 2 is a concrete example block diagram of the oragate group shown in FIG. 1. FIG.

3 is a diagram showing a storage area of a RAM in the clock memory of the first city.

4 is a block diagram showing the configuration of the clock circuit of the first city.

5 is a specific block diagram of the latch circuit of FIG.

6A, 6B, and 6C are type charts for explaining the operation when the clock memory is accessed by the CPU.

FIG. 7 is a flowchart illustrating the operation when the CPU receives the aforementioned clock memory and data.

8 is a time chart illustrating the operation of the circuit shown in FIG. 1 in the case of a power failure.

FIG. 9 is a flowchart for explaining the operation when processed by various data in the memory of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock data processing apparatus having a clock circuit. Conventionally, a calculator apparatus having a clock circuit such as a clock electronic desk calculator has been put into practical use.

However, since the clock circuit and the CPU (central processing unit) operate independently of each other, it is very difficult to read out the time data in the clock circuit to the CPU and perform various processing by the time data.

Therefore, in the conventional apparatus, the clock mode and the calculator mode are used by switching, which is simply a combination of clock circuits.

Therefore, various processing using time data, such as changing the operation type according to time, and complicated processing such as pinching data by time zone, could not be performed.

In addition, if the predetermined time is set, and the clock circuit has the function of detecting the time data, that is, coinciding with the current time, and performing a predetermined operation at the set time, the CPU periodically executes the clock circuit (for example, every second). Access is performed to perform the above-described coincidence detection operation.

In this case, the shorter the CPU access time and the coincidence detection time, the less the burden on the CPU.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described situation, and an object thereof is to provide a time data processing apparatus for facilitating various operations using the time data and the time operation in the clock circuit.

In order to achieve the above object, the present invention forms a clock memory between the clock circuit and the central processing unit, and the tactical clock circuit reads the data in the aforementioned clock memory at regular time intervals and updates the time data. The updated data is written back into the aforementioned clock memory, and the central processing unit causes the aforementioned clock circuit to access the aforementioned clock memory when it is necessary to access the aforementioned clock memory. A time data processing apparatus is provided so that the above-described clock memory can be freely accessed and various calculation processing based on time data can be performed.

The present invention compares a set time and a current time periodically in a clock circuit, sets a flag in the above-described clock memory when a match is detected, and the above-described CPU accesses the clock when accessing the clock memory. Since only the contents are determined and processed, the CPU access time for the aforementioned clock memory is reduced to a minimum, and even when multiple clocks are set in the aforementioned clock memory, matching with the current time is independent of the CPU. This can be done in the clock circuit, making the CPU burden extremely light.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to the drawings by way of example of an electronic cash register.

1 is an overall system configuration diagram of an electronic cash register to which the present invention is applied. The CPU (central processing unit) 1 is connected to the memory circuit 2 and the clock memory circuit 3 by the data bus DB, the row address bus RB, and the column address bus CB, respectively. and a clock circuit for a memory 3 is performed within the chips sent by the CPU1 table (chip Enable) signals CE1 and CE2 by the chip specify the yirueojim and at the same time the read / seoip signal R / W read out as the _first, or standing position affection.

The CRU1 described above is connected to the I / O port 4 by opening the data bus DB and the address bus CB. This I / O port 4 is provided with an operating signal J at CPU1.

The printing unit 5 and the display unit 6, the key input unit 7, and the alarm holding speaker 8 are connected to the above-mentioned I / O port 4, respectively.

The print section 5 sends a print position signal T of the print drum to the I / O port 4 by using a line printer, and the print position buffer T and the buffer for printing the I / O port 4 are printed. (Buffer) The hammer is driven by the hammer drive signal HD generated in accordance with the data in 21, and printed on the sheet of paper and chanel.

The display unit 6 performs display operation in accordance with the segment signal SG decoded from the digit signal I / O and the display buffer 22 of the I / O port 24 by the I / O port 4.

In addition, the key input unit 7 inputs the key input signal K ₁ to the input buffer 23 in the port 4 in response to the time signal KP in the I / O port 4 when the key operation is performed.

The alarm signal AL output from Table I / O Port 4 drives Speaker 8.

The collector 24 is connected to CPU1 by opening a data bus DB, and the control signal L from CPU1 is also input.

The clock memory circuit 3 has a clock memory 301. The data in the clock memory 301 is inputted to the clock circuit 9 through the gate circuit 302, and at the same time, the OR gate group 303 for writing a sign indicating the clock is displayed. Is connected to the data bus DB.

The data on the data bus DB or the data in the clock circuit 9 are again input to the clock memory 301 through the gate circuit 304.

A column address in CPU1 and a column address in clock circuit 9 are input to gate circuit 305. The row address in CPU1 and the row address in clock circuit 9 are input to the gate circuit 306.

The outputs of the gate circuits 306 and 307 are provided to the clock memory 301 via the decoder 311, and the specific address of the decoder 311 is input to the AND circuit 312.

The signals R / W ₁ and the signal CE ₂ output from the CPU ₁ are input to the gate circuit 308 by opening the AND circuit 307. R / W ₂ is again input to the gate circuit 308 by the clock circuit 9.

In addition, the clock circuit 9 performs a time-keeping operation once per second, and outputs the signal TC during posting between 15,625 msecs of the time-keeping operation period.

This posting signal TC is inputted to the above-described gate circuits 302, 304, 305, 306, and 308 with an OR circuit 309, where a row address, a column address, R / W ₁ , CE ₂ , and a data bus DB at CPU1. Is shorted in the clock memory 301, and the clock memory 301 is connected to the clock circuit 9. As shown in FIG.

Again, the clock signal TC outputted by opening the above-described OR circuit 309 is also given to the AND circuit 312. The output of the AND circuit 312 is input to the above-described OR gate group 303, and when the output of the AND circuit 312 is "1", it outputs the publishing code [1111] to the data bus DB of 4 bits of parallel.

A circuit example of this OR gate group 303 is shown in FIG. Parallel 4-bit data output from the gate circuit 302 is input to the OR circuits 313, 314, 315, and 316, respectively.

On the other hand, the output of the AND circuit 312 is commonly input to the OR circuits 313, 314, 315, and 316.

The outputs of the above-described OR circuits 313 to 316 are sent to the data bus DB as parallel 4-bit data.

That is, the CPU 1 turns on the end circuit 312 as a specific address in order to know whether or not the clock circuit 9 described above is being clocked.

If the RC signal 309 is input to the other end of the AND circuit 312, and the time signal RC is input, and the signal RC is "1" during the addressing mentioned above, the output of the AND circuit 312 becomes "1", and the OR gate group A clock sign [1111] is written to 303, and is read into CPU1 by opening the data bus DB. When the CPU 1 detects the clock code 1111, the CPU 1 does not access the clock memory 301 described above.

In addition, the power supply unit 10 shown in FIG. 1 uses an AC power source 11. The AC power source 11 is supplied to the power transformer 13 through a power switch 12.

The secondary winding output voltage of the power transformer 13 is rectified by the full-wave rectifier circuit 14 and smoothed by the smoothing capacitor CA and input to the DC-DC converter 15.

In this case, the smoothing capacitor CA described above is grounded at the positive potential side. The above-described DC-DC converter 15 converts an input voltage into various voltages and outputs the voltage. The output voltage is supplied to the circuit 100 other than the memory circuit 2, the clock memory circuit 3, and the clock circuit 9.

In addition, a series circuit of the diode 16 and the capacitor CB of the illustrated polarity is connected between one end of the secondary winding of the power supply transformer 13 and the ground.

In this case, the capacitors CA and CB are set in a relationship of CA >> CB.

The voltage generated at the junction A between the diode 16 and the capacitor CB is supplied to the OR circuit 309 through the inverter 310 and input to one of the AND circuits 19 through the inverter 17.18.

On the other side of the AND circuit 19, CE ₁ is inputted from the CPU ₁ , and the output of the AND circuit 19 becomes the memory circuit twice chip enable signal.

The power supply 20 supplies power to the circuit 200 consisting of the memory circuit 2, the clock memory circuit 3, the clock circuit 9, even when the power supply is turned off and in the case of a power failure.

3 shows a storage area of the clock memory 301, which is composed of RAM.

In other words, the RAM, 4 rows and 16 columns are configured, and the current date and time data of the year, month, day, hour, minute, and second are written in the 11 rows to 0 columns in the 0 row.

1 haengjul has 13 columns in column 2 the type of collection (收集) be the time data TR3~TR1, collected hulraek TRF 0 column line, and 2 is 13 10-2 haengjul column 3 type to be checked time data of the RE ₃ ~RE ₁ , 0 yeoljul checked hulraek REF haengjul and 3, the 13 columns 10-2 alarm hulraek ALF to the third alarm data AL ₃ ~AL _1, 0 immersed in China respectively seoip.

The collection flag TRF described above indicates whether the collection time data TR _{1 to} TR _{3 correspond} to the current time or not, and when the collection time data TR _{1 to} TR _{3 correspond} to the current time using three bits in column 0 Sets the "1" signal to the corresponding bit.

The same applies to the check block REF and the alarm block ALF. If the check time data RE _{1 to} RE ₂ alarm time data AL _{1 to} AL ₃ coincide with the current time, use the 3 bits in the 0 column. Set the "1" signal.

4 is a circuit diagram showing the clock circuit 9 in detail. In the drawing, 901 is a pulse generating circuit for generating a reference pulse signal of, for example, 32 KHz, and its oscillation output is sent to the dividing counter 902 and divided.

This dividing counter 902 consists of 15 bits, and sequentially divides the input 32KHz signal and finally divides the signal up to 1Hz.

In the above-described frequency dividing counter 902, the 8KHz and 4KHz bit outputs are divided into the AND circuit 903, and the 2KHz and 256Hz bit outputs are input to the AND circuit 904, and the 128Hz and 32Hz bit outputs are input to the AND circuit 905, and 16HZ-1Hz. The bit output of is input to the zero detection circuit 907. The zero detection circuit 907 detects a state in which the 32-Hz to 1-Hz all-bit output of the frequency division counter 902 has become zero, and outputs a "1" signal. The detection output is applied to the end circuits 903 to 905 as a gate control signal. At the same time, the clock signal is applied to the clock memory circuit 301 as the clock signal TC.

The output of the AND circuit 903 is applied to the bit decoder 908, the output of the AND circuit 904 is applied to the digit decoder 909, and the output of the AND circuit 905 is applied to the word decoder 910. The outputs B _{0 to} B ₃ and D _{o to} D ₁₅ W _{0 to} W ₃ corresponding to the bit decoder 908, the digit decoder 209, and the word decoder 910 described above are input to the time control circuit 911. The output of the AND circuit 904 is a column address, the output of the AND circuit 905 is a row address, and the 128 Hz bit output of the frequency divider circuit 902 is input to the clock memory circuit 3 as R / W ₂ .

Thus, when the clock signal TC "1" is output from the zero detection circuit 907, the read data from the clock memory 301 is sent to the change circuit 912 which converts parallel data into serial data by opening the gate circuit 302.

The above-described output of the conversion circuit 912 is applied to the four-digit shift register 915a via the gate circuit 914 which is applied to the coincidence circuit 913 and controlled by the output of the timing control circuit 911.

The output of the shift register 915a is sent to the coincidence circuit 913 and input to the one-digit shift register 915b. In the shift register 915b, each bit output is sent to the timing control circuit 911, and the final bit output is input to the input terminal a of the half adder 916.

In addition, the +1 signal is inputted to the input terminal b of the half adder 916 by the OR circuit 917 through the timing control circuit 911.

The carry output of the half adder 916 is applied to its input terminal b with the one-bit delay circuit 918 and the OR circuit 917 opened.

The addition output of the half adder 916 is input to the shift register 915c of one digit (4 bits).

Each bit output is sent to the timing control circuit 911, and the final bit output is returned to the shift register 915a by opening the gate circuit 914.

Each of the above-described shift registers 915a to 915c constitutes a time register 915, and the shift operation is controlled in accordance with the timing pulse output from the bit decoder 908 described above. The above-described coincidence circuit 913 output is input to the latch circuit 919 for coincidence output storage. The latch circuit 919 controls the operation timing according to the signal from the timing control circuit 911.

That is, the coincidence and inconsistency between the collection time data, the check time data, and the alarm time data stored in the above-described machine memory 301 and the current time are stored.

The output of the latch circuit 919 described above is sent to the conversion circuit 921 by converting serial data into parallel data through the gate circuit 920 gate-controlled by the timing control circuit 919.

The output of the shift register 915 is supplied to the conversion circuit 921 by opening the gate circuit 920.

The above-described conversion circuit 921 converts the input serial data into parallel data, sends out the gate circuit 304 to the clock memory 301, and writes the current time, the collection output TRF, the inspection hook REF, and the alarm hook ALF.

5 illustrates a circuit example of the latch circuit 919 of FIG. 4, and the detection output of the coincidence circuit 913 is input to the AND circuits 61, 62, and 63. FIG.

If the current time and the set time match, the output of the coincidence circuit 913 is "0", which is inconsistent. The case is "1".

Back-end circuit 61, 62 and 63 is input to both of the outputs of the word decoder 39, the output _{W 2, W 4, W 6} . Again, outputs D _{2 to} D ₁ of the output of the digit decoder 38 are input to the AND circuit 61, outputs D _{6 to} D ₉ are input to the AND circuit 62, and outputs D _{10 to} D ₁₃ are input to the AND circuit 63.

The outputs of the AND circuits 61, 62, and 63 described above are input to the input terminal S to the set input terminals S of the flip-flop circuits 64, 65, and 66, respectively. Reset input terminal R of the above-described respective flip-flop circuits 64, 65, 66 is input to both the output _{W 3 · D 1 · W 5} · D 1 · W 7 · D 1.

The output signals at the reset output terminals Q of the flip-flop circuits 64, 65, and 66 described above are applied to the AND circuits 67, 68, and 69, respectively.

The AND circuit 67, 68, 69, the output _{W 3 · D 0 · W 5} · D 0 · W 7 · D 0 both the input and back-end circuit 67, the output of the output of bitteu decoder 37 B ₀ the AND circuit 68 is output B ₁ is, AND circuit 69 has an output B ₂ is input.

The above-described outputs of the AND circuits 67, 68, and 69 are provided to the gate circuit 920 by opening the OR circuit 70. Next, the operation of the clock circuit 9 will be described. The battery output of 16 Hz to 1 Hz of the frequency dividing counter 902 is all “0” once per second, and the period is 32.25 m sec.

In this period, the end circuits 903, 904, and 905 are in a conductive state so that the clock signal TC output from the zero detection circuit 907 becomes " 1 " The clock signal TC described above switches the gate circuits 302, 304, 305, 306, and 308 of the clock memory circuit 3 shown in the first illustration to input and output data to and from the clock circuit 9.

The output of the end circuit 905 changes to "000", "100", "010", "110", "001", "101", "011", and "111", and each state is W ₀ , W ₁ , W ₂ …. … 8 War of the Admiral W _7.

8 Weird War period of the W ₀ ~W ₇ is a 3225m sec of post operation period.

First, in the word of W ₀ , since the R / W ₂ output of the 128 Hz batt is "0" and the RA output of the end circuit 905 is "00", the row 0 line of the clock memory 301 is read out sequentially, and the change circuit 912 The gate circuit 914 is opened and input to the time register 915.

At this time, the read time is +1 second to the half adder 916. In the word of W ₁ , R / W ₂ = 1 and RA = "00", and the gate circuit 920 and the conversion circuit 921 are opened and written to line 0 of the memory 301 for clock.

At this time, the hour and minute data is input to the shift register 915a for four digits by opening the gate circuit 914, and the output of the shift register 915a is again input to the shift register 915a by opening the gate circuit 914. I'm watching the cycle.

Next, since the W ₂ word is R / W ₂ = ORA = 10, the data of one line of the clock memory 301 is read out.

At this time, the acquisition time data to be read out is input to one of the coincidence circuit 913 through the change circuit 912. The current time is input to the other coincidence circuit 913, and the coincidence detection between the current time and the collection time is performed.

The detection result is written to the latch circuit 919 and output to the digit of the word D ₀ of W ₃ , and the gate circuit 920 and the conversion circuit 921 are opened and written as collection collection REF in column 0 of the first row of the clock memory 301. .

Hereinafter, coincidence detection of the check time data and the alarm time data is performed.

The clock circuit 9 finishes the posting operation as described above, and the posting signal TC in the zero detection circuit 907 becomes " 0 ". When the signal TC during posting becomes " 0 ", the gate circuits 302, 304, 305, 306 and 308 are switched by this signal, and the clock memory 301 performs data input / output with the CPU1.

Next, the operation when the CPU1 accesses the clock memory 301 will be described.

As shown in Fig. 6 (a), the clock circuit 9 operates once per second, and its operation period is 32.25 m sec.

This period is shown in Fig. 6 (b) in which the gyrosignal signal TC outputs the "1" signal in the clock circuit 9. In this period, the clock memory 301 is accessed from the CPU1 because the clock circuit 9 uses the clock memory 301. In FIG. 6C, where CPS1 cannot transfer the data with the clock memory 301, the presence or absence of the time code is detected first as in the processing A of FIG. 7.

That is, CPU1 sends out specific address values specifying the AND circuit 312 by opening the row address bus RB and the column address bus CB.

At this time, if the clock signal TC in the other end of the AND circuit 312 is described above, the output of the AND circuit 312 becomes "1", and the clock sign "1111" is written to the OR gate group 303, and is sent to the data bus DB.

CPU1 reads data on this data bus DB and detects whether it is a sign during timekeeping. If there is no sign in time, the above-described process a is repeated.

If there is a sign in time, the process proceeds to the next process b. As shown in process a, the operation for detecting the presence or absence of the sign in time is performed. Starting from this process c, the CPU1 accesses the clock memory 301. For example, the CPU 1 reads the check block REF in the clock memory 301 and inputs it to the register a (not shown) in the CPU1. In this way, CPU1 detects the presence or absence of the code during posting and confirms that the code is missing during posting, and then reads or writes data to the clock memory.

Next, the circuit operation at the time of power failure will be described. At the time of power switch 12 input as shown in the first illustration, the commercial AC power supply 11 is rectified to the rectifier circuit 14 and smoothed by the capacitor CA and input to the DC-DC converter 15.

The DC-DC converter 15 changes the input voltage into various voltages and supplies them to the circuit 100. When power is generated in the secondary winding of the power supply transformer 13 described above, this voltage is rectified to the diode 16 and stored in the capacitor CB.

For this reason, the predetermined electric potential Va similar to FIG. 8 (b) arises at point a, and this voltage is applied to inverter 310 and inverter 17. As shown in FIG.

For this reason, while the power is on, the outputs of the inverters 310 and 17 are "0", and the output of the inverter 18 is "1".

Therefore, there is no output according to the inverter 310 in the OR circuit 309, and in the AND circuit 19, the chip in the CPU ₁ sends the enable CE ₁ to the memory circuit 2.

In this state, since the capacity of the capacitor CB is set very small in the case of power failure as shown in FIG. 8, the charging of the capacitor CB discharges immediately.

For this reason, as shown in FIG. 8 (b), the output of the approach inverter 310 and the inverter 17 is “1” as rapidly as in FIG. do.

For this reason, the output of the inverter 310 becomes "1". Therefore, the output " 1 " of the inverter 310 is provided to the gate circuits 302, 304, 305, 306, and 308 by opening the OR circuit 309, and switches the respective gates to the data transfer state with the clock circuit 9.

In addition, the above-described output of the inverter 310 is provided to the AND circuit 312 by opening the OR circuit 309, and when one of the AND circuits 312 is designated by the address, it is outputted to the OR gate group 303 to output the sign being posted. For this reason, CPU1's access to clock memory 301 is prohibited.

On the other hand, the output of inverter 17 is inverted by inverter 18 to become " 0 " to close the AND circuit 19.

For this reason, the chip output from the CPU ₁ cuts off the enable signal CE ₁ , thereby preventing access to the memory circuit 2.

As described above, the malfunction of the CPU 1 caused by the power supply voltage drop during power failure is prevented from destroying the normal memory data of the clock memory 301 and the memory circuit 2.

When stopped or when the power supply is turned off, a voltage is supplied from the power supply 20 to the memory circuit 2, the clock memory circuit 3, and the clock circuit 9 so as to retain the stored data, and at the same time, the clock circuit 9 operates the clock.

In addition, the smoothing capacitor CA in the power supply unit 10 is set to a sufficiently large capacity, and holds the input voltage to the DC-DC converter 15 for a predetermined period even after a power failure.

Therefore, the output voltage of the DC-DC converter 15 is held at a predetermined value as shown in FIG.

While the output voltage of the DC-DC converter 15 is held at a predetermined value, the CPS1 performs an electrostatic process.

Thus, when the AC power source 11 recovers after the above-described power failure recovery, a predetermined voltage is output from the DC-DC converter 15 as shown in FIG.

Next, when the CPU1 performs various processes using the current time data CLK, the collection hook TRF, and the check hook REF alarm hook ALF in the clock memory 301, the operation of FIG. _As shown in ₁₁ , the contents of the input buffer 23 in the I / O port 4 are read into the register ACC formed in the CPU.

Then, as in step S ₁₂ , it is determined whether or not data is _held in the above-described register ACC ₁ , that is, whether there is key input data. When the key input operation is performed in the key input unit 7, key input data is first read into the input buffer 23 in the I / O port 4, so that the presence or absence of the key input data can be determined by examining the input buffer 23 and the stored contents. There is a number.

If it is determined in step S ₁₂ that the key input data is present, the process advances to step S ₁₃ to execute processing for key input.

And when ends the processing returns to step S ₁₁ to cause the data again, the dock to the register ACC ₁ in the CPU1 in the input buffer 23 for. If it is determined in step S ₁₂ that the key input data is "none", the process advances to step S ₁₄ , and after detecting that there is a sign presenting, the process advances to step S ₁₅ . After detecting that the missing step of a post code in S ₁₅ reads out current time data CLK in the step S ₁₆ for entering the memory clock 301 to be set to the ACC register ₂ in the predetermined area in the above-described CPU1.

Next, the process advances to step S ₁₇ , and it is determined whether or not the contents of the registers ACC ₂ and ACC ₃ described in the CPU1 described above are the same.

The contents of this register ACC ₃ are initially "0", but the present time data CLK is written in step S ₁₈ or S ₂₁ or S ₂₄ described later.

Thus the register ACC ₃ content above is because it is the first "0" to the decision step S ₁₇ is advanced to the first step S ₁₈ is NO. In this step S ₁₁ , it is determined whether the collection block TRF stored in the clock memory 301 is set.

Current time data CLK is collected time TR ₁ ~TR If coincides, or which side of the _three "1" is set in bitteu of any depth in the vertical hulraek TRF so collected hulraek is a TRF "0" is not in the step S ₁₈ NO In step S ₁₉ , at step S ₁₉ , " 1 " is written to the CPU register F1 (not shown) F1 of CPU1, and then step S ₂₀ is entered, and the present time data is stored in the clock memory 301 as described above. Read the CLK and write it to _register ACC ₃ in CPU1.

And if the end of the step S ₂₀ to advance to the next step S _21. In the above-described step S ₁₈ resin hulraek TRF will be determined as "0" Yiwu also advance to step S _21. In step S ₂₁ there is checked stored in the clock memory 301 for hulraek REF is set, it is determined whether.

If the current time coincides with any of the inspection time data RE _{1 to} RE ₃ , since "1" is set in the bit in all of the inspection flow REF, it is determined as NO in this step S ₂₁ and advances to the step.

Step S ₂₂ in hulraek amount of CPU1 register (not shown) to "1" to F2 in seoip, then clock the memory 301 for, as described above in advance to the step S ₂₃ reads out current time data CLK to the register ACC ₃ in the CPU1 Introduce. And Exiting the step S ₂₃ to advance to the next step S _24.

In addition to the check of the above-described step S ₂₁ hulraek REF is determined to be "0" will Yiwu also advance to the step S _24. In step S _24, there is stored in the memory 301 for the alarm clock hulraek ALF are set, it is determined whether. If the current time matches any of the alarm setting time data AL _{1 to} AL ₃ , since "1" is set in the bit of any of the alarm stacks ALF, it is determined as NO in this step S ₂₄ , and the process proceeds to step S ₂₅ . Advance. The step S in the _26, hulraek register (not shown) in the CPU1 F ₃ to the "1" in seoip, then clock the memory 301 for, as described above in advance to the step S ₂₆ reads out current time data CLK register ACC ₃ in the CPU1 Write on.

Then, the flow advances to the next step _S27 . In addition to the above-described step S ₂₄ hulraek alarm ALF is also advanced to the step S _27, if the register is equal ACC ACC ₂ and ₃ in the case where it is determined as "0", and the CPU1 to the above-described step S ₁₇ is determined. Here, the contents of the registers ACC ₂ and ACC ₃ are compared with each other at S ₁₇ , and when the results are the same, the process proceeds to step S ₂₇ without executing steps S _{18 to} S ₂₆ .

The reason is that each of the above-described hulks need to be set and hold for one second. Therefore, the current time data CLK read in the register ACC ₂ in step S ₁₆ advances for one second, and the comparison result of step S ₁₇ becomes NO. This is because the next hulk set operation, that is, steps S _{18 to} S ₂₆ are not executed until then.

The above-described step S ₂₇ determines whether or not the issue issuance full RT that stores "1" is set after issuing the receive in CPU1, i.e., issuing of a receive is made. If the sheet re-issue is not over yet goes back to step S _11.

However, if it is determined in step S ₂₇ that the receipt issuance RT RT is "1", that is, the completion of the receipt issuance is confirmed, the process proceeds to step S ₂₈ and it is determined whether or not the collection storage funnel F ₁ is set.

When the acquisition memory hulraek F ₁ is determined to be "1" in the step S ₂₆ to step S ₂₉ advance, by one data line DB from the CPU1 sends the collected data D to the collector 24. At this time, the CPU 1 transmits a control signal L to the collector 24.

At the end of a series of collecting operation will be seoip a "0" in advance, hulraek F ₁ in step S _30. The process then advances to step S ₃₁ . In addition, even if hulraek the above step S ₂₈ it is determined that F1 is 0, the advance to the step S _31.

Step S ₃₁ determines whether the hull F2 is set or not.

When the determination here hulraek F2 to "1" after a predetermined inspection process advanced to the step S _32, will be set to "0" in hulraek F2 to step S _33.

And it is advanced to step S _34. Further, when the check memory block F ₂ is compressed to "0" in step D ₃₁ described above, the process proceeds to step S ₃₄ .

In step S ₃₄ , it is determined whether the hull F3 is "0".

Alarm memory hulraek F301 is to advance to Step S ₃₅ if it is determined as "1" to send the I / O port 4 Upper cords of the alarm signal from CPU1 is set to fulfill the alarm operation.

And it sets "0" in the step S ₃₆ hulraek F _3, and the process returns to step S _11.

In addition to the above-described step S _34, even if the alarm memory hulraek F ₃ is determined to be "0", the process returns to step S _11.

The flowchart is repeated to detect various set times.

Claims (1)

A clock which is connected to the clock memory for storing time data and the clock memory described above, updates the time data read out from the clock memory described above, and then repeats the time-keeping operation written to the aforementioned clock memory at predetermined time intervals. And a central processing unit connected to the circuit and the aforementioned clock memory, the central processing unit for accessing the clock data in the aforementioned clock memory in addition to the clock clock operation described above.

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