KR830000225B1 - Pal switching control circuit - Google Patents

Abstract

In a PAL color television system for processing a color signal including burst and chrominance components alternating in phase at the image line scanning rate, identification and control circuitry for rapidly correcting an incorrect mode of line to line color demodulator switching. A bistable circuit generates timing signals for controlling line by line switching of a selected color demodulator(e. g., R-Y). An identification signal representative of an incorrect line switching mode is derived from information contained in the burst component, and serves to reset the bistable circuit such that timing signals corresponding to a correct switching mode are produced.

Description

Switch

1 is a schematic diagram of a portion of a chrominance signal processing channel of a color television receiver adapted according to the PAL signal processing standard and adapted to use the present invention.

1A to 1C are signal waveform diagrams for understanding the present invention.

2 is a partial circuit diagram of the arrangement of FIG. 1 according to the present invention.

3 to 5 are circuit diagrams of the respective parts of the FIG. 1 arrangement.

The present invention relates to a control circuit for correcting an incorrect switching mode for each line in a decoder of a PAL or SECAM type color television system. When the correct switching mode is quickly restored so that the system also includes an automatic color control (hereinafter ACC) circuit and a dyeing circuit, the visible effect of the switching operation, which may be perceived by the observer in the display image, may be allowed. To the extent it is.

In the PAL type color television system, the RY subcarrier component is 180 ° phase-changed for each line in the broadcast encoder, and in order to reproduce the RY component, it is necessary to perform switching for each line in the decoder (e.g., the receiver). have. In a PAL type color television receiver, the reference carrier signal input of the R-Y demodulator is switched for each line, and the reference carrier switch is driven by an appropriately controlled bistable (flip-flop) circuit. The information required for identifying the appropriate switching for each line is contained in the color burst component of the composite color signal whose phase is alternately and ground alternately for each line by a predetermined amount with respect to the reference phase. Additional details on this switching identification can be found in Peter S. US Patent Application No. 3,553,357 to Kant.

The desired phase relationship between the locally generated timing signal and the color burst component commonly used in PAL decoders with the PAL switch to switch the reference signal input of the RY demodulator so that proper RY demodulation is performed is desirable for various reasons. It may change without doing so. As an example, in the case of a color television receiver, this phase relationship may be changed by channel switching. In addition, the timing of the locally generated timing signal may be changed by the noise signal. In the case of a video signal recording medium such as a disk or a magnetic tape, the phase relationship may change due to a similar effect to that occurring at the channel switching of a television receiver due to discontinuities occurring in the recording material or during reproduction.

If an incorrect switching mode is produced according to one or more of the factors mentioned above, it is desirable to provide a means for quickly recovering to the correct switching mode and demodulating the appropriate R-Y components. This result is also important for television signal processing systems with automatic color control.

The ACC network of color television receivers is used to maintain the color saturation (saturation) at an average level of disturbance for a state where the signal intensity changes. Since the amplitude of the burst component is proportional to the amplitude of the received signal, it is an index of the received signal strength. Thus, for example, the ACC network will automatically increase the level of the color sandwich in response to the detected burst component of relatively small amplitude. In addition, when the amplitude of the burst component is less than or equal to a predetermined level, the chromaticity network associated with the ACC network is deactivated to generate a black and white image by deactivating the chrominance signal processing channel of the receiver. The dyeing network is activated when the switching mode is incorrect.

The operation of the PAL type ACC circuit and the sagger circuit may be affected by an incorrect switching mode. That is, improper decoding may be caused when the phase of the burst component is in a distressed or awkward state, and as long as this state continues, the ACC circuit raises the intensity of the color signal. Moreover, the color image reproduced by the operation of the ACC circuit generates a visible increase in color saturation (ie, "blooming") until the pigmentation circuit is operated. Since this effect disturbs viewing, it needs to be localized as much as possible in a PAL color television signal processing system.

The switching control device according to an embodiment of the present invention has a luminance component, a deflection synchronization component of each line frequency and a field frequency, and a chromium having a prescribed mutual timing relationship and whose phases alternate with each line. It is included in a system for processing color television signals containing nonce components and burst components. The system also includes a chrominance channel for processing the chrominance component and a plurality of demodulators for demodulating the predetermined phase of the chrominance component, the demodulator being switched for each line. For proper operation of the system, the switched demodulator needs to be switched in precise synchronization with each alternating line of the signal received by the system. The switching control device is provided with a means for supplying a timing signal of 1/2 line frequency which determines switching for each line of the switched demodulator in response to a locally generated trigger pulse occurring at the line frequency. When switching of the demodulator occurs with incorrect synchronization timing, the identification signal is extracted from the signal processed in the chrominance channel by a circuit showing a quick response compared to the line frequency. When this extracted identification signal is present, this identification signal is utilized as a boot trigger pulse input of the timing means to reset the timing means to generate a timing signal corresponding to the synchronization timing for each precise line.

In FIG. 1, signal source 10 is a first gate chrominance signal that includes a chrominance component given as an amplitude modulation of a periodic color synchronization burst component and a predetermined phase of a suppressed color subcarrier of about 4.43 MHz. Supply to amplifier 12. Typically, the burst component includes about 10 cycles of unmodulated color carriers in phase with the carrier, and is transmitted during the synchronization period accompanying the end of each line period of the image information in the transmitted television signal. The color burst information exists only during the horizontal burn scan period of about 2.5usec, which is a relatively short period with a duration of about 64 usec. Amplifier 12 generates separate chrominance and burst components in response to the locally generated complementary phaseburst gate signals? _B and? _B '. The signal? _B is shown in FIG. 1b. The burst gate pulse of duration T _B substantially coincident with the duration of the burst component is L. a. It may be in the form described in Halwood, US Pat.

The separated chrominance component from amplifier 12 is L. a. Amplified by a second gain control chrominance amplifier 14 of the type described in Halwood, US Pat. No. 3,740,462. The amplified chrominance component from this amplifier 14 is delayed by about one horizontal scan period by the delay and the PAL delay line included in the matrix unit 15. The output signal of unit 15 is supplied to the sync signal demodulators 16 and 18 which generate demodulated B-Y and R-Y color difference signals. The demodulators 16 and 18 also generate strains B-Y 'and (R-Y), respectively, of the demodulated color difference signals, and these color difference signals are synthesized in matrix 19 and generated as color difference signals G-Y. As is already known, the RY, BY and GY color chrominance signals are synthesized from the luminance signal Y from the luminance channel of the receiver and the matrix 22, and are then generated as color signals RB and G to be supplied to the image reproducing tube (not shown). .

The separated burst component from the amplifier 12 and the voltage-controlled oscillator (VCO) based on sub-carrier signal from the 26 ø _R El. a. Supplied to the input of a wideband synchronous phase detector 25 of the type described in Halwood, U.S. Patent Nos. 3,740,456 and 3740461, which detects the phase of the signal ø _R from VCO 26 and the burst component from amplifier 12. And / or generate an output signal? _D representing the frequency difference. The detected signal ø _D is supplied to the VCO 26 as a synchronous signal input through a filter network (not shown) to generate a signal representing the average level of the signal ø _D. VCO 26 also generates a subcarrier reference signal ø _Q in 90 ° phase relation with signal ø _R. The oscillation signal? _Q is supplied to the demodulator 16 for demodulation on the BY-signal phase, and the signal? _R is supplied to the demodulator 18 through the PAL switch 58 for demodulation of the RY signal. Oscillators suitable for use with VCO 26 are: a. See also U.S. Patent No. 4020500 to Halwood.

The detection burst expression signal? _D (Fig. 1a) is formed of periodic pulses that are positive and negative in intervals of one horizontal image scanning line period 1H. Typically the duration of this periodic pulse is shorter than the burstgate period T _B. Positive and negative pulses of this signal ø _D occur at half frequency of 7.8 KHz frequency or 15.6 KHz line scanning frequency, respectively. In this case, the amplitude of the pulses constituting the signal ø _D assumes a synchronous oscillation condition in the same shape.

Signal ø _D is also supplied to detector 30, including gate bias sample and hold switch 32, gate signal sample and hold switch 34 and filter 35 described in US Pat. Nos. 3,740,456 and 3740461. The level detector 40 responds to the control signal generated by the filter 35 and causes the second chrominance amplifier 14 to be in an inactive state when the ACC signal and the color signal controlling the first amplifier 12 are in a very weak or black and white signal state. Generates the control input signal of the sagger circuit 43. The color control device 45 (e.g., a potentiometer for viewer operation) is used to adjust the color saturation of the reproduction color image by adjusting the gain of the second amplifier 14.

Level detector 40 also generates a RESET signal to vary the operation of flip-flop 50 (e.g., bistable multivibrator) under the conditions described below to produce the correct output signal phase. Normally flip-flop 50 is triggered in response to the leading edge of burst gate signal ø _B from gating unit 54 which produces a complementary phase burst gate signal ø _B (FIG. 1b) and ø _B ′ at the prescan frequency. A suitable circuit configuration of the gating unit 54 is shown in FIG. The complementary phase output signals ø _F '(figure 1c) and ø _F from the flip-flop 50 are used as the synchronous timing signals of the PAL switch 58, so that the demodulator 18 receives the appropriate phase of the subcarrier reference signal ø _R to obtain the RY component. Demodulate correctly. The signals ø _F and ø _F ′ occur at half the frequency of the prescan frequency, and are usually exactly synchronized with the burst component. The output signal? _F 'from the flip-flop 50 controls the operation of the signal sampling switch 34 to be described later along with the burst gate signal? _F. A circuit configuration suitable for flip-flop 50 which generates signals? _F and? _F 'in response to the line frequency input signal supplied from the deflection circuit of the receiver is shown in FIG. The PAL switch 58 may be in the form shown in FIG.

Reference is now made to FIGS. 1 and 2. In FIG. 2, the detection burst representation signal? _D from the output of the detector 25 is low impedance series coupled to the signal sampling switch circuit 34 and the bias sampling switch circuit 32 through the isolation follower transistor 200. Switch 34 forms a signal sample and network with a filter circuit comprising a resistor 236 and a capacitor 238 that determine a first RC time constant, and switch 32 forms a resistor 232 and a capacitor 234 that determine a relatively long second time constant. A bias sample and hold network is formed together with the included filter circuit.

Signal sampling circuit 34 includes differentially configured switching transistors 222 and 224, current source transistor 226, and key follower transistor 228 as shown. The low impedance emitter output of transistor 228 is connected to first terminal T ₂₁ by a network including resistor 236 and capacitor 238. The bias sampling circuit 32 is similar to the circuit 34, and includes a switching transistors 212 and 214, a current source transistor 216, and a key follower transistor 216 in a differential configuration as shown. The emitter output of the follower transistor 218 is connected to the second terminal T ₂₂ by a network comprising a resistor 232 and a capacitor 234. A voltage smoothing network comprising a capacitor 240 and resistor 239 in series is coupled between terminals T ₂₁ and T ₂₂ to form a filter network with elements 232, 234 and 236, 238.

Typically the operation of sampling switches 32 and 34 is described in detail in the aforementioned US Pat. No. 3740456. In addition, the special operation of the switch 34 in response to the signals ø _F 'and ø _B is W. H. It is described in US Patent No. 836420 to PAL Identification Circuit, filed September 26, 1977 by Groenweg.

The bias and signal sampling circuits 32 and 34 operate complementarily in a high impedance state and an impedance state (i.e. one is blocked while the other is sampling the output of the detector 25 and the other is sampling). One side is disconnected), alternately coupling and disconnecting the output of detector 25 from the associated filter network. The bias switch 32 samples the zero DC voltage level of the detector 25 output during the period of the signal? _D without burst surface pulses (Tc in the 1a scheme), wherein the switching circuit 34 does not operate. A positive DC voltage indicating this level is generated and accumulated in the capacitor 232. For simplicity purposes this DC voltage is assumed to be substantially constant.

Typically a positive or negative pulse is generated that is representative of the magnitude of the corresponding sample pulse of the signal [Delta] _D and accumulated at capacitor 238 and then appears at terminal T ₂₁ . The base signal ø _F ′ of the transistor 222 is in a relatively negative state (ie, sufficient to deactivate the transistor 222), and the base signal ø _B of the transistor 224 is in a relatively positive state (that is, Sufficient to conduct transistor 224), the follower 228 is turned on and a pulse of signal ø _D at the base of the transistor 228 causes the capacitor to pass through the base-emitter junction of the transistor 228. Is sent to 238. A relatively positive or negative pulse voltage corresponding to the magnitude of this transmitted pulse is shown at terminal T ₂₁ .

Signal ø _F 'is relatively Jong Il time, the transistor 222 is conductive the collector current of the transistor 222 is the signal ø _D pulse Thereby the blocking transistor 228 by reducing the base drive current of the transistor 228 is It is not sent to capacitor 238 and terminal T ₂₁ . In this case, the capacitor 238 retains the charge accumulated during the immediately preceding sampling period, and the charge is reduced by the leakage current (e.g., the small base current of the follower transistor 241). The same observation can be applied to the operation of the sampling switch 32 with respect to the signals? _B and? _B '.

In this example, the circuit 34 samples the positive pulse from the detector 25 during each period T _B under accurate timing conditions. This positive pulse is sampled when the positive burst gate pulse? _B occurs during the " negative " period of the signal? _F '(Tc in Fig. 1c). (I.e., only every other pulse of the signal ø _D is sampled). The relative timing of the signals? _F 'and? _B from which this positive pulse is sampled corresponds to the normal and accurate timing state in this case.

The positive potential induced at terminal T ₂₁ with respect to terminal T ₂₂ as described above is followed by a follower transistor 241, 243 at the base input of the differential comparison transistors 242, 244 included in the level detection circuit 40. Are supplied separately). In the normal signal state, a predetermined ACC voltage and a dye control voltage are generated at the collector outputs of the PNP transistors 246 and 251, respectively. Circuit 40 also includes a divided delay network consisting of series resistors 255 and 256 coupled to the collector of transistor 251.

When the received color signal is weak, the amplitude of the detection burst expression signal? _D becomes correspondingly small, so that the voltage induced at the terminal T ₂₁ becomes small. In response to this state, the ACC voltage of the collector of the transistor 246 decreases in the direction of increasing and compensating the gain of the first chrominance amplifier 12. As the received signal becomes weaker, the collector voltage of the transistor 251 is raised to a magnitude sufficient for the conduction of the dye germination transistor 265 to generate a collector output control signal for shutting off the second chrominance amplifier 14. . Typically, the non-conducting control transistor 260 generates a collector output RESET signal for resetting the flip-flop 50 when an incorrect switching condition occurs, as described below. The transistor 260 conducts in response to the induced voltage to the connection point of the voltage divider resistors 255 and 266 used as the delay circuit so that the transistor 260 conducts after the transistor 265 conducts, thereby supplying a RESET signal.

In the case where the timing relationship between the burst gate pulse? _B and the flip-flop timing signal? _F 'causes a negative pulse of the signal? _D from the sampling switch 34 to be sampled, the presence of an incorrect PAL switching state is taken into account. This incorrect timing state originally corresponds to an incorrect timing relationship between the burst component and the flip-flop switching signal, which occurs for several reasons described above. This condition is preferably modified quickly.

This inaccurate timing state causes the filter voltage appearing at terminal T ₂₁ to exhibit a magnitude in the negative direction because circuit 34 samples a negative pulse than the positive pulse of signal? _D. At this time, the capacitor 238 is charged in response to the magnitude of the negative pulse to generate a negative voltage pulse at the terminal T ₂₁ . This voltage is hereinafter referred to as the identification voltage.

The values of resistor 236 and capacitor 238 provide sufficient noise-free function by placing high frequency noise and pseudo signals to ground, where capacitor 238 has a relatively short duration (approximately 2.5 μsec) of signal ø _D. It is chosen to respond quickly to the pulse of. In particular, the resistive capacitance time constants associated with filtration networks 236, 238, and 239, 240 allow for quick response to switching mode identification information supplied by the burst representation pulse of signal ø _D at the prescan frequency. Determine a response time short enough. This short response time generates an identification voltage of an appropriate magnitude at the terminal T ₂₁ in response to the magnitude of one negative pulse of the signal? _D. In addition, the value of capacitor 240 is each vertical, which is strongly disturbed enough to cause shading of the reproduced image as a result of the ACC action in which the voltage induced between terminals T ₂₁ and T ₂₂ responds thereto. It is selected to smooth the voltage during the retrace period.

The response time of the filter circuits 236 and 238 is shorter than the response time associated with the sacrificial operation. The latter response time includes the value of the effective collector-emitter impedance at the time of conduction of the saggered transistor 265, and the resistors 274, 275 and the viewer operating potentiometer 273 connected as shown. It is a function of the time constant determined by the value of the filter capacitor 279 of the color control circuit 270. Since the response time of this pigmentation action is long enough, it does not respond to metal or instantaneous changes in the received signal level (e.g., due to noise or rapid decrease in received color signal strength) in the correct timing state where the pigmentation circuit is normal. On the other hand, the visible effect of the pigmentation action in response to such a change may interfere with viewing.

In response to an incorrect timing state, the control voltage of the collector of the transistor 251 and the voltage of the connection point of the resistors 255 and 256 are increased by a corresponding amount by the identification pulse voltage induced at the terminal T ₂₁ . A negative RESET pulse for the reset flip-flop 50 is generated in the control transistor 260. The control signal from transistor 251 is also applied to the base input of sagger transistor 265, but second chrominance amplifier 14 is not immediately blocked due to the relatively long sagger response time.

The RESET pulse from transistor 260 alters the operation of flip-flop 50 in the sense of generating an accurate timing pulse after identification of an incorrect switching mode (? _F '). This can be done between one sampling period and the next, as will be described later in connection with the circuit embodiment of flip-flop 50 shown in FIG.

For an incorrect switching state during a predetermined signal pulping period, a negative burst representation pulse of the signal ø _D appears at the base of the transistor 228 (FIG. 2). The cross-coupled flip-flop switching transistors 410, 412 (FIG. 4) are respectively conductive and non-conductive, whereby the relative negative and positive phase collector output signals ø _F ', as shown, Create (ø _F ). A negative RESET pulse is generated by a negative identification voltage pulse during the sampling period. This RESET pulse is generated quickly and the flip-flop 50 is reset by non-conducting and conducting the flip-flop transistors 410 and 412, respectively, whereby the collector outputs ø _F 'and ø _{F are} respectively reset. ) Polarity is reversed. As a result, the relative positive level of the signal? _F 'is generated in time coinciding with the end of the associated burst gate pulse period due to the fast switching action of the flip-flop 50. This signal (ø _F ") state of the flip-flop 50, the signal (ø _F when triggered by the leading edge of the next burst gate pulse (ø _B) of the" correct timing due to a) indicate the size of the relatively negative Common to the state. At this time, a positive burst representation pulse of the signal ø _D will be present and sampled. This results in a positive identification voltage indicative of the correct timing mode so that the normal operation of flip-flop 50 remains undisturbed during the correct timing mode.

In this way, from the time constant selection of the circuit, an accurate timing state is normally reproduced in one diagonal line, so that demodulation of a suitable R-Y component is quickly recovered.

Since the magnitude of the extracted identification pulse depends on the magnitude of the sub-pulse sampled from the signal [Delta] _D , in some cases recovery of the correct timing state may require more than one sampling period (i.e., more than one scanning line). By way of example, the magnitude of the burst component separated as the internal amplifier 12 to receive the weak color signal may be below a predetermined level. Since the magnitude of the subpulse of the sampled signal ø _D , that is, the magnitude of the resulting identification pulse, will represent a correspondingly reduced magnitude, the resulting identification pulse resulting from one sampled subpulse is insufficient size. So that flip-flop 50 is not reset. More than two sampled pulses are required to generate an identification pulse of sufficient magnitude to reset flip-flop 50.

Typically, the ACC signal is used to adjust the gain of the amplifier 12 such that the separated burst component and chrominance component exhibit a predetermined magnitude when the received color signal level is within a predetermined range. In this case, the magnitude of the sampled burst representation pulse from the signal? _D produces an identification pulse sufficient to reset the flip-flop 50. A condition in which more than one sampling period is required to recover the correct timing as described above occurs when the received color signal level is below the ACC control range. The negative identification pulse generated at the terminal T ₂₁ indicates a weak state of the received signal, and the level detector 40 increases the gain of the amplifier 12 to increase the strength of the signal processed from the amplifier 12. Generates a faulty ACC signal. However, because the incorrect switching state that causes this ACC action is corrected quickly as described above, and at the same time, this ACC signal is also removed, so the effect of this ACC action (ie, "bringing of the color") is actually reproduced. It is not recognized by the observer of. The saggered circuit does not operate within a short time because its response time is relatively long.

While the invention has been described in terms of specific embodiments, various modifications are possible without departing from the scope of the invention. Examples of each component value and operating conditions mentioned above are mentioned to facilitate understanding of the present invention, but do not limit the present invention.

In the particular implementation of FIG. 2, the ACC voltage is drawn from circuits 34, 236 and 238 which generate the burst timing identification voltage at terminal T ₂₁ . However, the ACC and identification voltage may be generated separately from separate circuits (eg, sampling circuits of the type shown in US Pat. No. 3,740,456). The response time of each of these separate circuits can be adjusted to suit the specific conditions of a particular system. By way of example, the identification circuit may be provided with a time constant for determining a quick response speed by the principle described above, and the ACC circuit may be arranged to exhibit a slow response speed.

The switching mode control circuit of the present invention is useful not only for PAL type television receivers but also for other PAL type devices (e.g., tape recorders, cameras and image monitors, etc.) that require switching mode identification and control.

The control scheme of the present invention can also be effectively used in conjunction with a decoder of a color television system of the SECAM scheme.

Claims (1)

A luminance component; Deflection synchronization components of line and field frequencies; A chrominance channel for processing said color signal to process a color television signal comprising a chrominance component and a burst component that phase-shift each line with a prescribed mutual time relationship; A plurality of color demodulators for demodulating a predetermined phase of the chrominance component; Switching means for switching and controlling one of the demodulators for each line; A source of periodic trigger pulses occurring at the line frequency; And a timing means (50) coupled to the switching means for supplying a timing signal of 1/2 line frequency to determine the out-of-line switching for each line, wherein the demodulator is accurately synchronized to the alternation of each line of the received signal. In a receiver requiring proper operation to be switched, the receiver is coupled to the chrominance channel and outputs an identification signal in response to the burst component and the timing signal when switching of the demodulator is performed by incorrect synchronization timing. Identification signal extracting means (32, 34, 35) exhibiting rapid response with respect to the line frequency; Coupled to the identification signal extracting means, and responding to the extracted identification signal therefrom and outputting a reset signal as a boot trigger input signal to the timing means, thereby responding to the reset signal and correcting every line from the timing means. And switching means for causing a timing signal corresponding to the synchronous timing of the controller to be generated.

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