KR830000076B1 - Noise cancellation circuit - Google Patents

Abstract

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Description

Noise cancellation circuit

1 is a partial circuit diagram of the noise canceling circuit of the present invention.

2 is a partial circuit diagram of an embodiment of the present invention preventing a sidelock condition.

3A and 3B are cross-sectional views of an integrated circuit including two capacitors of the active filter of the present invention.

4A and 4B are plan views of 3A and 3B integrated circuits.

5 shows the horizontal synchronous signal waveform at the input of the FIG. 1 noise canceling circuit.

6 and 7 show waveforms illustrating noise cancellation according to the embodiment of the invention shown in FIGS. 1 and 2.

8 shows a synchronous pulse of varying width provided by the active filter of the present invention.

9 and 10 show waveforms in a sidelock state.

11 and 12 illustrate waveforms depicting operation of the FIG. 2 embodiment.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise canceling circuit, and more particularly, to a combination of a noise inverter and an active filter for removing impulse noise included in a synthesized video signal while maintaining a rise time of a synchronization signal component of the synthesized video signal. The threshold of the noise inverter changes in response to the level variation of the noise canceled video signal. When the circuit is configured in the form of an integrated circuit, the use of a new active filter provides several advantages in terms of price and function.

According to the television transmission standard scheme, the composite video signal includes synchronous scanning circuits associated with the picture tube in a television receiver and horizontal and vertical synchronization pulses periodically generated for the scanning circuits associated with an image detection device in a television station. In a composite video signal, all horizontal and vertical sync pulses have substantially the same amplitude as the reference level, and the reference level is limited by a particular luminance state (e.g., any black level). The television receiver includes a sync signal separation circuit capable of separating the reference or black level of the video signal and the tip of the sync pulse so that it starts at close to the reference black level and only responds to the signal within a range containing the sync pulse. Frequently, unwanted impulse noise appears in the synthesized video signal, and such noise appears at a level that differs from the sync pulse tip level. Such amplitude impulse noise may cause spurious operation of the synchronous circuit, and may also provide a state within the synchronous separator circuit, known as " impulse noise set-up. &Quot;

Conventional synchronous separator circuits include noise suppression circuitry to prevent noise setup of the synchronous separator. A typical noise suppression circuit cuts impulse noise to a level just above the sync tip level. This technique effectively removes the large amplitude noise pulses from the composite video signal, but the truncated noise pulses are applied to the synchronous separators and are therefore likely to be converted to sync pulses.

The improved noise canceling circuit includes a noise inverting circuit that inverts the noise pulses in the composite video signal. Such a noise inversion circuit uses a direct current threshold or an alternating current threshold for the detection of impulse noise and the generation of inverted noise pulses. The inverted noise pulses are additively combined with the composite video signal to remove impulse noise. In order to ensure the elimination of the granularity of the impulse noise, it is desirable to spread the noise pulse before the synthesized video signal is combined with the inverted noise pulse. It is also desirable to spread the inverted noise pulse so that the incoming portion of the noise pulse can be removed. However, as a delay of the video signal, a reduction in the bandwidth of the sync pulse in which the bandwidth of the synthesized video signal is reduced can be caused, and as such, the pulse width of the sync pulse can be significantly reduced. An excessively narrowed signal due to the excessive delay of the sync pulse appears at the input of the sync separator, so that a sync pulse less than the normal pulse width is generated.

In accordance with an embodiment of the present invention, a DC threshold noise inverter is used to invert the impulse noise in the composite video signal above a predetermined threshold level. Since the AC threshold circuit undesirably increases the detection threshold when noise with a large amplitude is applied, a DC threshold noise inverter is used. Moreover, alternating current threshold circuits are not good because they require restrictive components in being integrated circuits.

The synthesized video signal is also supplied to the ridge filter, and the supplied video signal is delayed as this filter, which combines the delayed signal by the active filter with the noise pulse provided as the noise inverter. Therefore, at the output of the filter, a noise canceled composite video signal is provided.

The filter includes a locker device to increase the transition time of the granularity of the sync signal component, and the proper period of sync and equalization pulses ensures the detection and separation by the sync separator and is caused by the variation of the video signal amplitude due to the plane roar. Minimize the phase modulation of one separate sync signal. The active filter is also combined with a noise inverter that effectively spreads the inverted noise pulse to remove the incoming portion of the impulse noise.

The use of a DC threshold noise inverter can give a false operating state known as "side lock." This condition occurs when the amplitude of the synthesized video signal increases such that the tip of the sync pulse exceeds the threshold of the noise inverter. In this case, the sync pulse can be regarded as a noise pulse by the noise inverter and thus can be inverted, so that the removal of the sync pulse can occur at the output of the active filter. In the horizontal sync pulse, the resulting composite video signal appears to have sync pulses on both sides of the horizontal sync pulse canceled at the front and back porches of the horizontal sync period. These two unnecessary sync pulses are separated by a synchronous separator and applied to the phase lock circuit as a horizontal oscillation signal.

One solution to the problem of side lock is to attenuate the amplitude of the synthesized video signal, thereby eliminating the possibility that the sync tip has reached the noise inverter threshold. However, if the video signal level is reduced in this manner, the signal-to-noise ratio worsens, and the degree of impulse noise cancellation is reduced. As a second solution, when increasing the speed of the AGC system, the AGC circuit returns the video signal to a low level during the vertical period when a wide vertical pulse is sampled by the AGC circuit.

However, increasing the speed of the AGC system increases the sensitivity of the AGC circuit to generate an AGC control voltage in response to the impulse noise contained in the video signal, a condition known as "AGC noise setup."

Incidentally, the side lock condition can be suppressed by changing the DC threshold level of the noise inverter in response to the video signal level at the active filter output. Deactivate the noise inverter by changing the DC threshold whenever the video signal level approaches the noise inverter threshold, and whenever the video signal level approaches the noise inverter threshold, detecting the level of the delayed and noise canceled video signal. To be ecological.

When the video signal level is at a normal signal level, the noise inverter is kept in operation so that the impulse noise included in the video signal is canceled at the output of the active filter.

The noise inverter and the active filter of the present invention can be easily configured as an integrated circuit. The DC threshold noise inverter does not require capacitive elements and can be configured completely as transistors, resistors and diodes. Active filters require two capacitors, but the capacitance values of these devices are extremely low, enabling this configuration to exploit the junction capacitance of semiconductor materials on integrated circuit chips.

Further, the feedback capacitor can be constructed using a low break potential N ⁺ P ⁺ semiconductor junction. N ⁺ P ⁺ capacitor has the advantage of providing a high capacity per unit area on the integrated circuit chip, and also can reduce the error of the capacity value during manufacturing.

The feedback capacitor acts as a low pass filter element against impulse noise by the active filter, so that feedback is provided through this capacitor, thereby increasing the transition time of the standing portion of the sync pulse in the video signal.

The present invention will be described in detail with reference to the drawings. In FIG. 1, the negatively directed composite video signal supplies a bias potential from the video amplifier 4 to the input of the noise inverter 30 and the active filter 50. The video signal is supplied through the resistor 112 to the base of the noise inverter transistor 102. Noise inverter transistors 102 and 104 include differential amplifiers for detecting noise pulses in the video scene. The base of the transistor 102 is prevented from overvoltage due to the diode diode 116. The cathode of the zener diode 116 is connected to the junction between the resistor 112 and the base of the transistor 102 and the anode is connected to the reference electrode (ground). Is connected to the collector of transistor 102. Constant current for the differential amplifier is supplied by transistor 106. The emitter electrode of this transistor 106 is grounded and the base electrode is connected to the Vbe source 80.

The Vbe source 80 consists of transistors 108 and 110 and resistors 118 and 126 to supply the Vbe voltage to the noise inverter 30 and the active filter 50.

Transistor 110 has an emitter electrode that is grounded and a collector electrode that is connected to B ⁺ through the base and resistor 126 of transistor 108. The collector electrode of transistor 108 is connected to the B ⁺ power supply, and the emitter electrode is connected to the base of transistor 110 and grounded through resistor 118. With this configuration, a first Vbe voltage (about 650 millivolts) is applied to the base of the transistor 110 and a second Vbe voltage (about 1.3 volts) is applied to the base of the transistor 108.

The Vbe supply source 80 supplies the first Vbe voltage to the bases of the current source transistors 106 and 140, and supplies the second Vbe reference voltage required for the noise inverting differential amplifier to the base of the transistor 104.

The collector electrode of the differential amplifier transistor 104 is connected to the base of the transistor 120 and the bias resistor 122. Resistor 122 is connected to the cathode of diode 124, and the anode of diode 124 is connected to the B ⁺ power supply. Diode 124 limits the base voltage of transistor 120 to at least a first Vbe level below B ⁺ power level.

Transistor 120 is a PNP transistor whose emitter electrode is connected to B ⁺ power supply via resistor 128. The inverted noise pulse is provided to the collector of transistor 120 and supplied to junction 60, which is a junction of the base of transistor 132 and resistor 54.

Synthetic video synth is also applied from the video amplifier 4 to the contact point 60 through a low pass filter and resistor 42 comprising resistors 44 and 54 and a condenser 48 of the active filter 50. Capacitor 48 is connected between ground and the junction of resistors 44 and 54.

The follower transistor 132 changes the voltage level of the synthesized video signal that is applied to the base electrode of the connection point 60. The collector electrode of transistor 132 is grounded and the emitter electrode is connected to the base of the follower transistor 138. Supply current for transistor 132 and bias current for transistor 138 are supplied through resistor 136, which is coupled to the emitter of transistor 132 and the base connection and power supply of transistor 138. Is connected between B ⁺ .

The collector electrode of the follower transistor 138 is connected to the B ⁺ power supply, and the emitter electrode is connected to the synchronous separator 40, the collector of the transistor 140, and the feedback capacitor 46. The emitter electrode of the current source transistor 140 is grounded, and the base electrode is connected to the first Vbe supply point of the Vbe supply source 80 to supply a constant current to the emitter of the transistor 138. The capacitor 46 feeds back the synth appearing at the emitter of the transistor 138 to a connection point between the resistor 42 and the resistor 44, which is a passage of the input video signal of the active filter 50.

In normal operation, the video amplifier 4 supplies a negatively directed synthetic video signal to the resistor 112 of the noise inverter 30. The synthesized video synth includes a synchronizing signal component, such as the horizontal synchronizing pulse 300 shown in FIG. The tip of the sync pulse 300 is nominally 2.5 volt level and the sync pulse appears on the 4.5 volt video black level pedestal. The horizontal sync pulse pedestal includes a front porch 302 preceding the sync pulse and a back porch 304 following the sync pulse. The synthesized video signal is applied to the base of the differential amplifying transistor 102 of FIG. 1, where the synthesized video signal is compared to the 1.3 volt reference level applied from the Vbe source 80 to the base of the differential amplifying transistor 104. do.

This noise inverter threshold level is represented by dashed line 310 in FIG.

The composite video signal is applied to the active filter 50 at the same time as it is applied to the input of the noise inverter 30, and includes a low pass filter comprising a resistor 42 and a capacitor 46 and a resistor 44 and a capacitor 48. Delayed by. The delayed video signal appears at the connection point 60, which is the output of the noise inverter 30. The composite video signal may contain unwanted impulse noise as shown by the solid line waveform 340 of FIG. The delayed video signal supplied to the connection point 60 through the active filter 50 is shown by dashed line 344 in FIG.

When the noise pulse 104 included in the video signal exceeds the noise inverter threshold 310,

The transistor 102 is in a non-conductive state, and the transistor 104 is in a conductive state. When transistor 104 is in a conductive state, transistor 120 is also in a conductive state, resulting in an inverted noise pulse 346 rising in the collector of transistor 120.

Referring to FIG. 6, at the time T ₀ at which the noise pulse passes the noise inverter threshold 310, the same noise pulse included in the delayed video synch 344 of the connection point 60 is about 0.5 below the pedestal level of the video synch. The amplitude of the volt is reached. Thus, the granular part of the noise pulse at connection point 60 cancels out before the pulse reaches the sync tip level 356 of the video synch. As the noise pulse is canceled in this manner, the sync separator 40 prevents the noise pulse from being inverted into the sync pulse.

The transistor 104 making up the noise inverter 30 is expected to terminate the noise pulse 346 in which the noise pulse 342 is inverted at time T ₁ , while charging by the current from the transistor 120. The active filter capacitors 46 and 48 must be discharged to terminate the inverted noise pulse 346. Thus, the inverted noise pulse 346 as shown by solid line 354 terminates at a subsequent time T ₂ , after which capacitors 46 and 48 are discharged through resistor 42. In this way, the inverted noise pulse 346 supplied by the transistor 120 is effectively unfolded so that the pulse has a period including the arrival portion of the delayed video synth 344 noise pulse. As a result, the spread and inverted noise pulses 346 cancel out the rising and falling portions of the noise pulses contained in the delayed video synth 344 appearing at the connection point 60.

The amplified and noise canceled video signal applied from the emitter of transistor 138 to synchronous separator 40 is shown in FIG. Waveform 352 illustrates removing a portion of the noise pulse above the sync tip level to about 6 volt levels. Only a few parts of the standing and the bottom of the noise pulse have an amplitude that is incomparable to the sync tip amplitude of the sync pulse 350.

When the video synthesizer that does not include the noise of FIG. 5 is supplied to the noise inverter 30 and the active filter 50, the noise inverter does not operate, and thus the signal does not exceed the noise inverter threshold.

However, as a description of FIG. 8 showing the sync pulse 320 having two granular portions, the active filter 50 serves to delay the video signal. The standing part 322-322 'shows the synchronous pulse delayed by the low pass filter containing the resistor 44 and the condenser 48, and the standing part 322-322' has the effect of the feedback condenser 46. The same waveform is considered when considered.

When a synchronous pulse is first applied to the active filter 50, the resistor 42 and the condenser 46 serve as a low pass filter to delay the standing portion 322 of the pulse shown as the standing portion 324 in FIG. Works. When the riser begins to decrease toward the sync tip level, a signal is applied to transistors 132 and 138 through local filters 44 and 48 and resistor 54, where a low impedance output signal is applied to the emitter of the transistor. Supplied. The low impedance output signal is coupled to the video signal input of the active filter 50 through the feedback capacitor 46. The feedback capacitor 46 no longer functions as a low pass filter capacitor and reinforces an impulse as a feedback capacitor.

The signal fed back to the junction of resistors 42 and 44 acts to reduce the time required for the riser to reach the sync tip level, as shown by waveform 324 '. Therefore, the sync pulse period, so there is a sync tip level, while T _2, T ₂ period is not longer than the sync tip time period T ₁ supplied by the low-pass filter (44,48) acting alone. The period of the synchronous tip becomes important when using a peak detection synchronous separator such as that shown in US Patent Application No. 934,821 entitled "Synchronous Signal Separation Circuit." This is because the long sync tip period determines the width of the separated sync pulses. The sync pulse width must be maintained to ensure the correct operation of continuous signal processing circuits, such as the vertical integrator of a vertical deflection system that supplies timing signals for proper interlaced scanning. Moreover, when the video signal fluctuates in amplitude due to plane roar, fluctuations in the sync pulse width will affect the sync separator circuit, resulting in undesirable phase shifted sync pulses.

While the feedback signal is useful in the emitter of transistor 132, it is known that this signal has an undesirable reduced bandwidth (5 MHz) due to the high output impedance of transistor 132 at high frequencies. . Transistors 138 and 140 are included in the active filter 50 for providing a wide bandwidth signal to the emitter of the transistor 138 which is the output of the active filter 50. The transistor 140 maintains the output of the active filter 50 at a low impedance so that noise coupled from the input of the active filter 50 (the connection point of the resistors 42 and 44) through the feedback capacitor 46 is reduced. It blocks the embedded video signal.

The coupling of the feedback capacitor between the output of the active filter 50 and the input signal path provides particular advantages when the circuit is configured in the form of an integrated circuit. The capacitor 46 is coupled between two signal points where virtually the same voltage fluctuations occur when the signal level fluctuates so that the capacitor 46 can be constructed on integrated circuit chips using low voltage and high capacitance N ⁺ P ⁺ semiconductor materials. have. For comparison, the capacitor 48 is connected between the signal path and ground, so it must be able to withstand the highest video signal level (8 to 10 volts with respect to ground) without causing breakdown and be configured as a "pocket" capacitor with low attenuation. Should be done.

Figure 3a typically illustrates a pocket capacitor of an integrated circuit. The integrated circuit device includes a body 210 of a semiconductor, which is usually formed of an embodiment cone, which includes a substrate 230 of a first conductive type and an epitaxial layer 232 of a second conductive type. do. Typically, the conductivity type of the substrate 230 is P type and the epitaxial layer 232 is N type.

A relatively thickly doped localized second region or buried pocket 216 is positioned in substrate 230 adjacent to junction 202. Buried pocket 216 extends into epitaxial layer 232 slightly away from junction 202.

The additional configuration shown in FIG. 3 is as follows. First, there is a P ⁺ type isolation region 214 that divides the epitaxial layer 232 into separate portions 212 and 242. Next, the contact region 218 is formed adjacent to the surface 234 of the epitaxial layer 232 on the pocket 216 embedded to be in electrical contact with a metal conductor (not shown) on the surface 234 of the integrated circuit. do.

The pocket capacitor is formed as an electric field 220-220 'which appears at the junction of the buried pocket 216 and the P ⁺ type isolation region 214. One terminal of the capacitor is located on the surface 234 of the contact area 218, and the other terminal is connected to the grounded substrate 230.

Since the carrier density of the P ⁺ -type isolation region 214 in contact with the buried pocket 216 is relatively low, an electric field 220- penetrating through the pocket junction resulting in a relatively high breakdown potential of 8 to 10 volts relative to the capacitor. 220 ') is also low. Therefore, the capacitor can block the maximum video signal potential of about 9 volts without causing breakdown.

However, the low carrier density of the P ⁺ -type isolation region 214 also causes a relatively low capacity per unit area of the integrated circuit, with a nominal value of about 0.4 pico farads per square mil. Thus, pocket capacitors usually require a large area of the chip or are limited to low capacitance values. Moreover, the relatively uneven carrier density of the P ⁺ type islands 214 in contact with the embedded pocket 216 and the relatively small difference in carrier density between the embedded pocket 216 and the P ⁺ type islands are due to the differences between the chips. It is difficult to adjust the electric field strength. Because of these bad factors, pocket capacitor tolerances can only be maintained at ± 40 percent in high volume manufacturing.

A cross-sectional view of a typical N ⁺ P ⁺ integrated circuit capacitor is shown in Figure 3b. In a pocket capacitor of this type, an N ⁺ P ⁺ capacitor is formed on a semiconductor body 210 including a substrate 230 and an epitaxial layer 232.

The capacitor is located on the portion 252 in the epitaxial layer 232 defined by the P ⁺ isolation region 214. P ⁺ type region 222 having a high carrier density is formed adjacent to the surface of epitaxial layer 232, and N ⁺ region 224 of high carrier density is also adjacent to the surface of epitaxial layer 232. ^It is located in the ⁺ type region 222.

The N ⁺ P ⁺ capacitor is formed by an electric field 226-226 'added to the junction of the N ⁺ region 224 and the P ⁺ region 222. One terminal of the capacitor is located on the surface of the N ⁺ region 224, and the other terminal is located at the junction of the P ⁺ region 222.

Due to the opposite conductivity type N ⁺ and P ⁺ regions 224 and 222 with high carrier density, the strength of the electric fields 226-226 'across the junction of the two regions becomes relatively high. This results in a relatively low brake potential of about 4 volts for the N ⁺ P ⁺ capacitor. Thus, the N ⁺ P ⁺ capacitors are unable to block the maximum video signal potential of the P volts relative to ground without causing breakdown.

However, N ⁺ P ⁺ capacitors have other operational advantages. The high carrier density of the N ⁺ and P ⁺ regions 224, 222 provides a high capacity of about 1.2 peaks per square mill. Moreover, because the two regions are in direct contact with each other in the region closest to the surface of the chip and also have a high opposite carrier density, the tolerance of the capacitor can be maintained at ± 10 percent in high volume manufacturing.

The unique features of the pocket and the N ⁺ P ⁺ condenser are beneficially used in the active filter 50 of FIG. The delay line shown in U. S. Patent No. 3,624, 288 is an RC delay line having a capacitor connected from the signal path to ground to form a low pass filter pocket capacitor or a MOS capacitor. As such, this delay network is a large part of the integrated circuit. However, in the present invention, a pocket capacitor is used for the condenser 48 and an N ⁺ P ⁺ capacitor is used for the feedback capacitor 46. Resistor 44 and pocket condenser 48 include a first local filter capable of withstanding the maximum video signal potential of P volts relative to ground without causing breakdown. Resistor 42 and N ⁺ P ⁺ condenser 46 include a second low pass filter with a breakdown potential of only 4 volts.

However, the capacitor 46 is connected between two points of the signal path. It is shown from the first diagram that the signal at the emitter of the transistor 138 is the same as the signal at the connection point of the resistors 42 and 44 and is only delayed by the first low pass filter and the transistors 132 and 138. .

With this arrangement, the breakdown potential of the condenser 46 will not be exceeded for any critical period of time. As Figures 4a and 4b it is explained how to most advantageously use a high capacity N ⁺ P ⁺ capacitor. FIG. 4A shows the surface cross section of the pocket capacitor of FIG. 3A, and FIG. 4B shows the surface cross section of the N ⁺ P ⁺ capacitor of FIG. The buried pocket 216 of the pocket capacitor of FIG. 4A is shown to occupy the same area as the epitaxial layer isolation portion 252 of the N ⁺ P ⁺ capacitor of FIG. 4B. However, the N ⁺ P ⁺ condenser 46 has about three times the capacity of the pocket capacitor 48 (10 pico farads for 30 pico farads).

Therefore, N⁺P⁺feedback The low pass filters 42 and 46 using a capacitor provide a considerably larger delay in the active filter 50 than the low pass filters 44 and 48 using a pocket capacitor, even if the integrated circuit chip area is the same. Moreover, N⁺P⁺As described above, the capacitor has an additional advantage with respect to the tolerance of the capacitance value.

The error operating state known as "side lock" has been described above. The video signal states that may be the cause of sidelock are shown in FIG. A large amplitude video signal 306 is shown, which may appear due to the sudden application of a strong video signal before the AGC control is completed. The video signal 306 has a front porch 315 and a back porch 317 at a 2.5 volt level, which is the sync tip level of the normal video signal shown in FIG. The tip 316 of the horizontal sync pulse in the video signal 306 is at a 0.5 volt level above the 1.3 volt threshold 310 of the noise inverter 30.

Noise waveform 308 in FIG. 1 represents a delayed video signal supplied to connection point 60 by an active filter delay. Inverted sync pulse 318 cancels the sync pulse of waveform 308 at connection point 60.

The result of this cancellation is shown in FIG. The waveform shown represents the signal supplied to the synchronous separator 40 from the emitter of the transistor 138. This waveform contains two pulses 312 and 314 which are the front and back porches 315 and 317 of the original video signal. The sync separator responds to the pulses 312 and 314 by the generation of two sync pulses, resulting in the sidelock counterpart described above.

The sidelock condition can be eliminated by using the improved noise inverter shown in FIG. The reference numerals of the noise inverter 30, the Vbe source 80, and the active filter 50 in FIG. 1 are also used in FIG.

In FIG. 2, the base of the differential amplifier transistor 104 is grounded through a resistor 178 and is also connected to the emitter of the transistor 180 and the collector of the transistor 162. The collector of transistor 180 is grounded and the base is connected to the junction of the emitter and resistor 118 of transistor 108 that constitutes Vbe source 80. The resistor 126 of the Vbe source 80 shown in FIG. 1 is replaced in FIG. 2 as resistors 166, 168, and 172 that are in series connection between the base of transistor 108 and the B ⁺ power supply.

The base of the current source transistor 106 is connected to one Vbe connection point of the Vbe source 80 through the non-coupling resistor 176. The emitter of transistor 162 is connected to the emitter of corresponding transistor 164 for configuring comparator 160. Emitter current for comparator 160 is provided by constant current source transistor 170, the base of which is connected to the junction of resistors 168 and 172, the collector is connected to B ⁺ power source, The rotor is connected to a reference voltage point through a resistor 174. The collector of transistor 164 is grounded and the base is connected to the output of active filter 50 to which the emitter of transistor 138 is connected.

Whenever the video signal level exceeds the reference level that appears at the base of transistor 162, comparator 160 senses the voltage level of the delayed synthesized video signal that appears at the output of active filter 50 and sets the base of transistor 140. The grounded state is rendered ineffective and the noise canceller is disabled. Resistors 172, 168, 166 and Vbe source 80 include a voltage divider that maintains the base of transistor 162 at a constant reference level of 4.1 volts. As long as the composite video signal level at the base of the transistor 164 is maintained at the above level, the transistor 164 is in a non-conductive state, and the transistor 162 causes a current to flow through the base of the transistor 104. The base voltage of transistor 104 is fixed at 1.3 volts when transistor 162 is brought into conduction due to two Vbe voltage drops of two transistors 180 and 110.

Under this condition, the noise inverter 30 will operate at a 1.3 volt noise threshold level as mentioned in FIG.

When the video signal approaches the noise inverter threshold level, the video signal level at the output of the active filter 50 will exceed the 4.1 volt comparator reference level, and the transistor 164 is in a conductive state and the transistor 162 is It becomes a non-conducting state. Thus, the transistor 162 does not apply current to the base of the transistor 104, and the transistor 104 remains at ground potential through the resistor 178. Resistor 178 also discharges parasitic capacitances at noise inverter 30 and Vbe source 80 to ground. Since all video and noise signals are cut near the ground potential by the video amplifier 4, the noise inverter 30 does not invert the sync pulse that falls below the 1.3 volt nominal noise inverter threshold, so that the side Locking is prevented.

This operation of comparator 160 is illustrated by the waveforms shown in FIGS. 11 and 12. 11 illustrates a normal video signal 332 appearing at the output of the active filter 50. Since the video signal 332 is continuously present on the comparator reference level 330 excluding the sync pulse, the noise inverter 30 continuously cancels the noise pulse to the 1.3 volt threshold except for the sync pulse period. However, it should be noted that noise may be generated while the sync pulse falsely triggers the sync separator 40. This is because the sync separator 40 can generate a sync pulse in this period.

12 shows a strong video signal 334 above the noise inverter threshold 310 at the input of the noise inverter 30. Dotted line waveform 336 represents the delayed video signal that appears at the output of the active filter 50. Unlike canceling the sync pulse 338 mentioned in FIG. 9, even if the input video signal 334 exceeds the noise inverter threshold 310 at time T ₂ , below comparator reference level 330 at time T. The shift of the output video signal 336 at ground level causes the noise inverter 30 to be incapable of canceling the sync pulse 338.

Therefore, the noise inverter 30 becomes impossible to cancel the sync pulse 338, and the sync pulse is supplied to the sync separator 40 for proper peak detection and separation. Although the noise invertor becomes disabled between the time T ₁ to the time T ₃ of FIG. 12, impulse noise is generated while this period does not cause a problem in the television receiver. Since waveform 334 is higher than the normal signal level, correction by the AGC system is required to return the signal to the normal level. By driving the AGC keying signal from the sync separator pulse, the AGC system can take advantage of the noise generated sync pulse by sampling the level of the impulse noise. Since impulse noise occurs in the direction of arrival, AGC control based on this signal level is in the direction of reducing the gain of the television receiver circuit. Thus, the noise generated sync pulse substantially increases the speed of the AGC system to quickly return the video signal to the normal signal level. Furthermore, as shown in US Patent Application No. 934,835, if a matching circuit is used to key an AGC system as a match of a sync pulse and a horizontal repeat pulse, a false sync pulse that occurs at a different time than the horizontal repeat pulse interval It is ignored for AGC keying purposes.

Finally, the impulse noise in the rated level video signal, such as waveform 340 in FIG. 6, does not change the noise inverter threshold level if it falls below this comparator reference level. This is because the comparator 160 senses the level of the noise canceled video signal that appears at the output of the active filter 50. As for the waveform 350 of FIG. 7, the removed noise pulse 352 does not fall below the 4.1 volt comparator reference level.

Further, even though the wedge wave in the granular portion of the removed noise pulse 352 drops below the 4.1 volt reference level, the pulsing effect of the active filter capacitors 46 and 48 continues to cancel the impulse noise, and the transistor The canceled noise pulse 352 appearing at the base of 164 quickly rises above the 4.1 volt reference level, and the noise cancellation continues over and over again.

Claims (1)

A noise canceling circuit for removing impulse noise in a composite video signal, comprising: a first reference potential when the composite video signal exceeds a predetermined level and a second when the video synthesis signal does not exceed a predetermined level Differential amplifiers 102 and 104 having devices 162, 164 and 180 for generating a reference potential, a first input terminal connected to a source of a composite video signal and a second terminal connected to a reference potential generator, and a device 120 connected to a differential amplifier. And an active filter (50) for supplying a video signal through the delay circuits (42, 46).

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