KR820002104B1 - Electron type integrating watt meter - Google Patents

Abstract

The object of this invention is to present an integrating watt meter which has no off-set voltage even in the case of light load, to eliminate off-set voltage error especially variable with time, to increase the accuracy, and to make it suitable for large-scale fabrication. The characteristics of the watt meter are as follows.(1) It has an integrating circuit with operational amplifier where pulse width modulation(PWM) circuit integrates voltage signal proportional to load voltage.(2) It has a comparator circuit which reverses polarity when out voltage of integrating circuit reaches the prescribed valve.

Description

Electronic integrated power meter

1 is a block diagram showing the basic arrangement of an electronic integrated power meter.

2 is a partially block diagram showing an example of an electronic integrated power meter according to the present invention.

3 is a waveform diagram for explaining the operation of the pulse width modulation circuit shown in FIG.

4 is a waveform diagram of various parts of the voltage-to-frequency conversion circuit shown in FIG.

5 is a partially block diagram showing an example of the pulse width modulation circuit of the present invention.

6 is a waveform diagram for explaining the operation of the pulse width modulation circuit shown in FIG.

FIG. 7 is an equivalent circuit diagram of the effect of offset voltage of a comparator circuit in the pulse width modulation circuit shown in FIG. 5. FIG.

8 is an explanatory diagram of the offset voltage effect of the comparison circuit in the pulse width modulation circuit shown in FIG.

9 is a circuit diagram showing an arrangement of a conventional voltage-to-frequency conversion circuit.

10 is a diagram of input and output characteristics of a multiplication circuit obtained when the circuit constants of the circuit shown in FIG. 2 are not in a predetermined relationship.

11 is a partial block diagram circuit diagram showing a voltage-to-frequency circuit of another example of an electronic integrated power meter according to the present invention.

12 is a waveform diagram of a particular part of the circuit shown in FIG.

13 is a diagram of input and output characteristics of the voltage-to-frequency conversion circuit shown in FIG.

FIG. 14 is an equivalent circuit diagram including the effect of offset voltage of the comparison circuit in the voltage-to-frequency conversion circuit shown in FIG.

15 is an explanatory diagram of the effect of offset voltage of a comparison circuit in a voltage-to-frequency conversion circuit.

16 and 17 are voltage-to-frequency conversion circuit diagrams in the third and fourth examples of the electronic integrated power meter according to the present invention, respectively.

18 and 19 are output circuit diagrams of a conventional comparison circuit, respectively.

20 is an output circuit diagram of a comparison circuit in the electronic integrated power meter according to the present invention.

21 is an equivalent circuit diagram of the circuit of FIG. 20. FIG.

22 is an inverter circuit diagram of a C-MOS type field effect transistor in an electronic integrated power meter according to the present invention.

23 is a circuit diagram of an electric source unit used in the electronic integrated power meter according to the present invention.

FIG. 24 is a circuit diagram, partially in block diagram, showing another example of an electrical integrated power meter according to the present invention that can be fabricated in an integrated circuit form.

25 is a partially block diagram showing a modification of a boly phase integrated power meter in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic integrated power meter, and more particularly, to an electronic integrated power meter having improved light load characteristics and stabilized with time.

Since the electronic integrated power meter does not have a movable element mechanically, it is extremely excellent in characteristics with time. That is, its accuracy remains unchanged for a long time. Moreover, it is advantageous in that its size is relatively small, suitable for mass production, and the production price can be reduced by that much. This integrated power meter has a characteristic that the change of charge to the integrated power value or its remote control can be realized by a simple electric circuit.

Electronic wattmeters are therefore likely to replace inductive wattmeters consisting essentially of mechanical components. Various electronic integrated power meters are excluded from this technology.

This conventional electronic integrated power meter has an equivalent circuit as in FIG. In this way, the integrated power meter has a voltage signal e _{v in} which the load voltage of the power supply line is proportional and a voltage signal e _i in proportion to the consumption current of the supply line is multiplied, and thus a voltage signal e _o in proportion to the instantaneous power of the supply line. = k · e _v · e _i , k is a constant) and a voltage-to-band where the output voltage signal e _o of the multiplication circuit M is integrated to supply the frequency signal fout. It is composed of frequency conversion circuit (V _F ). Therefore, this integrated power meter obtains the integrated power value by counting the frequency signal fout from the voltage-to-frequency conversion circuit V _F.

However, since the multiplication circuit (M) and the voltage-to-frequency conversion circuit (V _F ) of the electronic integrated wattmeter shown in FIG. 1 are composed of an operational amplifier, the accuracy of the integrated wattmeter is full range (rating). Note that the offset voltage appears exactly with the result that affects the accuracy of the measurement of the integrated power meter because it is expressed as the absolute error about the measured value instead of the phase error of the. Therefore, the accuracy of the integrated power meter must be guaranteed to be within absolute error even if the input is 1/30 (3.33%) or 1/50 (2%) of the rated (100%). If the rating of the voltage signal ei corresponding to the current consumption is 5 (V), for example, then the 0.5% error corresponds to the conversion value input 25mV when the rating is 100%.

Therefore, even if the input of the conversion value is on the order of 25 mV, then the accuracy will not be so severely affected.

However, in the case of 0.5% error (light load) with respect to 1/50 input, the input of the conversion value is 0.5 mV. Therefore, it is necessary to reduce the offset voltage induced by the operational amplifier of the multiplication circuit M and the voltage-to-frequency conversion circuit V _F to 0.5 mV or less. However, removing the offset voltage from the op amp is quite difficult. In addition, the offset voltage is converted by time and temperature. Therefore, it is difficult to maintain an electronic integrated power meter with high accuracy.

Accordingly, it is an object of the present invention to provide an electronic integrated power meter in which no offset voltage error occurs in the operational amplifier therein, even at light loads, and in particular, the offset voltage error that is changeable with time is clearly eliminated.

Another object of the present invention is to supply an electronic integrated power meter, when its rating is adjusted at the time of manufacture, after which there is no need to inspect or adjust it. It is yet another object of the present invention to provide an electronic integrated power meter, in which its circuit is in the form of an integrated circuit, which is suitable for making on a large scale.

Another object of the present invention is to provide an electronic integrated power meter in which no operational amplifier is used for the multiplication part.

A special object of the present invention is to increase the accuracy of the measurement by giving an electronic integrated power meter with a stable voltage in its various circuits.

New features regarded as features of the invention are set forth in the appended claims. However, other objects and advantages thereof as well as the present invention will be better understood when read in conjunction with the accompanying drawings, with reference to the following detailed exemplary embodiments.

2 is a block diagram showing an example of an electronic integrated power meter according to the present invention. To assist in the full understanding of the present invention, the outline of the present invention will first be described with reference to FIG. 2, and the configuration circuit for it will be described later.

의 출력을 내기위해 펄스폭 변조를 요하는 펄스폭 변조회로(101)를 가지고 있다. 펄스폭 변조회로(101)는 기준전압 ±e_r을 제동하기 위한 기준전압원과 인버어터 회로(G₁)가 설비되어 있다. 변류기(CT)는 부하 전류검출을 위하여 전력공급선에 주어져 있고, 변류기(CT)의 권선은 저항 RL에 의해 션트(SHUNT)되어있다. 번류기(CT)의 권선의 중앙탭은 접지되어 있다. 전력공급선의 소모전류에 비례하는 전압신호 ±ei는 저항 RL의 양단에 나타나고, 두신호의 진폭은 서로같고 위상차는 180。이다. 전압신호 ±ei는 논리신호 "1"로 턴-언(turn on)되고 논리신호 "0"에 의해 턴-오프(turn off)되는 아날로그 스위치 S₁-S₄로 구성된 증배회로(102)에 가해진다.As shown in FIG. 2, in the integrated power meter, a voltage signal e _V proportional to the load voltage applied to the power supply line is sensed by the transformer PT, and the pulse width duty ratio whose voltage signal ev is proportional to the value of the voltage signal ev. Duty cycle signal D and

It has a pulse width modulation circuit 101 that requires pulse width modulation in order to produce the output of. The pulse width modulation circuit 101 is provided with a reference voltage source and an inverter circuit G ₁ for braking a reference voltage ± e _r . The current transformer CT is provided to the power supply line for detecting the load current, and the winding of the current transformer CT is shunted by the resistor RL. The center tap of the winding of the current transformer CT is grounded. The voltage signal ± ei, which is proportional to the current consumption of the power supply line, appears across the resistor RL. The two signals have the same amplitude and phase difference of 180 °. The voltage signal ± ei is applied to the multiplication circuit 102 consisting of analog switches S ₁ -S ₄ which are turned on by the logic signal "1" and turned off by the logic signal "0". All.

The analog switches are made of semiconductor devices such as J-FETs and MOS-FETs. The inputs of analog switches S ₁ and S ₂ are connected to one end of the winding of the current transformer CT, while the inputs of analog switches S ₃ and S ₄ are connected to the other end. The outputs of analog switches S ₁ and S ₃ are commonly connected to a 10w-pass filter consisting of resistor R ₁₁ and capacitor C ₁₁ . The outputs of analog switches S ₂ and S ₄ are also commonly connected to a low pass filter consisting of a resistor R ₁₂ and a capacitor C ₁₂ . The resistance value of the resistor R ₁₁ is the same as that of the resistor R ₁₂ . The capacitance of the capacitor C ₁₁ is equal to the capacitance of the capacitor C ₁₂ .

에 의해 교대로 구동되는 아날로그 스위치 S₁-S₄및 저역 통과 필터를 통하여 나온다. 신호 e_op및 e_on은 전력 공급선의 부하전압에 비례하는 전압신호 e_v와 소모전류에 비례하는 전압신호 e_i의 적(積)에 비례하는 직류전압이다. 즉, 그것은 뒤에 설명되지만 순시전력에 비례하는 직류전압이다. 직류 전압신호 e_op및 e_on은 주파수 변환회로(103) (뒤에 설명하는)에 가해진다. 주파수 변환회로(103)은 각기 저역통과 필터에 연결된 아날로그 스위치 Sa 및 Sb를 가지고 있다.The voltage signal ± ei proportional to the load current of the power supply line is applied to the multiplication circuit in the current transformer (CT), from which the DC voltage signals e _op and e _on which are equal in absolute value and opposite in polarity are pulse width modulation circuits ( Pulse width duty cycle signal D and

It comes out through the analog switches S ₁ -S ₄ and the low pass filter, which are alternately driven by. The signals e _op and e _on are direct current voltages proportional to the product of the voltage signal e _v proportional to the load voltage of the power supply line and the voltage signal e _i proportional to the consumption current. That is, it is a DC voltage that is described later but proportional to instantaneous power. The DC voltage signals e _op and e _on are applied to the frequency conversion circuit 103 (to be described later). The frequency conversion circuit 103 has analog switches Sa and Sb, respectively, connected to the low pass filter.

The output of the analog switches Sa and Sb are connected to the input of the integration (integration) circuit (A ₁₎ consisting of an operational amplifier that is already known through the resistor R21, the other input of it (the integration circuit A ₁₎ is grounded. The output of the integrating circuit A ₁ is connected to one input of a comparison circuit (consisting of an operational amplifier) in which the logic signal "1" or "0" is output whenever the integral output reaches a predetermined value. The output of the integrating circuit A ₁ is fed back to its input via a capacitor C ₂₁ . The other input of the comparison circuit A ₂ is grounded through a resistor R ₃₁ . The switches Sa and Sb are operated by the output of the comparison circuit A ₂ . The output of the comparison circuit A ₂ is applied to the switch Sb via the inverter G ₂ , so that Sb opens when Sa closes and Sb closes when Sa opens.

Moreover, the output of the comparison circuit A ₂ is connected to its other input via the resistance value R ₂₃ of the inverter G ₃ .

In FIG. 2, the reference character e _Q denotes the output voltage of the integrating circuit A ₁ , e _c denotes the voltage at the negative input of the comparing circuit A ₂ , and e _m denotes the switches S _a and S _b . It indicates the voltage applied to the negative input of the integration circuit (A ₁ ) through.

In this way, the logic signal "1" or "0" comes out through the comparison circuit A ₂ by the integral circuit output voltage value. When the comparison circuit A ₂ generates the logic signal "1", the analog switch S _a is closed to introduce the DC voltage signal e _op into the integration circuit A ₁ .

When the comparison circuit A ₂ generates a logic signal "0", the analog switch S _b is closed to introduce the DC voltage signal e _on to the integration circuit A ₁ . In this way, the integral output of the integration circuit A ₁ is proportional to the DC voltage signal e _op or e _on (instantaneous power), and the logic signal of the comparison circuit A ₂ is a preset voltage of the integral output to form a pulse frequency. Inverted by the value. Therefore, the frequency signal f _o proportional to the power can be obtained at the output of the comparator A ₂ .

In FIG. 2, reference characters G ₃ denote inverter circuits, and R ₃₁ and R ₃₂ denote voltage divider resistors. Resistor R ₃₁ and R ₃₂ are the same in resistance value.

The operation of the integrated power meter shown in FIG. 2 is described.

First, the voltage signal introduced by the transformer (PT) e _v is the pulse width which is proportional to the voltage signal e _v dew in a pulse width modulation circuit (PWM) - is converted into a cycle T D.

This is clarified by the waveform diagram shown in FIG.

를 얻을수 있다. 만약 듀-티 사이클 신호 D에서 논리신호 "1"의 간격에 대한 시간폭이 t_a로 표시되고, 논리신호 "0"의 간격에 대한 시간폭이 t_b로 표시된다면, 그때 펄스폭변조회로(PWM)에서 e_v=o이면 t_a=t_b이므로, 50% 듀-티 사이클 신호 D가 얻어진다. 펄스 폭은 전압신호 e_v가 양의 전압일때 이고 그것이 부의 전압일때 t_a＜t_b가 된다. 이러한 펄스폭 듀-티 사이클 신호 D 및

는 e_r이 펄스폭 변조회로 (PWM)의 기준전압인 곳에서 다음과 같이 표현할 수 있다.That is, if a portion of the voltage signal e _v is widened during the period S in part (a) of FIG. 3, then it is shown as in part (d) of FIG. In this case, the voltage signals + e _i and e _i are displayed as part (b) or part (c) in FIG. If the voltage signal e _v in part (d) is subjected to pulse width modulation, then the pulse width duty cycle signal D, as shown in part (e) of FIG.

You can get If the time width for the interval of the logic signal "1" in the duty cycle signal D is denoted by t _a , and the time width for the interval of the logic signal "0" is denoted by t _b , then the pulse width modulation circuit ( In PWM), if e _v = o, then t _a = t _b, so a 50% duty cycle signal D is obtained. The pulse width is t _a <t _b when the voltage signal e _v is a positive voltage and it is a negative voltage. This pulse width du-tee cycle signal D and

Can be expressed as follows where e _r is the reference voltage of the pulse width modulation circuit (PWM).

중에서, 신호 D는 그것이 논리레벨 "1"로 되었을때 증배회로의 아날로그 스위치 S₂및 S₃를 턴-언하는데 사용된다. 그리고, 신호

는 그것이 논리 레벨 "1"로 되었을때 증배회로의 아날로그 스위치 S₁및 S₄를 턴-언 하는데 사용된다.The pulse width duty cycle signal D thus obtained and the signal D were applied to the inverter G ₁ .

Among them, the signal D is used to turn on the analog switches S ₂ and S ₃ of the multiplication circuit when it is brought to logic level "1". And signal

Is used to turn on and off the analog switches S ₁ and S ₄ of the multiplication circuit when it reaches logic level " ₁ &quot;.

로 아날로그 스위치 S₁-S₄의 언-오프동작을 제어하므로써 얻을 수 있다. 신호 e_op및 e_on은 다음과 같이 표현할 수 있다.At that time, the voltage signal ± e _i proportional to the consumption current of the power supply line is introduced into the analog switches S ₁ -S ₄ to obtain the DC voltage signals e _op and e _on . That is, the DC voltage signals e _op and e _on provided by the multiplication of the voltage signals e _v and e _i are the pulse duty cycle signal D and the pulse width modulation circuit PWM.

This can be achieved by controlling the un-off operation of analog switches S ₁ -S ₄ . The signals e _op and e _on can be expressed as follows.

As is clear from equations (3) and (4), the signals e _op and e _on are the same in absolute value and are positive and negative DC voltage signals proportional to the instantaneous power represented by e _i and e _v .

및 D로 스위치 S₁∼S₄의 온-오프 동작을 제어하므로써 얻어질 수 있다. 따라서, 평균치 e_on및 e_op는 방정식(3) 및 (4)에 의해서 제공되는 직류 전압치와 비슷하다. 이점은 제3도의 (f)부분으로 부터 분명해질 것이다. 즉, 제3도의 (f)부분에서, 빗금친 부분의 평균치는 e_on에 해당하고, 나머지 부분의 평균치는 e_op에 해당한다.Equations (3) and (4) can only be established in the state R _{11 ″} R ₂₁ . This ignores the effects of switches S _a and S _b . That is, the average values e _on and e _op of the voltage signals -e _i and + e _i provided when the switches S _{1 to} S ₄ are turned _on are pulse width duty cycles.

And D to control the on-off operation of the switches S ₁ to S ₄ . Therefore, the average values e _on and e _op are similar to the direct current voltage values provided by equations (3) and (4). This will be apparent from part (f) of FIG. That is, in part (f) of FIG. 3, the mean of the hatched portion corresponds to e _on , and the mean of the remaining portions corresponds to e _op .

On the other hand, at the input portion of the integrating circuit A ₁ , the analog switches S _a and S _b are un-off operation asynchronously with the un-off operation of the analog switches S _{1 to} S ₄ .

The resistance of resistor R ₁₁ is estimated to be much less than the resistance of resistor R _21. (R ₁₁ ≪R ₂₁ ) Under this condition, analog switches S _a and S _b are on and off. When operated at, the DC voltage signals e _op and e _on are alternately supplied to the common output of the analog switches S _a and S _b . That is, the voltage signal e _m is obtained as shown in part (a) of FIG. The voltage signal e _m is converted into the frequency signal f ₀ by the integrating circuit A ₁ and the comparing circuit A ₂ as described later.

The circuit constituting the electronic integrated power meter shown in FIG. 2 will now be described in detail. The pulse width modulation circuit shown in FIG. 2 is illustrated in FIG. 5 in more detail. Accurate electrical energy can be obtained without accurate pulse width modulation. Conventional pulse width modulation circuits are subject to interference of the offset voltage of the operational amplifier.

In the secure pulse width modulation circuit in FIG. 5, the voltage signal e _v is applied to the negative input of the integrating circuit A ₁₀ composed of the operational amplifier through the resistor R ₁₀ . The output of the integrating circuit A ₁₀ is applied to the positive input of the comparing circuit A ₁₁ composed of an operational amplifier. The capacitor C ₁₀ is sandwiched between the negative input of the integration circuit A ₁₀ and the output of the integration circuit A10 for integration of the input signal. The output of the comparison circuit A ₁₁ is applied to the negative input of the integration circuit A ₁₀ via the resistor R ₂₄ and on the other hand to the inverter G ₄ . The output of the inverter G ₄ is divided by the resistors R ₂₂ and R ₂₃ , and the synthesized signal is applied to the negative input of the comparison circuit A ₁₁ . The resistance of the resistor R ₂₂ is equal to the resistance of the resistor R ₂₃ . One terminal of resistor R ₂₂ is connected to the negative input of comparison circuit A ₁₁ , and the other terminal is connected to the output of inverter G ₄ . One terminal of the resistor R ₂₃ is grounded and the other terminal is connected to the one terminal of the resistor R ₂₂ . Furthermore, while the other terminal of the resistor (R ₂₂₎ is there connected to one terminal of the resistor (R _13), the other terminal of the resistor (R ₁₃₎ is connected to the positive input of the integrator circuit (A _10), (A The positive input of ₁₀ is grounded through capacitor C ₁₃ . In this way, resistors R ₁₃ and C ₁₃ form a low pass filter.

In FIG. 5, the reference character e _n is the input voltage applied to the positive input of the integrating circuit A ₁₀ , e _h is the input voltage applied to the negative input of the comparing circuit A ₁₁ , and e _k is the integrating circuit. Indicates the output voltage of (A ₁₀ ).

The case will now be described where the low pass filter has been removed in this configured (figure 5) pulse width modulation circuit and the integrating circuit A ₁₀ is grounded like a dashed line.

e_n인 관계가 성립할때 그때 비교회로(A₁₁)의 출력 논리신호 "1"은 "0"으로 바꾸어 진다.A comparison circuit ₍₁₁ A) is a logic signal "1" is a signal e + _r is out, it is intended gekkeum signal -e _r is out a logic signal "0". For easy understanding of the operation, suppose that the voltage signal e _v = 0 and the logic signal "0" is provided at the output of the comparing circuit _Al . In this case, the negative voltage signal e _h obtained by the divided voltage to the voltage dividing resistors R ₂₂ and R ₂₃ is applied to the negative input of the comparison circuit A ₁₁ . Furthermore, a positive voltage signal + e _r is applied to the negative input of the integrating circuit A ₁₀ via the resistor R ₂₄ . Therefore, the integration circuit A ₁₀ integrates with the negative slope mode. The output voltage e _k of the integrating circuit A _{10 depends} on -e _r / 2 and e _k

e _n is then output a logic signal "1" of the comparison circuit ₍₁₁ A) when the relationship is established shall be changed to "0".

As a result, the voltage signal e _h with the value + e _r / 2 is applied to the negative input of the comparison circuit A ₁₁ . Furthermore, the voltage signal -e _r is applied to the negative input of the integrating circuit A ₁₀ via the resistor R ₂₄ . As such, the integration circuit A ₁₀ integrates with a positive slope mode.

e_h인 관계가 성립할때, 비교회로 (A_l1)의 출력 논리신호 "0"은 "1"로 바꾸어진다. 펄스 폭 변조회로(PWM)은 위에 언급한 방법으로 자여발진을 수행한다.The integral force voltage e _k reaches + e _r / 2 and e _k

When the relationship e _h is established, the output logic signal " 0 " of the comparison circuit _Al is changed to " 1 &quot;. The pulse width modulation circuit PWM performs the self oscillation in the above-mentioned manner.

The signals in the various parts of this circuit are as shown in Figure 6, the waveform diagram. If further detail, the sixth degree (a) part of the output signal of the comparing circuit (A _11), (b) part of the input signal e _h is applied to the negative input of the comparator circuit (A _11), and (c) in Denotes an output signal of the integrating circuit A ₁₀ .

As apparent from Fig. 6, when the voltage signal e _v applied to the negative input of the integration circuit A ₁₀ is at 0 [V], then the intervals t _a and t _b of the integration process become equal to each other. That is, 50% du-tee pulses are obtained. In the action of the voltage signal e _v , additional integration is made with the help of resistors R ₁₀ and R ₂₄ , so that pulse width modulation is performed.

가 계산될 것이다. 만약 비교회로(A₁₁)의 출력 논리 신호가 논리 레벨 "1"에 있는 것에 대한 간격이 t_a로 표시되고, 그것이 논리수준 "0"에 있는 것에 대한 간격이 t_b로 표시되면, 그때 간격 t_a에 대한 적분회로 (A₁₀)의 적분출력 e_k는 다음과 같다.Regarding the pulse width modulation circuit, the pulse width duty cycle signal D and

Will be calculated. If the interval for the output logic signal of the comparison circuit A ₁₁ is at logic level "1" is denoted by t _a , and the interval for it is at logic level "0" is denoted as t _b , then the interval t e _k the integral output of the integrating circuit (a ₁₀₎ for _a is as follows.

e _k (t _a ) is the negative directional fraction, so

From equations (5) and (6),

Thus, the interval t _a is

In this case, if R ₁₀ = R ₂₄ then the interval t _a can be represented by the following equation (8).

On the other hand, the integral output e _k for another interval t _b is as follows.

e _k (t _b ) is the positive direction integral,

From equations (9) and (10),

Therefore, the interval t _b is represented by the following equation (11).

In this case, if R ₁₀ = R ₂₄ , then the interval t _b can be expressed by the following equation (12).

는 위에 언급한 결과로부터 다음과 같이 얻을 수 있다.The change ratio of the intervals t _a and t _b by the voltage signal e _v , that is, the pulse width

Can be obtained as follows from the above mentioned result.

That is, the pulse width duty cycle signal D of the circuit PWM is exactly proportional to the input voltage signal e _v , and the characteristics of the capacitor C ₁₀ are removed from equations l3 and 14. Therefore, the pulse width modulation circuit is theoretically quite stable. In the pulse width modulation circuit PWM, the voltage signal e _v is proportional to the load voltage of the power supply line, which is an Ac signal of 50/60 Hz. Therefore, the self-excited frequency in the pulse width modulation circuit PWM is selected to be much higher than 50/60 Hz. Now, the oscillation frequency is the inverse of the interval t _a + t _b .

에서 오차를 일으킨다.However, since the operational amplifier is actually used as the integrating circuit A ₁₀ of the pulse width modulation circuit, the original offset voltage of the operational amplifier is equal to the pulse width duty cycle signal D.

Causes an error in.

가 그러한 오차를 포함하는 사실이 설명된 것이다. 연산 증폭기는 앞서 설명한 바와 같이 펄스폭 변조회로에서 적분회로(A₁₀) 및 비교회로(A₁₁)로 사용된다. 그러나, 비교회로(A₁₁)에서의 오프셋 전압은 다음의 이유 때문에 아무런 오차를 일으키지 않는다. 즉, 오프셋 전압을 포함하고 있는 비교회로(A₁₁)의 등가회로는 제7도에 나타나 있다. 오프셋전압 e_os11이 제7도에 나타난 바와같이 비교회로(A₁₁)의 부의 입력이 제공된다. 그러나, 크기에 관계없이 오프셋 전압이 비교상(제8도) 히스테리시스(hysterisis) 전압과 동상이므로, 그것은 펄스폭 듀-티 사이클 D와

에 영향을 주는 아무런 오차를 일으키지 않는다.Pulse width due-to-cycle signal D and

The fact that includes such error is described. As described above, the operational amplifier is used as an integration circuit A ₁₀ and a comparison circuit A ₁₁ in the pulse width modulation circuit. However, the offset voltage in the comparison circuit A ₁₁ causes no error for the following reason. That is, the equivalent circuit of the comparison circuit A ₁₁ that includes the offset voltage is shown in FIG. As the offset voltage e _os11 is shown in FIG. 7, a negative input of the comparison circuit A ₁₁ is provided. However, since the offset voltage, regardless of magnitude, is in phase with the comparative (figure 8) hysterisis voltage, it is equal to the pulse width du-tee cycle D.

It does not cause any error that affects.

8 illustrates the output voltage of the comparison circuit.

In FIG. 8, a solid line indicates an output voltage when no offset voltage appears and a broken line indicates an output voltage when an offset voltage appears. In each case, the voltage width is e _r , and the values of the time widths t _a and t _b remain unchanged, although there is an offset voltage.

On the other hand, since the offset voltage of the integrating circuit A ₁₀ is continuously applied to the voltage signal e _v , an error occurs as shown in the following equation.

In the case of equations (8) and (12),

는Therefore, the duty cycle signal D and

Is

Therefore, it is necessary to provide an adjusting circuit in order to set the offset voltage e _os (10) shown in equations (17) and (18) to zero. Moreover, it is necessary to use an operational amplifier with less offset drift over time. However, such a measure is undesirable in that the operational amplifier is expensive, with the result of reduced certainty, and also takes time to adjust the offset voltage.

In the pulse width modulation circuit of FIG. 5, an inverter G ₄ having a local pass filter composed of a resistor R ₁₃ and a capacitor C _{13 is} connected to the positive input of the integrating circuit A ₁₀ and to the comparator A ₁₁ . It is installed between the outputs. The voltage e _n obtained by smoothing the output voltage of the inverter G ₄ with a zone pass filter is:

Here, the sign (-) represents a fungal value.

The output of the inverter circuit G ₄ is + e _r with logic signal "1" and -e _r with logic signal "0". These outputs are equal in amplitude and opposite in polarity.

f∑t_b이고, 전압 e_n은 오프셋전압e_os(10)의 크기에 비례하는 양의 전압을 제공한다. 따라서,

인 관계는 인버터회로(G₄)의 출력전압의 진폭을 적당히 선택하므로서 성립할 수 있다. 펄스폭 변조회로(PWM)의 특성을 나타내는 방정식(15)와 (16)에서 적분회로(A₁₀)의 오프셋 전압 e_os(10)은 적분회로(A₁₀)의 부의 입력을 따라 형성된다.AC signal, supplied voltage signal e _v has no DC offset voltage. Therefore, infinity is zero. Therefore, if the time constant of the low pass filter composed of the resistor R ₁₃ and the capacitor C ₁₃ is much higher than the frequency of the voltage signal e _v to zero the offset voltage e _os (10) of the integrating circuit A ₁₀ . If it is made larger, then ∑t _a = ∑t _b and e _n is 0 volts. If the offset voltage e _os (10) is positive, ∑t _a

f∑t _b , the voltage e _n provides a positive voltage proportional to the magnitude of the offset voltage e _os (10). therefore,

The phosphorus relation can be established by appropriately selecting the amplitude of the output voltage of the inverter circuit G ₄ . Offset voltage e _os (10) in a pulse width modulation circuit (PWM) Equations 15 and 16 represent the characteristic of the integrating circuit (A ₁₀₎ is formed along the negative input of the integration circuit ₍₁₀ A).

Therefore, if the offset voltage e _os offset voltage 10, when the voltage e _n a return to the positive input of the integrator circuit (A _10), such as a time integration circuit (A ₁₀₎ e _os 10 becomes the practically erased by .

As will be apparent from the above description, in the pulse width modulation circuit of FIG. 5, the offset voltage e _os of the integrating circuit A ₁₀ can be neutralized by the equipment of the low pass filter feedback circuit. As such, it is possible to use means such as operational amplifiers that are useful and inexpensive for a variety of purposes in order to reduce manufacturing costs or prevent the effects of offset voltage. Moreover, the use of operational amplifiers is quite effective in fabricating pulse width modulation circuits in the form of integrated circuits and in principle eliminates the need to adjust the offset voltage. In addition, since the feedback is made with the help of time constants of resistor R ₁₃ and capacitor C ₁₃ , the offset voltage can be adjusted automatically after a delay of time constant (seconds) due to changes in time or temperature. Can be.

As such, the pulse width modulation circuit is very stable for a long time, and the measurement can be made very precisely as the pulse width modulation circuit.

The voltage-frequency conversion circuit used in the present invention is described.

The arrangement and operation of the frequency conversion circuit 103 shown in FIG. 2 have already been briefly described.

Now, the operation of the frequency conversion circuit 103 is described.

By the output logic signal of the comparing circuit A ₂ , when the switch S _a is turned on in the interval t _c and the switch S _b is turned on in the force t _d , the signals e _op 1, e _on 1, e _op 2, e _on 2, ... The voltage signal e _m is supplied to the integrating circuit A ₁ as indicated in part (a) of FIG.

The voltage signal e _m is integrated in the integrating circuit A ₁ , and its integral output e _Q (part (b) of FIG. ₄ ) is applied to the input of the comparing circuit A ₂ . For comparison, the voltage signal e _c is applied to the other input of the comparison circuit A ₂ . The voltage signal e _c is -e _p / 2 at interval t _c and + e _p / 2 at interval t _d as shown in part (d) of FIG. The integrating circuit A ₁ receives a positive DC voltage signal e _op at interval t _c , which shows a down characteristic. When the integral output e _Q reaches -e _p / 2, the output logic signal of the comparison circuit A ₂ is inversely transformed, and it becomes the interval t _d . At an interval t _d , a negative DC voltage signal e _on is applied to the integrating circuit A ₁ , thereby increasing the integral output e _Q of the integrating circuit A ₁ . When the integral output e _Q reaches + e _p / 2, the output logic signal of the comparison circuit A ₂ is inversely converted and the interval t _c is provided again. In the connection of the fourth degree (C) part of the switches S _a and S _b un-should be noted that points to the OFF state.

Therefore, the inversion period T ₀ of the comparison circuit A ₂ is

to be.

If we substitute e _op and e _on in equations (3) and (4) into equation (20)

이 된다.

Becomes

Therefore, the frequency signal f ₀ is obtained at the output of the comparison circuit A ₂ as shown by the following equation (21).

Since e _p and e _r are always constant reference voltages, the frequency signal f _o has a value proportional to the power consumption (e _i · e _v ) of the supply chain. The integrated power value can be obtained by counting the values.

The frequency conversion circuit of the electronic integrated power meter according to the present invention will be compared with a conventional converter in terms of offset voltage. In the conventional frequency conversion circuit, as shown in part (a) of FIG. 9, in the conversion circuit, the polarity signal inverse conversion circuit A _o is applied to the front end of the integration circuit A ₁ to realize a double slope characteristic. Installed. Inverting circuit A _o is provided to obtain signal -e _op . The signal ± e _op is applied to the integrating circuit A ₁₅ by the switching _operation of the switch S _w .

In part (a) of FIG. 9, the reference character A ₁₆ designates a comparison circuit. Thus, the polarity signal inverse conversion arc A _o requires an operational amplifier and is interfering with the original offset voltage of the operational amplifier under light load (ie, when the level of the input signal e _op is low). Offset voltages cause a large feature error for integrated power meters where measurement clarity is more important than the full range of accuracy.

In contrast, in the integrated power meter according to the present invention, the signals e _op and e _on , which have the same absolute value and are opposite to the polarity signal, are obtained in the process of multiplication of e _v and e _i . Therefore, errors are hardly caused even at light loads.

In the multiplication circuit of the example (example) of the electronic integrated power meter according to the present invention shown in FIG. 2, the comparison circuit A represented by the DC voltage signals e _op and e _op and equation (20) of equations (3) and (4) (A). _second frequency signal of the inverse conversion period T _o, and equation (21)) is f _o is the resistance (R ₁₁₎ and (R ₁₂ go previously described) is established only when the right conditions, R ₁₁ «R _21. Therefore, considering the values of resistors R ₁₁ and R ₂₁ ,

1000R₁임을 의미한다. 따라서, 예를들어, 만약 저항체(R₁₁)의 저항이 10㏀이나 그 정도라고 하면, 그때에 저항체(R₁₂)의 저항은 10㏁보다 높다. 그러므로 그 저항의 높은 안정성을 얻는 것이 어렵다. 이 어려움은 저항체(R₁₁)의 저항을 줄이므르써 제거될 수도 있다. 그러나, 이 방법은 전압신호 e_i및 e_v가 상용 주파수(50/60Hz)의 AC 신호이므로, 상당히 큰 시정수(R₁·C₁)를 가지는 저역 통과 필터를 설비하는 것이 필요하다는 점에서 유리하지 못하다. 그러므로 저항체(R₁₁)의 저항의 감소는 제한되어 있다.This equation (22) gives R ₂ when linearity is 0.05% or more.

1000R ₁ means. Thus, for example, if the resistance of the resistor R ₁₁ is 10 kΩ or so, then the resistance of the resistor R ₁₂ is higher than 10 kΩ. Therefore, it is difficult to obtain high stability of the resistance. This difficulty may be eliminated by reducing the resistance of resistor R ₁₁ . However, this method is advantageous in that since the voltage signals e _i and e _v are AC signals of commercial frequency (50/60 Hz), it is necessary to install a low pass filter having a fairly large time constant (R ₁ · C ₁ ). I can't. Therefore, the reduction of the resistance of the resistor R ₁₁ is limited.

When the condition R ₁₁ &lt; R ₂₁ is not satisfied, then the second term in equation (22) represents the quadratic characteristic, so when e _v is a constant, the upper curve is the new e _i -f _o -characteristic curve and the lower As shown in FIG. 10, in which the curve is an abnormal characteristic curve, the input / output curve of the multiplication circuit is a saturation mode. Thus, the nonlinearity described above affects the portion of the pulse coefficient connected to the output of the multiplication and frequency conversion circuits, and therefore it is difficult to measure electrical energy with high accuracy.

The effect of nonlinearity can be overcome by installing an impedance conversion operational amplifier A ₃ in front of the integrating circuit A ₁₇ as shown in part (b) of FIG. 9.

However, addition of the operational amplifier (A ₃₎ raises the manufacturing cost, the offset voltage of the operational amplifier (A ₃₎ there is provided a further problem with the light load. Even if the offset voltage of the operational amplifier A ₃ is adjusted externally, problems such as a change in time or a temperature change still exist. In fact, it is necessary to use expensive op amps with low drift.

In order to overcome the difficulties described above and to improve linearity or accuracy, another example of the electronic integrated power meter according to the present invention is the frequency conversion portion as shown in FIG.

In this frequency conversion section, the operational amplifier A ₃ described above is not installed in front of the integrating circuit A ₁ , but instead a linearity correcting resistor R ₄ is used for the linearity correction. It is installed in a feed back system extending from the output of A ₁ ) to the negative input of the same circuit. In other words, the nonlinearity caused by the resistor R ₁₁ of the low pass filter or resistor R ₂₁ connected to the integrating circuit is corrected to linearize the input-output characteristics. The series of operations for obtaining the DC voltage signals e _op and e _on and the related frequencies for power of the same absolute value and opposite polarity is similar to that in FIG. Therefore, the effect of providing only the linearity correction resistor R ₄ will be explained.

Parts (a) and (b) of FIG. 12 are diagrams indicating the input voltage e _m and the output voltage e _Q of the integrating circuit A ₁ each having a linearity correcting resistor R ₄ connected thereto. The integral output characteristic when the resistor R ₄ is not connected is as indicated by the dotted line. With a connected resistor (R ₄ ), the output voltage jumps by e _s when the analog switches (S _a ) and (S _b ) are switched. The amplitude of this jump is

to be.

Therefore, it is proportional to the multiplication DC voltage signal e _op or e _on . Therefore, the integration process of the integration circuit A ₁ is reduced by the jump voltage e _s . Thus, when the resistor R ₄ is connected, the output frequency characteristic of the frequency converter is completely opposite to that shown in Fig. 13 and shown in Fig. 10, in which the upper curve is an ideal e _m -f _o characteristic curve. And the lower curve is the new f _o -e _m characteristic curve.

Thus, if the values of resistors R ₁₁ , R ₁₂ and R ₄ and capacitor C ₂₁ are properly selected in the circuit of FIG. 11, then the error with respect to the multiplication circuit is canceled, and the values e ₁ and A frequency signal having an ideal characteristic proportional to e _v can be obtained.

Similarly to the pulse width modulation circuit, the operational amplifier was also used as the integrating circuit A ₁ and the comparing circuit of the frequency converter. Therefore, the offset voltage of the amplifier causes an output error, which poses a problem at light loads. However, as explained with reference to FIGS. 7 and 8, the offset voltage of the comparison circuit A ₂ causes no error. This is evident from Figures 14 and 15, similar to Figures 7 and 8. That is, the offset voltage e _os2 of the comparison circuit A ₂ is just in phase with the hysteresis voltage, which is the reference voltage for comparison, and it has no effect on the output at intervals T _c and T _d at which frequencies are determined.

The offset voltage e _os1 of the integrating circuit A ₁ is supplied in series with the DC voltage signals e _op and e _on , causing an error. The effect of the offset voltage of the integrating circuit A ₁ will be explained with reference to FIGS. 2 (or 12) and 4. The integral output T _Q (t _c ) at the interval T _c is

therefore,

The integral output e _Q (t _d ) at interval t _d is

therefore,

Thus, the period T _o is

From this equation the frequency f _o is;

With the dc voltage signal e _op which is the multiplication of e _i and e _p , equation (26) can be rewritten as

(k is a constant)

If the offset voltage e _os1 of the integration circuit A ₁ is zero (e _os1 = 0), from equation (27):

The ideal output frequency is obtained. (k. e _i. e _v) »e when the _os1, obtained is the quadratic equation, and can be error is very small, therefore. However, at light loads, the value (k. E _i . E _v ) is sometimes small. In this case, it is impossible to avoid the result of the error due to the offset voltage e _os1 in the frequency conversion circuit shown in FIG. 2 or 11 due to the characteristic of equation (27).

In order to eliminate the effect of the offset voltage and to make a measurement with high accuracy, another example of the frequency converter in the electronic totalizing power meter according to the present invention will be described with reference to FIG. In this frequency converter, the lowpass filter, consisting of resistor R ₅ and capacitor C ₃ , is connected to the positive input of integrating circuit A ₁ and the inverter circuit G ₃ (positive input is not directly grounded). ) Are connected. The voltage e _f obtained by smoothing the output voltage of the inverter circuit G ₃ with the low pass filters R ₅ and C ₃ can be calculated as follows.

e _f = t _c (-e _p ) + t _d (e _p ) (29)

가 인버터 회로(G₃)의 출력 레벨(e_p의 진폭)을 적당히 선택하므로써 얻을 수 있다.The inverter circuit G _{3 generates} a signal + e _p having a logic signal "1" and a signal -e _p having a logic signal "0". The signal ± e _p is the same in amplitude and the polarity is reversed. The DC voltage signals e _op and e _on applied to the integrating circuit A ₁ also have the same absolute value and the opposite polarity. If the offset voltage e _os1 of the integrating circuit A ₁ is zero, then t _c = h according to the results of equations (24) and (25), and the voltage e _f is zero. If the off cell voltage e _os1 is positive, then t _c <t _d and the voltage e _f provides a positive voltage. If the off-cell voltage e _os1 is negative, then t _c <t _d and the voltage e _f provides a negative voltage. therefore,

Can be obtained by appropriately selecting the output level (amplitude of e _p ) of the inverter circuit G ₃ .

Regarding equations (24) and (25) representing the integration characteristic, the offset voltage e _os1 is modeled at the negative input (see FIG. 14) of the integration circuit A ₁ ). Therefore, if a voltage e _f equal to the voltage e _os1 is applied to the positive input of the integrating circuit A ₁ after being smoothed by a lowpass filter consisting of resistor R ₅ and capacitor C ₃ , then the offset voltage e _os1 can be offset physically.

As is clear from the above description, in the frequency converter shown in FIG. 16, the offset voltage of the integrating circuit A ₁ having an operational amplifier can be corrected simply by providing a feedback circuit, that is, a low pass circuit. Thus, the use of operational amplifiers for a variety of purposes and inexpensive cost makes it possible to eliminate the effects of offset voltage and to fabricate the frequency converter portion in the form of an integrated circuit. Moreover, for the same reason, it is not necessary to adjust the offset voltage externally. In addition, the feedback was made based on the time constants of the resistor R ₅ and the capacitor C ₃ . Therefore, even with time or temperature changes, the offset voltage is automatically adjusted after a time constant delay (several seconds), and therefore the frequency converter can remain stable for a long time.

Another example of the frequency conversion circuit of the electronic integrated power meter according to the present invention is shown in 17th. In the frequency converting circuit of FIG. 16, the output of the inverter circuit G ₃ is fed back to the positive input of the integrating circuit A ₁ . On the other hand, in the frequency conversion circuit of FIG. 17, the output of the inverter circuit G ₃ is fed back to the positive input of the integration circuit A ₁ via another integration circuit A ₂₀ . The output of the inverter circuit G ₃ is applied to the negative input of the integrating circuit A ₂₀ via the resistor R ₅ . The positive input of integrating circuit A ₂₀ is grounded. Capacitor C ₂₂ is connected between the output of integrating circuit A ₂₀ and the negative input. The output of the integrating circuit A ₂₀ is input to the negative input of the integrating circuit A ₁ via a resistor R ₆ .

The output of the comparison circuit A ₂ is fed back to the negative input of the integration circuit A ₁ via the integration circuit A ₂₀ as described above. This removes the offset voltage contained in the input voltage e _op or e _on .

In the frequency conversion circuit shown in FIG. 16, the offset voltage of the integrating circuit A _j is corrected but it is impossible to completely remove the offset voltage included in the input voltage e _op or e _on . Input voltage e _op or an input voltage included in the e _on the switch S ₁ ~S ₄ and switches S _a and S _b of the unloading of the multiplication circuit, the value of the off operation because then, _op e is offset by the voltage e _on You can also derive from the value of. For this reason, the output of the integrating circuit (A ₂₀₎ sets the voltage e ^s in the input portion of the be fed back to the negative input of an integrating circuit (A ₁₎ an integrating circuit (A ₁₎ as a 0 [v]. As such, the offset voltage including the input voltage e _op or e _on may be corrected.

The stabilization of the output voltage of the comparison circuit will be described. The comparison circuit has been described with reference to FIG. 2 or FIG. The output of the comparator should have a value + e _p or + e _r with logic signal "1" or a value -e _p or -e _r with logic signal "0".

In general, the output circuit of this type of comparison circuit is composed of a bipolar integrated circuit as shown in FIG.

In Fig. 18, the reference character e _in is a signal obtained by converting the differential input. When transistor Q ₃ is energized (on) by signal e _in , transistor Q ₂ is also energized and produces a voltage output of approximately -V _ee . On the other hand, when transistor Q ₃ is deenergized Transistor (Q ₁ ) is energized, resulting in a voltage output of approximately + V _ee .

In such a circuit, the saturation voltages of transistors Q ₁ and Q ₂ are limited. In particular, an offset voltage of about 2V comes from transistor Q ₂ . Thus, for example, when a ± 15V power supply is used, the output voltage is about 14.5V when the logic signal is "1" and about -13V when the logic signal is used.

To overcome this difficulty, one method can be used, in which a Zener diode D _z is connected to the output of the comparison circuit to clamp the output voltage as shown in FIG. This stabilizes the amplitude of the output voltage.

However, with this method, it is difficult to keep the positive and negative output voltages the same because the zener diode Dz fluctuates in the zener voltage.

In order to solve this problem, the output circuit of the comparison circuit is composed of C-MOS circuits in each example of the electronic integrated power meter as shown in FIG. 20, and in FIG. enhancement) MOS field effect transistor. Transistor Q11 is a P-channel field effect transistor, while transistor Q11 is an N-channel field effect transistor. In this circuit, when the transistor Q13 is energized, the P-channel field effect transistor is energized, and when the transistor Q13 is not energized, the N-channel field effect transistor Q12 is energized.

The characteristic of this circuit is that since the field effect transistors Q11 and Q12 are voltage regulating elements, no offset voltage actually occurs. Therefore, an equivalent circuit as shown in FIG. 21 can be obtained by replacing the circuit of FIG. 20 with a resistance circuit. In general, each of the MOS type field effect transistors Q11 and Q12 shows tens of ohms to hundreds of ohms when energized, and shows high resistance of several thousand mega ohms. Thus, the circuit in FIG. 20 can be replaced with a switching circuit as shown in FIG. Therefore, the amplitude of the output voltage of the comparison circuit using the C-MOS type field effect transistors Q11 and Q12 is represented by the following equation (30) when the output logic signal "1", and the output logic signal "1". Is represented by the following equation (31).

Where e _OH is a high level of output e _O and e _OL is a low level of output e _O.

In Fig. 21, reference characters rds.n and rds.n respectively denote resistances of the field effect transistors Q11 and Q12, and the reference character RL is a load resistance.

Therefore, if the supply voltage V _DD becomes equal to the supply voltage -V _SS, and the switched-on resistance of the field effect transistor Q11 becomes that of the field effect transistor Q12, the value (absolute value of amplitude) e _OH It is possible to make equal to the value e _OL . In this manner, the output voltages ± e _p and ± e _r of the comparison circuit described above can be accurately obtained by the network (circle configuration) shown in FIG.

The output stabilization of the inverter circuit will be described.

Similarly to the comparison circuit of FIG. 20, an inverter circuit composed of C-MOS type field effect transistors Q21 and Q22 is shown in FIG.

N-channel field effect transistor Q22 is energized to generate signal-e _p when voltage + e _p is applied to the input of this circuit, and P-channel field effect is applied when voltage-e _p is applied to the input of this circuit. The transistor energizes and generates an output signal + e _p . Also in this circuit, the output voltage obtained by inverting the input voltage can be accurately obtained by making the switch-on resistances of the field effect transistors Q21 and Q21 equal to each other. As will be apparent from the above description, the output circuits of the comparison circuit and the inverter circuit are composed of C-MOS field effect transistors, and the saturated "on" resistance of the P-channel field effect transistor connected to the power supply + V _SS is the power supply -V _SS. This is the same as that of the N-channel field effect transistor connected to the power supply, and this power supply + V _DD and -V _SS is made of the same amplitude and high safety to drive the transistor. Therefore, the preset voltage output can be obtained with high accuracy.

23 shows a power supply unit for driving various parts of the electronic integrated power meter.

In the electronic integrated wattmeter, the power supplies + V _DD and -V _SS were actually used for the reference voltages e _p and e _r . Therefore, it is necessary to supply positive and negative power with the same voltage amplitude because of the characteristics of the reference voltages e _p and e _r .

Since the total current consumed in the electronic integrated wattmeter of the present invention is about several amperes, as shown in FIG. 23, a power that is easily tracked is used in the integrated wattmeter. In FIG. 23, the reference character REG indicates a positive voltage regulator. The output voltage e _o of the regulator REG was chosen to fit the equation:

e _o + V _DD -(-V _SS )

The midpoint voltage OV is determined by the resistors R40 and R41 and the impedance conversion buffer amplifier A30. Thus, for example, in order to be ± 12V as a power source, it is necessary to equip a 24V regulator and make the resistance of the resistor R40 equal to the resistance of the resistor R41 (R40 = R41). An operational amplifier was used as the buffer amplifier A30. Because of the configuration of the circuit shown in FIG. 23, the operational amplifier has an infinite input impedance and practically has a zero output impedance. Therefore, the input voltage e _z of the buffer amplifier A30 is;

This value shows that the voltage at the midpoint of this circuit is OV. Therefore, when the output voltage of the buffer amplifier A30 is OV,

therefore,

Therefore, in this power supply section, the change in the output voltage e _o of the regulator REG is evenly distributed to the voltages + V _DD and -V _SS . In this way, this power supply is used as a fully tracked power supply.

In the integrated power meter described above, the pulse width modulation circuit and the frequency converter are respectively integrated circuits, comparison circuits with output buffers using C-MOS field effect transistors, and analog switches S ₁ -S ₄ and S _a and S _b . use.

In general, it is difficult for a monolithic IC to mix passive components, but it is possible for a monolithic IC to mix active components. Thus, if an integrating circuit composed of operational amplifiers and an analog switch are made as an active element, then this integrated power meter can be made in the form of a monolithic IC.

24 shows an example of an integrated power meter configured in the form of an integrated circuit (IC). In Fig. 24, the multiplication circuit section 10 having the pulse width modulation circuit (shown in dashed lines) is identical in arrangement with the frequency conversion section 20 in which the voltages e _op and e _on after the multiplication are adapted for frequency conversion.

In Fig. 24, the elements already described with reference to Figs. 5 and 16 are therefore numbered dissimilarly, and their operations are inversely similar to those previously described. The switches S _c and are additionally given to the frequency converter 20. Switch S _c and S _d is the DC voltage signal e _op e and _on the switch as shown in the unloading Sa~S _d from - to be turned OFF and has a resistance (R _20), regardless of the constant load resistance (R ₂₀₎ . More precisely, a resistor R ₂₀ having the same value as the input resistance of the integrating circuit A ₁ is connected to the analog switch S _c and the common contact above. The circuit configuration shown in Fig. 24 can be obtained by installing two ICs which are structurally the same, which reduces transmission data and manufacturing cost and facilitates maintenance (contact and maintenance). In order to operate the integrated power meter shown in FIG. 24 with high precision, the power supply section used in FIG. 23 described above should be used.

The present invention has been described with reference to a single phase two linear integrated power meter. However, if a plurality of signal detection units including transformers PT or current transformers CT and a plurality of multiplication circuit units 10 are installed, then the present invention can also be applied to a poly phase integrated power meter.

25 shows an example of a multiphase integrated power meter according to the present invention. In this multiphase integrated power meter, electrical energy is the sum of the polyphase power.

_{P o = e v l · e} i 1 + e v2 · e i2 + e vn · e in (35)

의 도움으로 아날로그 스위치 S₁∼S₄에 의해 스위치 되어, 그리하여 위상에 대해 각기 증배되는 신호들은 저역통과 필터에 의해 더해진다. 결과적으로, 방정식(35)를 만족하는 전력 Po가 얻어질 수 있다. 역시 위에 설명한 다상의 적산전력계에서, 펄스폭 변조회로를 포함하는 증배 회로부(10)은 매 위상에 대해 한개의 IC로 구성될 수 있다.In this case, the voltage signal e _i proportional to the consumption current of the corresponding phase is equal to the pulse width duty cycle signal D of the pulse width modulation circuit and

With the help of the switches are switched by analog switches S _{1 to} S ₄ , so that the signals each multiplied with respect to the phase are added by a low pass filter. As a result, a power Po that satisfies the equation 35 can be obtained. Also in the multiphase integrated power meter described above, the multiplication circuit section 10 including the pulse width modulation circuit may be composed of one IC for each phase.

Since the frequency converter 20 can be used in common for all phases, the multiphase integrated power meter is similar to the single phase integrated power meter in this respect.

In the example described above, the voltage signal e _v is applied to the pulse width modulation circuit, and the voltage signal e _i is applied to the multiplication circuit. However, it is clear that the voltage signal e _v may be applied to the multiplication circuit and the voltage signal e _i may also be applied to the pulse width modulation circuit. As is apparent from the above description, according to the present invention, in a pulse width modulation circuit having an integral circuit and a comparison circuit composed of an operational amplifier, the offset voltage is caused by the operational amplifier, but the offset voltage is equal to the offset voltage. It can be removed by applying to the input of the op amp by a low pass filter installed in the feedback system. Therefore, the pulse modulation circuit can be made into a general purpose op amp inexpensive, and the pulse width duty cycle can be obtained with high accuracy without externally adjusting the offset voltage. In a low pass filter, the feedback is made by the time constant provided by the resistor and the capacitor. Therefore, even if the offset voltage changes with time or changes with temperature, the low pass filter is automatically adjusted to comply with the change of the offset voltage.

As such, the integrated power meter according to the present invention can operate stably for a long time.

In addition, the frequency conversion portion is composed of an integration circuit and a comparison circuit composed of operational amplifiers, and have an effect as described above.

The output circuit of each pulse width modulation circuit or the comparison circuit of the frequency conversion portion is composed of a P-channel C-MOS field effect transistor and an N-channel C-MOS field effect transistor. Eliminate variations in the positive and negative output voltages involved. That is, since the C-MOS type field effect transistor is a voltage regulated device, the difference between its "on" resistance and "off" resistance is quite large. Therefore, the C-MOS type field effect transistor is used as a complete switching circuit. This principle can be applied to the inverter circuit as well as to the integral circuit of the frequency conversion part.

To obtain a positive and negative supply voltage, an op amp with an output impedance of zero and infinite input impedance is connected to the voltage division resistor circuit of the output circuit of one regulator, resulting in exactly positive and negative power. . Furthermore, according to the present invention, the multiplication circuit having the pulse width modulation circuit is the same in structure as the frequency conversion portion, and the multiplication circuit and the frequency conversion portion are composed of active elements.

Therefore, these circuits are suitably manufactured in the form of integrated circuits, and as a result, the size of the electronic integrated power meter is minimized.

Claims (1)

A pulse width modulation circuit for pulse width modulating a voltage signal proportional to the load voltage of the power supply line to obtain a pulse width duty cycle signal; From the pulse width modulation circuit so that the positive and negative DC voltages obtained from the result of the voltage signal proportional to the current consumption of the power supply line and the pulse width duty cycle signal resulting from the voltage signal proportional to the load voltage are equal in absolute value. A multiplication circuit for selectively operating a plurality of analog positions with the aid of the generated pulse width duty cycle signal; A double integrated frequency conversion circuit for converting a positive and negative DC voltage into a frequency signal, wherein the pulse width modulation circuit is configured for the negative input of the negative signal for an additional part of the voltage signal proportional to the load voltage. An integrated integrated power meter comprising: an integrating circuit having an operational amplifier applied to the comparator; and a comparing circuit in which the polarity is reversed whenever the integral output voltage of the integrating circuit reaches a predetermined value.

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