KR800001164Y1 - Solid state electronic timepiece - Google Patents

Abstract

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Description

Electronic clock

1 is an overall appearance of the watch in the state of the present invention.

2 is a drive block circuit diagram of the present invention clock.

3 is a circuit diagram for integration display which is a main part of the present invention.

4 is an integrated display mode.

5 to 30 are circuit diagrams and display form diagrams of another embodiment of the present invention.

The present invention is an electronic clock having an apparatus for displaying time analogously using an optical display element such as a liquid crystal or a light emitting diode. More specifically, the second display is performed by each display function of a plurality of display elements. It relates to a display device.

Conventionally, in the digital electronic clock or the like, in particular, one display element is formed on the clock surface, and the second display element is simply flashed for one second, and the time of hours, minutes, seconds, etc. All digitally displayed numbers are already known and are in practical use. However, since the former only flashes one display element for one second, the elapse of seconds cannot be known, and therefore, the blink display is only a confirmation mark that the clock is operating. In addition, in the latter case, since the second changes quickly, not only is it difficult to read, but especially when the liquid crystal is used as the display element, the response of the liquid crystal is bad, and thus there is a defect that is more difficult to see.

The present invention eliminates the above-described drawbacks, wherein a plurality of display elements are arranged, among which, one display element is used as a starting point, and a display function is successively shifted to another display element at an arbitrary time interval, thereby shifting the display function. The present invention aims to provide an electronic clock that is excellent in design by displaying at least one time by arranging the display element on the surface of the clock.

The present invention will be described below with reference to the accompanying drawings. In addition, in the embodiment of the present invention, but only one example of the "super display" is not limited to the super display.

In Fig. 1, the embodiment of the present invention embodies the appearance of a digital electronic clock, and the surface of the clock main body 1 is located below the date display element 2 and the date display element 2; The ultra-display element group 4 positioned under the day of the week display element group 3 and the dual-display element group 3, and the hour and minute display elements 5 positioned under the hyper-display element group 4. ) And (6), two divisional display elements 7a and 7b are formed between the display element 5 and the minute display element 6, and one of the division display elements is formed. When the elements 7a or 7b are lit, the morning is displayed, and when 7a and 7b are lit at the same time, this is an example of an electronic clock composed of display elements configured to display afternoon. As described above, each of the display elements is formed of an optical display element, and the display of time and minutes is an example in which digital display and second are analog display.

That is, it is a subject of the present invention to arrange a plurality of superdisplay elements and to display the superdisplay elements in a flashing, lighting, or extinction format at an arbitrary time interval. Therefore, in the case of this electronic clock, the example of the time drive circuit is the same as that of 2nd degree. In Fig. 2, for example, the storage oscillator 10 having a frequency of 32,768 KHz divides it up to 1 second pulse, and divides the output of the frequency divider 11 to 10 seconds pulse. (12), a divider 13 for dividing the output of the divider 12 to one minute pulse, a divider 14 for dividing the output of the divider 13 to one hour pulse, and a divider 14 A divider 15 for dividing the output to 12 hours pulses, a divider 16 for dividing the output of the output to 1/2, and a second decoder 17 to which the output of the divider 13 is applied, Split decoder 18 to which the output of the divider 14 is applied, and there are CD decoders 19 to which the output of the divider 15 is applied, and each decoder 17, 18, 19 and The output of the divider 16 is applied to the drive device 20 for driving the time display device 21, and displays the time on the time display device 21. The divider 16 is a divider for AM-PM display. Here, the description of the date and day display driving is omitted.

Here, the gist of the present invention is, for example, using a shift register or a ring counter for the divider 13 for the second display, and the display element by the logic of the shift register or the ring counter and the decoder 17. The second reading was made possible by the arrangement of flashing, flashing, and extinction. An example is shown below in FIG.

3 to 30 show an example of displaying 60 seconds using six display elements, in which the divider 13 is replaced with a 6-bit shift register.

It demonstrates in the following order.

In FIG. 3, the 6-bit shift register 22 is always supplied with a signal ("1") (voltage having a predetermined voltage value, the same as below) at the lead line A, and the divider 12 is applied. The shift pulse is applied every 10 seconds via the output lead line B in the. Therefore, when 10 seconds have elapsed after resetting the register, a signal of "" 1 "] appears on the output lead line 22a of the shift register 22, and every 10 seconds elapses, the right output lead line ( 22b), 22c)... … Signal of "" 1 "appears on the display, and when 60 seconds have elapsed, all of the signals of" "1"] appear from (22a) to (22f), and all of the registers are displayed with the signal of the output lead line 22f. Reset at the same time. The output leads 22a-22e are connected to the decoder 17. That is, the decoder 17 includes five OR gates 23a and 23e and five AND gates 24a and 24e. Output lead lines 22a to 22e of the shift register are correspondingly connected to one input terminal of 23e, and a one second pulse is applied from the divider 11 to the other input terminal of each or gate. Common lead wire C is connected. In addition, the output lead wires 22a-22e of the shift register 22 are connected to the pressure terminal of the AND gates 24a-24e. The output lead line of the OR gate 23b is connected to the other input terminal of the AND gate 24a, and the output lead line of the OR gate 23c is different from the AND gate 24c to the other input terminal of the AND gate 24b. The output lead line of the OR gate 23d is connected to the input terminal of the side, and the output lead line of the OR gate 23e is connected to the other input terminal of the AND gate 24d, and the output lead line of the OR gate 24e is connected to the other input terminal of the AND gate 24e. The common lead line C for applying one second pulse ["1"] is connected. The output lead wires of the AND gates 24a and 24e and the output lead wires of the left ore gate 23a are removed from the driving device (exciter for power amplification) to display the super display element 41. (42), (43), (44), (45), and (46) are connected correspondingly. In addition, in the embodiment of the present invention, the superdisplay elements 41 to 46 use liquid crystals to form sandwiches of liquid crystals (e.g. nematic liquid crystals) on two sheets of glass each having electrodes. The structure is inserted, and when a predetermined voltage or more is applied, the reflectance of the liquid crystal is changed to indicate that the display can be read. However, the present invention is not limited thereto, and light emitting devices such as light emitting diodes are also included. In the super display electronic circuit connected as described above, when the output of the shift register 22, that is, the signal of the output lead lines 22a to 22f is ["0"], the super display element 25 is divided into minutes. It is divided by the period 11, enters the OR gate 23a via the output lead line C, and a 1 second pulse ["1"] is applied through the driving device 20, so that it blinks once every 1 second. Repeatedly display 10 seconds from 0 to 9 seconds. When 10 seconds have elapsed, a 10 second signal ["10"] is generated by the divider 12, and its output is applied to the shift register 22 via the output lead line A, and then the output lead line 22a of the shift register. The ore gate 23a and the AND gate 24a enter through the gate. As a result, the output of the OR gate 23a maintains the state of the signal ["1"], and the super display element 41 changes from flashing to lighting. Since the OR gate 23b and the AND gate 24a are in the ON state, the flash display is transferred to the super display element 42 by the one second signal pulse ["1"] of the output lead line C. Thereafter, by the same operation, the super display elements 43, 44,... … 10 seconds flashes in turn, and keeps lighting when each device finishes flashing 10 seconds. When the signal ["1"] enters the output lead line 22f of the final stage of the shift register 22, the signals are reset at the same time. Each of the display elements 42 to 46 is turned off, and the first display element ( 41) The flashing starts. Subsequently, the same operation is repeated, and each of the superdisplay elements 41 to 46 flickers every 10 seconds, and then shifts while maintaining lighting after flashing. The above display state is shown in FIG. In Fig. 4, in the case of 35 seconds, the superdisplay elements 41-43 are kept lit, the superdisplay element 44 flashes six times, and the remaining superdisplay elements 45, 46 ) Is off.

Then, the display device 46 can see the display for 60 seconds by ending the 10 blinks. In Fig. 4, the table flashes, the □ table lights up, and the-table lights out.

Next, another embodiment shown in FIGS. 5 and 6 will be described. In this embodiment, the display element shifts from the off state to the lit state after 10 seconds has elapsed, and from the lit state to flashing state after 10 seconds has elapsed. To keep it. In this case, the decoder 17 is a combination of nine end gates 25a-25i, five or gates 26a-26e, and five inverters 27a-27e, as in the fifth diagram. It was comprised by connection and the display form was shown in FIG.

Next, Figs. 7 to 14 show another embodiment of the display form by arrangement of blinking and lighting. In FIG. 7, the decoder 17 is composed of five or gates 27a and 27e, and the output lead of the shift register 22 is connected to one input terminal of the orgates 27a and 27e. 22a)-(22e) are correspondingly connected to each other, and a common lead line C for applying a 1 second pulse from the divider 11 is connected to the other input terminal of the angle gates 27a-27e. The output lead lines of the gates 27a-27e are connected to the super display elements 41-45 via the driving device 20, and a 1 second pulse is applied to the rightmost display element 46. The common lead line C to be applied is connected via the drive device 20. With this connection configuration, a display mode similar to that of the eighth degree can be obtained. In FIG. 9, the OR gates 27a-27e shown in FIG. 7 are replaced with AND gates 28a-28e, and the output lead line C of the divider 11 is an inverter ( It is connected to the input terminal of each NAND gate in common via 29). In the case of the display form in this case, as shown in the tenth diagram, each display element is sequentially turned to blink in the lit state, and the time is integratedly displayed by the so-called blinking.

11 to 14 use the ring counter 30 instead of the shift register 22. In FIG. 11, the decoder 17 has 6 bits at the input terminals of the six NAND gates 31a to 32f. The common lead wire C, which applies the 1 second pulse ["1"] of the output lead wires 30a-30f of the ring counter 31, is connected, and when all the display elements are in the lit state, they blink every 10 seconds in turn. The display form is shown in FIG. 12 as to shift from the display element 41 to 46. FIG. In FIG. 13, the ordinal gates 32a and 32f are used instead of the NAND gates to display the 14th degree.

Next, Figs. 15-22 show another embodiment in which the display is switched on and off. 15 to 18 show an example in which the 6-bit shift register 22 is used for the divider 13.

In Fig. 15, the output leads 22a-22e of the shift register 22 are connected to the display elements 42-46 except for the first display element 41 via the driving device 20. The first display element 41 is provided with the signal ["1"]. This display mode is integrated in order from light off to light like the sixteenth degree.

In the embodiment of Fig. 17, the output lead lines 22a-22e of the register are configured to apply signals to the respective display elements via the inverters 33a-33e. As shown in Fig. 18, the display in Fig. 16 is the opposite. 19 to 22 are circuits and display diagrams in the case where the frequency divider 13 uses the 6-bit ring counter 30. In FIG. 19, the output lead lines 30a-30f of the 6-bit ring counter 30 are connected to the display elements 41-46 via the driving device 20, and Similarly, the display is arranged with the lights turned on and off, and in the case of FIG. 21, the 20th degree is made to be the opposite display like the 22nd degree through the indium 34a-34f.

23 to 30 show another embodiment of the display means by arrangement of blinking and extinguished lights. 23 to 26 show a case where the 6-bit shift transistor 22 is used instead of the divider 13, and FIGS. 27 to 30 show an example where the 6-bit ring counter 30 is used. In these figures, (35a) to (35f) represent gates, and (36a) to (36f) represent knock gates.

As described above, according to the present invention, there are a plurality of display elements arranged, and one display element is used to sequentially display the time by arranging the other display elements in order of flashing, lighting, and extinguishing. It is not only possible to display visually and interestingly, but also to check the operation of the clock, and to display one of the other display elements in turn by flashing, turning on or turning off the light on the other display element at a predetermined time interval. By the unit of seconds, it is possible to know the number of seconds, and it is not as complicated as displaying the number by number, and it is possible to obtain a great effect even by using a liquid crystal with poor responsiveness.

Claims (1)

It is composed of a plurality of display elements, and each time a relatively short time elapses, the plurality of display elements are sequentially changed to at least one display state so that the display means for informing the time elapsed and the predetermined time elapsed. A display control means for flashing, turning on, or turning off at least one display state among a plurality of display elements sequentially posted each time is provided. An electronic clock characterized by displaying at least one of the display elements sequentially posted each time by changing to one of the display states, such as flashing light and off.