KR800000931B1 - Gating circuit for a video driver including a clamping circuit - Google Patents

Abstract

A video driver cct. device for controlling the operation of a kinescope(24) is composed of amplifying means(44a) for coupling the video signals to the image reproducing device, clamping means(48a, 54a) coupled to the amplifying means for periodically clamping a predetd. cct. point of the amplifying means to a reference voltage, means for providing a control signal during the horizontal retrace intervals and gating means(62) responsive to the control signal for coupling the reference voltage from the means for providing a direct voltage to the clamping means during the horizontal retrace intervals.

Description

Gating circuit for kinesco off driver with clamping circuit

Figures are some schematic diagrams and some schematic diagrams showing a general circuit arrangement of a color television receiver using a device constructed in accordance with the present invention.

The present invention relates to an apparatus for controlling the operation of an image reproducing apparatus, and more particularly to a video driver circuit for controlling the operation of kinesco off.

Television signal processing systems, such as television receivers, generally include kinesco-off for playing back images in response to video signals. One or more electron beams generated by the kinescooff are deflected to generate a horizontal sweepline on the screen of the kinescooff that is modulated according to the video signal during the “horizontal sweepline” period. When the electron beam reaches the end of the horizontal line, it quickly deflects to the beginning of the next horizontal line during the “horizontal retracement” period. The electron beam is also deflected vertically at a slow rate during the "vertical edge" period until the beam is scanned line by line to the bottom of the screen. When the beam reaches the bottom of the screen, it is deflected to the top of the screen during the "vertical retracement" period. Since the vertical retrace period is longer than the horizontal sweep and retrace periods, the electron beam is deflected horizontally several times during the vertical retrace period. As a result, a chaotic zigzag pattern is created as long as the kinesco off is inactive or “erased” during the horizontal sweep line portion of the vertical blank.

Various kinesco off drivers are known for controlling kinesco off in response to video signals. US Patent No. 504,357, entitled “Circuit for Maintaining Operation Point Stability of Amplifiers,” filed by Donald Henry Walls, describes an amplifier that synthesizes a brightness signal and a chrominance signal to drive a carnal kinescooff. Is explained. The amplifier includes a clamping circuit that operates during the horizontal return period to stabilize the amplifier's operating point.

Although the horizontal and vertical erasing pulses, each having a period corresponding to the horizontal and vertical retrace periods, are inserted into the brightness signal coupled to the kinesco off driver, the erase pulses do not operate the kinesco off to generate an electron beam. To become incomplete under certain conditions, such as the appearance of noise or other undesirable signals. Such noise may be in the form of the undesirable zig-zag sweep lines described above generated during the horizontal sweep line portion of the vertical retrace period.

According to the present invention, a gating circuit that can be used in connection with a kinesco-off driver of the type described in the above-mentioned U.S. patent application operates the clamping portion of the driver during each horizontal retrace period and the horizontal of each vertical retrace period. A special erase signal is provided to couple the driver so that the kinesco off does not operate to generate an electron beam during the sweep line portion. The gating circuit is arranged to decouple the special cancellation signal from the driver during the horizontal retrace period so that the special cancellation signal does not interfere with the clamping operation of the driver.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. A typical arrangement of color television receivers embodying the present invention is to produce a composite video signal containing chromaticity, lightness, voice and synchronization by means of a suitable intermediate frequency circuit (not shown) and detection circuit (not shown). RF) video processing stage 12 responsive to the television signal. The video signal processing stage 12 is coupled to the chroma channel 14 including the chroma processing stage 16 and the brightness channel 18 including the brightness processing stage 20.

Chromaticity processing stage 16 includes a chromaticity demodulator (not shown) to derive a color difference signal representing, for example, R-Y, B-Y and G-Y information. The color difference signals are applied to the kinesco off driver 22 comprising only 44a, 44b and 44c. The color difference signals are matched with the output signal -Y of the brightness processing circuit 20, for example, to produce a color signal representing the R, B and G information of the appropriate polarity. The color signals are coupled to the respective cathodes 38a, 38b, and 38c of kinescooff 24.

The brightness processing stage 20 works to amplify and process the video signal to produce the brightness signal -Y, resulting in the appearance of relatively weak undesirable signal portions such as the chroma and audio signal portions on the brightness channel 18.

The contrast control stage 26 is coupled to the brightness processing stage 20 to control the amplitude of the brightness signal. The brightness control stage 28 is coupled to the brightness processing stage 20 to control the DC component of the brightness signal.

The output of video processing stage 12 is coupled to a synchronous separator 30 that separates horizontal and vertical sync pulses from the composite video signal. The sync pulse is coupled to the horizontal deflection circuit 32 and the vertical deflection circuit 34. Deflection circuits 32 and 34 are coupled to kinesco off 24 and high voltage stage 36 to control the deflection of one or more electron beams generated by kinesco off 24 in the manner described above.

The deflection circuits 32 and 34 generate horizontal and vertical cancellation signals each having a period corresponding to the horizontal and vertical retrace periods. The erase signal is coupled to the brightness processing stage 20 which is combined with the brightness signal to form a brightness signal -Y including a forward horizontal erase pulse. Since there are as many as 250 horizontal erase pulses between the vertical erase pulses, only horizontal erase pulses are shown in waveform-Y. The vertical erase pulse has a long duration but has the same amplitude as the horizontal erase pulse.

As shown as an example in the figure, the horizontal feedback signal generated by the horizontal deflection circuit 32 during each horizontal retrace period is coupled to the gating circuit 2 to control its operation. The period of the negative part of the feedback pulse waveform is synchronized in time with the horizontal erase pulse. The gating circuit 62 is coupled to stages 44a, 44b and 44c of the kinesco off driver 22 to control its operation as described below.

Kinescooff 24 may be, for example, multiple gun kinescooff, such as a delta gun, a shadow or aperture mask, or a precision in-line kinescooff or the like. Kinescooff 24 includes each different phosphor gun, such as, for example, red, green and blue. As shown, each gun includes cathodes 38a, 38b and 38c, control grids 40a, 40b and 40c and screen grids 42a, 42b and 42c.

The bias control voltage is coupled to control the control grids 40a, 40b and 40c from the bias control stage 41 and the screen control voltage is coupled from the screen control stage 43 to the screen grids 42a, 42b and 42c to adjust the operating conditions of the respective guns.

The kinesco off driver 22 includes steps 44a, 44b and 44c to drive each gun of kinesco off 24 respectively. Since the columns are similar, only 44a will be described in detail. Note that 44a includes NPN transistor 46a and NPN transistor 48a. There is also provided a PNP brightness amplifier 50 that is commonly coupled to three stages 44a, 44b and 44c.

Regarding only 44a, transistors 46a and 50 have emitter electrodes coupled together through variable drive control resistor 52a. The base of the resonator 46a is coupled to the R-Y signal output of the chromaticity stage 16 via a capacitor 54a. The base of transistor 50 is DC coupled to the output of brightness processing stage 20. The collector of transistor 46a is coupled to positive operating voltage source Bt through resistor 56a. The emitter of transistor 46a is coupled to ground through a variable bias control resistor 58a. The collector of transistor 46a is directly coupled to the cathode 38a of the red (R) gun of kinesco off 24.

Transistors 46a and 50 interoperate to synthesize an R-Y chrominance signal and a brightness signal (-Y) to produce a red signal at the collector of transistor 46a. Transistor 46a operates as a common emitter mode to amplify the R-Y chrominance signal. By emitter coupling of transistors 46a and 50, transistor 46a operates in a common base mode to amplify the brightness signal (-Y). The R, b and G signals generated at the collectors of transistors 46a, 46b and 46c are coupled to kinescooff cathodes 38a, 38b and 38c, respectively.

The NPN transistor 48a is arranged in a feedback relationship with the NPN transistor 46a, and this combination clamps the circuit to maintain the operating point of only 44a independent of the DC state of the RY output of chromaticity 16 and the base-emitter voltage of transistor 46a. Coupled to resistor 60a and capacitor 54a to form a resistor.

The emitter of transistor 48a is coupled to the emitter of PNP transistor 64 of the gating circuit 62. The gating circuit 62 acts to apply a reference voltage to the emitter of transistor 48a during each horizontal retrace period to be in a conductive state. When transistor 48a is conducting, this causes the emitter of transistor 46a to be independent of the DC state of the RY output of chromaticity stage 16 and to the temperature induced variation of the base emitter voltage of transistor 46 (base-emitter voltage of transistor 48a). Interoperates with transistor 46a and capacitor 54a to lock to + reference voltage).

Detailed description of operation of 44a is described in the above-mentioned United States Patent Application. In short, the interaction of transistors 48a and 46a during the horizontal retrace period can be understood by considering their arrangement as a negative feedback arrangement. Thus, for example, when the emitter voltage of transistor 46a decreases due to the increase in voltage across the base-emitter junction of transistor 46a, the collector voltage of transistor 48a increases. As a result, the emitter voltage of transistor 46a increases.

Since the operating point of 44a is determined by the voltage generated at the emitter of transistor 46a, this operating point is maintained irrespective of the base-emitter voltage of transistor 46a and the DC state of the R-Y output of chromaticity processing stage 16. Similarly, the operating point of stage 44b is maintained regardless of the DC state of the BY output of chromaticity processing stage 16 and the base-emitter voltage of transistor 46b, and the operating point of stage 44c is the base-emitter voltage and chromaticity processing stage of transistor 46c. It remains independent of the 16 GY output DC status.

The gating circuit 62 also acts to combine a signal called the “special erase signal” of kinesco off 24 to be cut off during the horizontal sweep line portion of each vertical retrace period. In this way, there is no chaotic jig-zag sweep line formed due to the horizontal deflection of the electron beam which may be generated by kinesco off 24.

Gating circuit 62 includes a PNP transistor 64 having an emitter coupled to emitters of transistors 48a, 48b and 48c and a collector connected to ground. The horizontal feedback voltage waveform generated by the horizontal deflection circuit 32 (as shown in the figure) is coupled to the base of transistor 64 via terminal 74, resistor 72, resistor 70 and diode 66.

Diode 68 is coupled between the contacts of resistors 70 and 72 and ground. Diode 68 serves to prevent the occurrence of excess voltage at the contacts of resistors 70 and 72. Diode 66 acts to prevent reverse breakdown of the base-emitter junction of transistor 64. Resistor 76 is coupled between the constant voltage source (C +) and the junction of resistor 70 and diode 66.

The series coupling of resistor 86, diode 80 and resistor 82 is coupled between the constant voltage source (D +) and the common junction of resistors 52a, 52b and 52c. The emitter of transistor 64 is coupled to the anode of diode 80.

The general arrangement shown in Figure 1 is, for example, the color television technical data for a CTC-68 type receiver published by the United States, Indianapolis, Indianapolis City, R.C.A. Suitable for use with color television receivers of the type shown in Volume 8.

Before describing the operation of the gating circuit 62, the transistors 46a, 46b and 46c are allowed to conduct slightly during the generation of the horizontal erase pulse contained in the brightness signal -Y due to the connection of the resistors 58a, 58b and 58c and the bias component associated therewith. You must first know that it is biased This is the feedback interaction of transistors 48a, 48b and 48c and transistors 46a, 46b and 46c to fix the respective emitters of transistors 46a, 46b and 46c to the reference voltage provided by gating circuit 62 during the horizontal retrace period. It is desirable to enable this. However, the continuous conduction of transistors 46a, 46b and 46c results in undesirable signals, such as noise, in which the viewable sweep line pattern is coupled to the respective bases of transistors 46a, 46b and 46c during the horizontal sweep line portion of the vertical retrace period. The problem arises as stated in the response.

It should be noted that undesirable lines are formed in response to undesirable signals coupled to the respective bases of transistors 46a, 46b and 46c during the horizontal retrace period. The formation of these horizontal retraces is prevented in many ways. One such method is to provide an apparatus for coupling incidental erase pulses to the grids of kinesco off 24 such that it is cut off during the horizontal retrace period. Such a device may, for example, interoperate with a bias control stage 41 or a screen control stage 43.

The problem with the formation of a zig-zag sweep line pattern is that the calibration television signal processing system is further exacerbated when signals such as the vertical period test signal (VITS) currently proposed are included in the composite video signal and coupled to chromatic channel 14. It should be noted that.

When the gating circuit 62 is in operation, the horizontal feedback waveform shown in the figure is coupled to terminal 74. Therefore, a constant voltage (e.g., + 20V) is coupled to terminal 74 during each horizontal sweep line period. As a result, diode 68 is reverse biased and the constant voltage determined by the magnitude of the feedback signal and the fraction of C + and the values of resistors 70,72 and 76 is generated at the cathode of diode 66. These components are selected to keep diode 66 and transistor 64 relatively non-conductive. At the same time, the constant voltage determined by the voltage distribution of resistor 86 in series with the impedance formed by resistors 82,52a, 52b, 52c, 58a, 58b, and 58c and the impedance between the emitter and collector of transistor 50 causes the diode 80 to conduct. Occurs at the anode. By conduction of diode 80, the current from power source D + is coupled to the emitters of transistors 46a, 46b and 46c. The amount of current coupled to the emitters of transistors 46a, 46b and 46c is mainly determined by the conduction of the transistor which allocates the current supplied through diode 80.

The conduction of the transistor 50 is controlled in response to the brightness signal -Y. The portion of the signal in the direction of the desired pulse, ie in the black direction, conducts the transistor 50 less than the signal in the opposite direction, ie in the white direction.

In the amplitude range of -Y, which corresponds to a signal between white and black (black level is just below the maximum amplitude of the desired pulse), a slight current from power supply D + is relatively bypassed by the conductive transistor 50 to ground To emitters 46a, 46b, 46c. However, when the amplitude of the brightness signal exceeds the black level, a relatively large portion of the current from the power supply is coupled to the emitters of transistors 46a, 46b and 46c, with only a small fraction of the current from the power supply D + being non-conductive and It is bypassed to ground through cutoff transistor 50. As a result, there is a tendency to increase the emitter voltages of transistors 46a, 46b and 46c and these transistors are cut off or close to this. The collector voltages of transistors 46a, 46b and 46c attempt to further cut off the electron beam generated by the three guns of kinesco off 24.

Therefore, it can be said that the gating circuit 62 provides a "special black drive" capability during the minor ship period. That is, during the horizontal sweep line period corresponding to the period between the horizontal erase pulses, when the amplitude of the brightness signal-Y exceeds the black level, the current coupled to the emitter of the transistor 50 through the diode 80 causes the transistor 50 to be cut off. This enables the voltage generated at the collectors of transistors 46a, 46b and 46c to rise even higher than previously generated. During the horizontal sweep line portion of the vertical retrace period, the vertical erase pulses cause transistor 50 to be cut off. A current is then supplied through diode 80 to drive transistors 46a, 46b and 46c to cut off them so that irrelevant jig-zag sweep line patterns are not formed. The latter feature of the gating circuit 62 is called the "special erase" ability.

During each horizontal retrace period, the negative portion of the horizontal feedback signal is generated at terminal 74. Diode 68 is conducting and a bypass pulse is generated at the cathode of diode 68 where negative excursions are limited to ground potential below the voltage generated between the anode and cathode of diode 68. As a result, a bypass pulse whose amplitude is determined by the voltage distribution of resistors 70 and 76 and C + is generated at the cathode of diode 66 to conduct transistor 64. Transistor 64 acts as an emitter follower and is applied to the emitters of transistors 48a, 48b and 48c with the voltage generated at the cathode of diode 66 (and the voltage generated at the anode and cathode of diode 66 and the emitter and base of transistor 64). Combine them. Transistors 48a, 48b and 48c are conductive and emitters of transistors 46a, 46b and 47c are actually independent of the DC state of the RY, BY and GY outputs of chromaticity stage 16 and the base-emitter voltage of transistors 46a, 46b and 46c. They interact with the conductive transistors 46a, 46b and 46c, respectively, in a feedback manner to fix them to a reference voltage.

The operation of transistors 48a, 48b and 48c causes the voltage generated at the emitter of transistor 64 during each horizontal sweep line period to bias the diode 80 again, leaving it non-conductive. As a result, the current coupled to the emitters of transistors 46a, 46b and 46c from the D + source during the sweep line period is decoupled, so that the clamping action of 44a, 44b and 44c cannot be prevented. Representative values of the various components of the receiver device are shown in the figures. The values of resistors 70,72,76,82 and 86 cause the diodes 66 and 68 and transistors 64,48a, 48b and 48c to be relatively non-conductive and the diode 80 to be relatively conductive during each horizontal sweep line period. And select transistors 64, 48a, 48b and 48c and diodes 66 and 68 to be relatively conductive and diodes 80 to be relatively non-conductive during each horizontal retrace period. Although the present invention has been described with respect to the specific embodiments shown in the drawings, it is possible to modify and modify the embodiments within the context of the invention.

Claims (1)

A video signal source comprising a vertical erase pulse, a horizontal erase pulse between the vertical erase pulses, and an image information signal between the horizontal erase pulses, and an apparatus for generating an electronic current in response to the video signal. And a device for reproducing an image from the video signal, a scanning device for causing the current to sweep the image area of the device in a predetermined pattern comprising a horizontal sweep line retrace period, a vertical sweep line and a retrace period; A television processing system comprising an amplifying device 44a for coupling a signal to the image reproducing apparatus, in particular, the amplifying apparatus for periodically fixing a predetermined circuit operating point of the amplifying apparatus to a reference voltage in response to a control signal. Clamping devices (48a, 54a) coupled to the electronic current during the respective vertical retrace periods. A voltage source device (D +, 86, 80, 82) which is coupled to an amplifying device for supplying a special erasing signal to said image reproducing device and which does not operate to couple said special erasing signal to said device during said horizontal retrace period. A gating device (62) for coupling said control signal to said clamping device during said horizontal retrace period.

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