KR790001694B1 - Monostable multivibrator circuit - Google Patents

Abstract

A cct. was simplified by using a 4-terminal semiccnductor element comprising ordinary 3-terminal semiconductor element added a 4th electrode, capacitively coupled to a portion of 1st region(1). Bias current was applied to the 2nd electrode(5b)(base) and fixed voltage was applied through a resistor(15) to the 4th electrode(gate) and capacitor(14) was connected between the 3rd and the 4th electrode of the semiconductor element and trigger signals were applied to the base(t1), thus monostable output was obtained from the collector(t2).

Description

Monostable circuit

1 and 2 are cross-sectional views showing two embodiments of a three-terminal semiconductor device in accordance with the description of one embodiment of a four-terminal semiconductor device used in the present invention.

3 is a cross-sectional view showing an embodiment of a four-terminal semiconductor device used in the present invention.

4 is a characteristic measurement circuit diagram of the 4-terminal semiconductor device of FIG.

5 is a characteristic curve diagram of the four-terminal semiconductor device of FIG.

6 is a circuit diagram showing one embodiment of the present invention.

7 is a characteristic curve diagram according to the operation description thereof.

8 is a waveform diagram according to the operation description thereof.

According to the present invention, a monostable circuit, which is conventionally constructed using two agricultural devices, is simply configured as a single active device using a new semiconductor device.

Hereinafter, an embodiment of a four-terminal semiconductor device used in the present invention will be described. However, this bipolar transistor has a higher current amplification factor, better saturation characteristics, lower noise, and more bidirectionality than a conventional bipolar transistor. Since the transistor is configured by providing a gate in a three-terminal semiconductor element of a special structure proposed by the present applicant, the three-terminal semiconductor element will be described first, comparing with a conventional bipolar transistor.

H _FE (emitter ground current amplification factor), which is used as one of the parameters for evaluating the characteristics of a bipolar transistor,

Is given by This α is

Is given by Where α * is the collector amplification factor, β is the base transfer efficiency, and γ is the emitter injection efficiency. Now, considering the emitter injection efficiency γ of NPN transistor, in this case γ is

Is given by Where J _n is the current density by electrons injected from the emitter to the base, and J _p is the current density by holes injected from the base to the emitter.

Where J _n and J _p are each

Because of

Where L _n is the diffusion distance of minority carriers in the base

L _p : Diffusion distance of minority carriers in the emitter

D _n : Diffusion distance of minority carriers in base

D _p : Diffusion distance of minority carriers in the emitter

n _p : minority carrier concentration at equilibrium in the base

P _n : minority carrier concentration at equilibrium in the emitter

V: applied voltage to emitter junction

to be.

은,

로 치환할 수 있고, 또 L_n은 베이스폭 W로 제한하여, L_n=W로 되므로And if the impurity concentration of the emitter is N _D and the impurity concentration of the base is N _A

silver,

And L _n is limited to the base width W so that L _n = W.

Becomes The diffusion constant is a function of carrier mobility and temperature, which is considered to be nearly constant here.

As is evident in each of the above-described equations, it is preferable that δ is smaller to raise the h _FE in the bipolar transistor.

Therefore, in the conventional general bipolar transistor, the impurity concentration N _D of the emitter is sufficiently large to reduce δ.

However, when the impurity concentration of the emitter is sufficiently large, for example, about 10 ¹⁹ atoms / cm ³ or more, lattice defects, dislocations, and the like are generated, and crystal perfection can be obtained. High, shortening the life time τ _p of the minority carrier injected from the base

The diffusion distance L _p of this small number of carriers (holes) becomes short, and as shown in Eq. (7), δ cannot be loaded very much and the injection efficiency γ does not increase to some extent.

Therefore, a three-terminal semiconductor device having a special configuration has been proposed to avoid such drawbacks. An example of this semiconductor element will be described with reference to FIG.

An example of the illustration is a case of configuring an NPN transistor. In this case, the semiconductor substrate S has a first conductivity type, that is, an emitter region 1, which is an N-type high resistivity first semiconductor region, and a second conductive type, i.e., P-type high, disposed adjacent thereto. A base region 2, which is a resistive second semiconductor region, and a collector region 3, which is a high resistivity third semiconductor region, such as a first conductive type, that is, an N-type, disposed adjacent thereto are provided. A first PN junction, that is an emitter junction J _e, is formed between the first and second regions 1 and 2, and a second between the second and third regions 2 and 3. A PN junction, that is, a collector junction J _c, is formed. And the first region (1) in the joint that the distance between the junction J _e opposite to J _e of the diffusion length of minority carriers (step) that is in the area of the second (2) injected into the region 1 of the first L _p In a smaller position, a potential barrier 7 of at least this minority carrier energy and at least thermal energy is provided.

For a first degree is the case of installing the high impurity concentration region (1a) of a conductivity type such as this in the area of the (1) to form a L · J _H H bond in the region (1).

The first, second and third electrodes, namely the emitter, the base and the collector, are resistively on the high concentration region 1a, the second region 2 and the third region 3 of the first region, respectively. The inter electrodes 5e, 5b and 5c are deposited and the first, second and third terminals, i.e., emitter, base and collector terminals E, B and C are derived, respectively.

The portion except for the high concentration region 1a of the first region 1 selects a sufficiently low concentration whose impurity concentration is about 10 ¹⁵ atoms / cm ³ . The second region 2 is selected to about 10 ¹⁵ to 10 ¹⁷ atoms / cm ³ . The third region 3 is also selected to the same extent as the low concentration portion of the first region 1, for example, at about 10 ¹⁵ atoms / cm ³ .

As described above, the impurity concentration of at least the portions where junctions J _e and J _c of the regions 1, 2 and 3 are formed is low and excellent in crystallinity. The diffusion distance L _p of the minority carriers becomes large.

(3a) is a low-resistance region of high impurity concentration provided at a distance from the junction J _c in the third region 3, and (6) is an insulating layer such as SiO ₂ formed on the surface of the substrate S.

In this configuration, a forward bias is applied to the emitter junction J _e to each terminal E, B, and C, and a voltage giving a reverse bias to the collector junction J _c is applied. This results in transistor operation. In this case, holes injected from the base region, that is, the second region 2, into the emitter region, that is, the first region 1, have low impurity concentrations in the first region 1, good crystallinity, and the like. As a result, the life thereof is long and the diffusion distance L _p of the hole in the first region 1 becomes long. Therefore, the emitter injection efficiency γ can be increased, as is apparent from equations (6) and (3). However reaches the diffusion distance is also the substrate surface by increasing the L _p is the actual phase the injection hole, if there is anything, such as discarding by surface recombination, can not substantially lengthen the diffusion length L _p. However, in the above-described configuration, since the dislocation barrier 7 is disposed to have an interval smaller than the diffusion distance L _p to face the emitter junction J _e , the surface recombination becomes small and the diffusion distance L _p is considered to be sufficiently large.

In this way, the potential barrier 7 is provided, which has the effect of reducing the current component J _p of the holes injected into the first region 1 in the second region 2. In other words, in the L · J _H H bond doctor difference in Fermi level, or encapsulated in the region (1) of claim 1 occurs (封入buildin) total length. Since this acts in the reverse direction to the hole diffusion of minority carriers, if this level is sufficiently large, the diffusion current due to the concentration gradient of holes in this L-H junction J _H and the drift current due to the enclosed electric field cancel each other. It is effective to reduce the hole current J _p injected through the low concentration emitter at the base. By this effect, the ratio of the electron current reaching the collector among the current components passing through the emitter junction becomes high, and the value of the emitter injection efficiency γ becomes large and h h _FE becomes high, as is apparent from Equation (3).

This level difference (potential barrier height) must be at least above the hole energy, at least above the thermal energy. The thermal energy is almost kT (where k is Boltzmann's constant and T is temperature), but the above-described level difference is preferably 0.1 eV or more.

In the transition region of this dislocation, the hole diffusion distance should not stop within the region.

In other words, it is required that the hole diffusion distance L _p is larger than the width of the transition region. In the case of the L-H junction like the first diagram, a potential barrier of 0.2 eV can be provided by appropriately setting the amount of impurities and the gradient in the high impurity concentration region 1a.

FIG. 2 is another example of a three-terminal semiconductor device having a special configuration. The first region 1 is provided with a region 1a of high impurity concentration to form a potential barrier 7 and the first region ( 1) toward the first joint _e and J against to the case of installing the additional area (4) of P type for forming a PN junction J _s. In this case, in terms of the minority carrier selected to be smaller than the distance L _p in the PN junction region and the J _s (1) of a first distance between the junction J _e of the even region (1a). That is, in this case, the process injected into the first region 1 has a large diffusion distance as described above, so that it reaches the additional region 4 effectively and is absorbed by the P-type additional region 4. When the additional region 4 is electrically floating, the potential increases as the hole increases, and the PN junction J _s formed between the region 4 and the first region 1 is It is forward biased to near light voltage and holes are reinjected into the first region 1. As a result, the concentration of holes in the vicinity of the additional region 4 of the first region 1 increases.

Therefore, the concentration distribution of the holes between the junctions J _e and J _s of the first region 1 becomes uniform, the gradient becomes smooth, and the diffusion current J _p from the second region 2 to the first region 1 is It becomes small.

In the example shown in FIG. 2, the additional type 4 of the same conductivity type as the second area 2 is provided separately from the second area 2, but in some cases, the area 4 May be continuously extended in the region (2).

In the above description, the first, second, and third areas 1, 2, and 3 are operated as emitters, bases, and collectors, respectively. Since the first and third regions 1 and 3 on both sides of (2) have the same low impurity concentration as each other and have a symmetrical structure in the region 2, the first second And the third region (1) (2) and (3) as the reverse transistor for operating as the collector, the base and the emitter, respectively. In other words, this three-terminal semiconductor device is a transistor that operates in both forward and reverse directions and has excellent electrical symmetry.

In this case, in order to obtain better h _FE characteristic copper with respect to the reverse transistor, in order to avoid surface recombination on the main side surface of the substrate S, the low resistance region 3a of the third region 3 is used as the main substrate S substrate. Install on the side. The distance between the area 3a and the second area 2 is shorter than the diffusion distance of the minority carriers injected into the third area 3 in each part, and between the area 3 and the area 3a, A potential barrier above the energy of the minority carriers is provided.

The advantages of this specially constructed three-terminal semiconductor device are listed below.

(i) The current amplification factor h _FE is high and can be set to 3,000 or more.

(ii) The dispersion degree of h _FE is small. That is, in the conventional general bipolar transistor, the concentration of the emitter region is sufficiently increased to increase the emitter injection efficiency. In other words, since it depends on the concentration difference in the vicinity of the junction between the emitter region and the base region, the setting of the concentration of both regions should be correlated.

On the other hand, the three-terminal semiconductor element of this special configuration forms an electric potential barrier in the first region 1 as opposed to the first junction J _e , thereby suppressing the current component of the minority carriers injected into the first region, In order to increase the injection efficiency, the first and second regions 1 and 2 indicate that the first region 1 can be selected at a relatively low concentration. The distribution and the like can be designed without the degree of dispersion, and therefore the degree of dispersion of h _FE is also reduced.

(iii) In addition, the h _FE is high even at a low current because the effect of surface recombination is avoided.

잡음을 작게 할수가 있다. 더우기 파열(burst) 잡음과

잡음은 h_FE가 높아도 감소된다. 또 베이스 분포저항 r_bb'를 적게하면 신호원 임피던스가 낮은 경우에도 잡음은 적어진다.(iv) less noise. That is the second of the first and second engagement J _e and J major part of _c is determined less defects because each forming a P-type and N-type region of low impurity concentration, for example, the second region (2) of the back By increasing the impurity concentration near the electrode 5b, the lateral current along the substrate surface of the inter-emitter base current as a transistor can be reduced. therefore

Noise can be reduced. Moreover, burst noise

Noise is reduced even at high h _FE . In addition, if the base distribution resistance r _bb 'is reduced, the noise is reduced even when the signal source impedance is low.

(v) In addition, h _FE has good temperature characteristics.

(vi) It is excellent in symmetry as a positive and reverse transistor.

(vii) the first and second junction J _e and the impurity concentration in the vicinity of J _c is lower forward and reverse BV _BEO as a bi-directional transistor (open collector, the base-emitter breakdown voltage) is high.

(viii) When used as a power-transistor, the intensity is high because the emission is uniformed by the distribution resistance in the emitter.

(ix) Moreover, saturation characteristics are good.

(x) The equivalent resistance of the base decreases when the additional area 4 for injection or re-injection is provided. In addition, although each of the above-described examples is of the NPN type, of course, the PNP type is also possible as in the conventional general bipolar transistor.

However, a four-terminal semiconductor element constructed by providing a semiconductor control region in the first semiconductor region of the three-terminal semiconductor element of the special configuration described above and providing a control electrode (gate) associated therewith is controlled at the control electrode (gate). The current amplification rate can be changed by applying a voltage.

In the example of the three-terminal semiconductor device shown in FIG. 2, the additional region 4 itself is used as the semiconductor control region, and the control electrode (gate) is derived therefrom to form a four-terminal semiconductor device. Detailed description will be omitted.

Next, a four-terminal semiconductor element suitable for use in the present invention will be described with reference to FIG. 3, which is a part of the first semiconductor region (emitter region) of the three-terminal semiconductor element of FIG. And a control electrode (gate) coupled capacitively to form a four-terminal semiconductor device.

In FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals and redundant description thereof will be omitted.

In FIG. 3, the first semiconductor region (the insulating layer (gate insulating layer) 8) of a predetermined thickness (for example, several hundred microseconds) is opposed to a part of the emitter region 1 in FIG. The insulating layer 6 is formed of, for example, SiO ₂ , but corresponds to the gate insulating layer of the MOS field effect transistor, and a control electrode (gate) 5g having a predetermined area is formed thereon from a metal layer such as Al. The deposition is performed, and the gate terminal G as the fourth terminal is derived from the control electrode 5g.

The portion 9 corresponding to the control electrode 5g on the surface of the first semiconductor region 91 is a semiconductor control region.

When the gate bias voltage is applied between the gate emitters of the four-terminal semiconductor device, that is, between the gate terminal G and the emitter terminal E, the current amplification factor, that is, the emitter ground current amplification factor h _FE is lowered according to the value. It forms and changes approximately axially symmetrical curves with respect to the iron minima. That is, in the example of FIG. 3, when a negative bias voltage is applied to the emitter terminal E, the first semiconductor region (emitter region) goes in the positive direction as the range on the positive side from the predetermined threshold voltage of the bias voltage. In part (1), that is, in the control region 9, an accumulation layer CG having the same function as the L-H junction J _H as the potential barrier 7 in FIG. 1 is formed. As a result, the current density J _p due to the hole of the diffusion current from the second semiconductor region (base region) 2 to the first semiconductor region (emitter region) 1 decreases, and as a result, h _FE increases. In addition, in the range on the negative side from the predetermined threshold voltage of the bias voltage, a part of the first semiconductor region (emitter region) 1, that is, the control region 9, is inverted in the negative direction as it goes in the negative direction. As in the case where the additional region 4 in FIG. 2 is electrically floating, holes are re-injected into the first semiconductor region (emitter region) 1 in the inversion layer IN, whereby the second semiconductor region ( The current density J _p due to holes of the diffusion current from the base region 2 to the first semiconductor region (emitter region) 1 decreases, and as a result, h _FE increases.

는 이 4단자 반도체소자를 표시하고, 이 기호는 종래의 바이폴러 트랜지스터의 기호에 그 에미터와 평행하게 짧은 선을 추가하여 이것을 게이트로서 나타낸다. 제 4 도의 회로에서는 이 4단자 반도체소자

를 에미터 접지형으로 한 경우이고, R_L은 그 콜렉터부하저항, V_CC는 콜렉터전원전압, I_C는 콜렉터 전류, I_B는 베이스 전류(정전류), V_GE는 게이트 에미터간 전압을 각각 표시한다. 그리고 콜렉터 에미터간 전압 V_CE=3(V), I_B=(μA) 때의 게이트, 에미터간 전압(게이트 바이어스 전압) V_GE(V)-콜렉터 전류 I_C(μA) 에미터 접지 전류 증폭율 h_FE특성 곡선을 제 5 도로 표시한다. 이 제 5 도의 곡선에 의하면, 게이트 바이어스 전압의 변화에 따라, 전류 증폭율 h_FE가 아래로 철(凸)형을 이루고 그 철부 극소치(이 때의 게이트, 에미터간 전압이 상술한 임계치전압이다)에 대해 거의 축대칭인 곡선으로 변화할 수 있음을 알수 있다. 또 제 3 도의 제1 반도체 영역(에미터 영역)(1)의 두께를, 정공(주입 캐리어)의 확산거리 L_p보다 적게 선정 할 때는, 게이트 소오스간 전압 V_GE가 임계치 전압에 거의 비슷한 경우로서 표면 재결합의 영향이 코게 되어 주입 캐리어(소수 캐리어)의 수명 시간이 짧아 지고, 여기에 의하여 h_FE의 철(凸)부 극소치를 일층 적게 할 수가 있다.FIG. 5 shows an example of the characteristic curve of the four-terminal semiconductor device of FIG. 3 measured using the measuring circuit of FIG. In FIG. 4,

Denotes this four-terminal semiconductor element, and this symbol adds a short line in parallel with the emitter to the symbol of the conventional bipolar transistor and represents it as a gate. In the circuit of Fig. 4, this four-terminal semiconductor element

Is the emitter ground type, R _L is the collector load resistance, V _CC is the collector supply voltage, I _C is the collector current, I _B is the base current (constant current), and V _GE is the voltage between the gate emitters. do. And gate when the collector-emitter voltage V _CE = 3 (V), I _B = (μA), the voltage between the emitters (gate bias voltage) V _GE (V) -collector current I _C (μA) emitter ground current amplification factor h The _FE characteristic curve is shown at the fifth degree. According to the curve of FIG. 5, according to the change of the gate bias voltage, the current amplification factor h _FE is convex downward and the convex minimum value (the voltage between the gate and emitter at this time is the threshold voltage described above). It can be seen that it can be changed into a curve which is almost axisymmetric about. When the thickness of the first semiconductor region (emitter region) 1 of FIG. 3 is selected to be smaller than the diffusion distance L _p of the hole (injection carrier), the gate-source voltage V _GE is almost similar to the threshold voltage. is scorching the influence of surface recombination is possible to reduce the carrier injection shorten the life time of (minority carriers), the ground floor of the iron h _FE (凸) parts by minimal value herein.

The example of FIG. 3 described above is of the NPN type, but of course, the PNP type is also possible as in the conventional general bipolar transistor.

를 가지고 그 베이스에 일정 베이스 바이어스 전류가 흐르고 게이트에 저항기(15)를 끼워 전류 증폭율서 철부 극소치로 되는 게이트 바이어스 전압이 주어지고 게이트 및 콜렉터 사이에 콘덴사(14)가 주어져 이 게이트 및 콜렉터 사이에 콘덴사(14)가 접속되어 이루어 지고 베이스에 트리거 신호가 공급되고 콜렉터에서 다안정 출력이 얻어져서 단안정 회로가 구성된다. 이 4단자 반도체소자

는 이 예에서는 NPN형이고 그 콜렉터가 부하 저항기(12)를 통하여 전원+B₁에 접속되고 에미터가 접지되고 베이스가 바이어스용 저항기(11)를 통하여 전원+B₁에 접속된다. -B₂는 반도체 소자

의 게이트, 에미터 간에 상기 소정의 게이트 바이어스 전압을 주는 전원이다. t₁은 콘덴사(13)를 거쳐 반도체소자

의 베이스에서 도출된 트리거(trigger) 신호의 입력단자이고, t₂는 그 콜렉터에서 도출된 단안정 출력이 얻어지는 출력단자이다.An embodiment of the present invention will be described below with reference to FIG. In the present invention, an emitter collector base and a gate are provided. The current amplification rate is changed to an almost axisymmetric curve with respect to the iron minimum where the current amplification factor is concave down according to the change of the gate bias voltage applied between the gate and the emitter. 4-terminal semiconductor device exhibiting characteristics

A constant base bias current flows through the base and a resistor 15 is inserted into the gate to give a gate bias voltage that is a minimum value of the current amplification factor. The condenser 14 is connected, a trigger signal is supplied to the base, and a multistable output is obtained from the collector, thereby forming a monostable circuit. 4-terminal semiconductor element

Is connected to this example, the NPN-type and the collector is connected to the power supply + B ₁ through the load resistor 12, the emitter connected to ground and power the base is via a resistor 11 for bias B + _1. -B ₂ is a semiconductor device

It is a power supply which gives the said predetermined gate bias voltage between the gate and the emitter. t ₁ is a semiconductor device via a condensate (13)

The input terminal of the trigger signal derived from the base of the signal, t ₂ is the output terminal from which the monostable output derived from the collector is obtained.

의 게이트, 에미터간 전압 V_GE-에미터 접지 전류증폭을 h_FE특성곡선을 표시하고, 같은 도면에 있어서 h_FE1은 h_FE의 철부 극소치 즉 최소치를 표시하고, 이때의 V_GE는 -V₁(이때는 V₁〉0)이다. 또 V_GE가 이 -V₁보다 다시금 저하하여, h_FE가 점점 증대하여 포화하기 시작한 곡선의 견부의 h_FE가 h_FE2로 된다. 그때의 V_GE는 -V₂(이 경우는 V₂〉0)이다. 그리고 출력단자 t₂의 출력전압(콜렉터전압)의 고전압 V_H및 저전압 V_L은 저항기(11), (12)의 저항치를 각각 R_B, R_L전원+B₁의 전압을 V_CC, 베이스 바이어스 전류를 I_B로 하면 각각7 is a semiconductor device of FIG.

The gate, emitter voltage V _GE - the emitter grounding current amplification h _FE h _FE1 in the figure show a characteristic curve, and h _FE is a minimum value of the convex portion that is shown the minimum value, and wherein the V _GE is -V ₁ ( At this time, V ₁ > 0). In addition to V _GE is again lower than the -V _1, h _FE that h _FE of the shoulder of the curve begins to increase more and more saturated and is in h _FE2. At that time, V _GE is -V ₂ (in this case V ₂ > 0). In addition, the high voltage V _H and the low voltage V _L of the output voltage (collector voltage) of the output terminal t ₂ correspond to the resistance values of the resistors 11 and 12 with the voltages of R _B and R _L power supply + B ₁ , respectively, V _CC and base bias. If the current is I _B ,

_{V H = V CC -h FE1 ·} I B · R L

_{V L = V CC -h FE2 ·} I B · R L

Is displayed as: Between V _CC , V _H , and V _L

V_H》V_L의 관계가 성립 하도록 저항기(11)(12)의 저항치 R_B, R_L이 선정된다.V _CC

The resistance value R _B, R _L of the resistors 11 and 12 is selected for the relationship between the V _H "V _L to satisfied.

The time width T of the square wave as a monostable output is mainly determined by the voltage V _CC of the power supply + B _1, the voltage between the gate and the emitter -V ₂ , the resistance R of the resistor 15, and the capacitance C of the condenser 14.

Next, the operation of this monostable circuit will be described with reference to FIG.

8a, b, and c show respective waveforms of the trigger signal supplied to the input terminal t ₁ (base), the output signal obtained from the output terminal t ₂ (collector), and the voltage V _GS between the gate sources.

의 베이스에 트리거 신호(정펄스)가 공급되면 콜렉터 전압은 거의 접지 전위가 되고 이 때문에Semiconductor device

When the trigger signal (constant pulse) is supplied to the base of the

V _GS is V _GS = -V _1- (V _H -0)

=-(V ₁ + V _H )

0)로 보지된다. 그리고 이 콜렉터 전압의 저하에 의하여 콘덴사(14)의 전하가 저항기(15)를 통하여 콘덴사(14)의 용량 C 및 저항기(15)의 저항치 R에 의하여 정해지는 시정수를 가지고 방전되고, V_GS는 서서히 상승하고 V_GS가 -V₂를 통과하면 h_FE가 하강하기 시작한다. 이에 따라 콜렉터 전압은 상승을 시작한다. 이 콜렉터 전압의 상승은 콘덴사(14)를 통하여 게이트에 정궤환 되고 V_GE가 -V₁에 도달하고, 콜렉터 전압(출력전압)은 처음의 V_H(

V_CC)에 돌아 온다.Becomes And even after the constant pulse to the base disappears, the collector voltage will remain at V _L (

0) Due to the decrease in the collector voltage, the charge of the condensate yarn 14 is discharged through the resistor 15 with the time constant determined by the capacitance C of the condensate yarn 14 and the resistance value R of the resistor 15. _GS slowly rises and h _FE begins to fall as V _GS crosses -V ₂ . As a result, the collector voltage starts to rise. This collector voltage rises positively to the gate through the condenser 14 and V _GE reaches -V ₁ , and the collector voltage (output voltage) is the first V _H (

Return to V _CC ).

According to the present invention described above, a monostable circuit having a simple configuration using one active element is obtained.

Claims (1)

As described in the text and shown in the drawings, the first semiconductor region of the first conductivity type, the second semiconductor region of the second conductivity type in contact with the first region, and the third conductivity type of the first conductivity type in contact with the second region High concentration region and first region in the semiconductor region and the first region and in contact with the low concentration region in the second region and the low concentration region in the first region, and the distance between the junction surface and the second region is smaller than the diffusion distance of minority carriers in the low concentration region. And a four-terminal semiconductor element having a first electrode connected to the second electrode, a second electrode connected to the second region, a third electrode connected to the third region, and a fourth electrode connected by placing an insulating layer in the high concentration region. And a bias current is supplied to the second electrode, a predetermined voltage is supplied through a resistor to the fourth electrode, and a condenser is connected between the third electrode and the fourth electrode, and the trigger is applied to the second electrode. Monostable circuit, characterized in that the call is a supply so that the monostable output is obtained from the third electrode.

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