KR790001052B1 - Circuit arrangement for generating a sawtoooth deflection current through a line deflection coil - Google Patents

Abstract

A circuit for generating a sawtooth wave deflecting current through a line deflecting coil in the receiver converts the unstable supplying voltage into stable deflecting current, high voltage, and supplementary voltage. It consisted of a deflection circuit (Ly, Ct, Cr), the first diode(D1) the second diode(D2), control switches, an inducing device(L1, L2), a transformer(T2), and the third diode(D3). The transformer(T2) was comprised of a magnetic core and a winding (L3) series coupled to the condenser(C1).

Description

Sawtooth deflection current generating circuit device of line deflection coil

1 is a circuit diagram schematically showing basic elements in an embodiment of a circuit device according to the present invention.

2 is a waveform of voltage generated in the above-described embodiment.

3 is a graph used for parameter selection.

4 is a circuit diagram of a modified part of the circuit device of FIG.

The present invention relates to a circuit arrangement for generating a sawtooth deflection current through a line deflection coil in an aquatic apparatus, the circuit arrangement comprising a deflection coil, a trace network including a trace capacitor and a trace capacitor, and a first diode. Current flows through the first diode during some portion of the trace interval and through the second diode and the control switch during the remainder of the trace interval, and the control switch and the second diode are connected in parallel with the first diode. The device comprises a single inductive element and a transformer, which are connected to a switch and to a deflection network via a third diode, the transformer having a core of magnetic material, whose windings deflect in series with the capacitor. It is connected to the network.

These circuits are called "IEEE Transactions on Broadcast and Televison Receivers."

It is described in Volume BTR-18, Nr 3,177-182, August 1972, which is a combination of a line deflection circuit and a switch mode supply voltage stabilization circuit, where the control switch is used to perform the two functions described above. Such known circuit arrangements have the following advantages: they are supplied with an unstabilized supply voltage, which can supply satisfactorily stabilized deflection currents, stabilized high voltages and even stabilized auxiliary voltages. It is obtained by controlling the conduction time of the switch. When designing such a circuit device, three of the following problems arise.

First, care must be taken to ensure that the maximum voltage across the switch (transistor) during the retrace period does not exceed the limit allowed for this device.

Second, the change in the conduction time of the transistor should be able to adjust the expected change in supply voltage,

Third, the trace capacitor voltage supplied to the deflection coil (stable) during the trace interval should be arbitrarily selected because this voltage supplied to the deflection coil described above determines the strength of the generated deflection current. The problems described above are distinct from one another. For example, if the trace voltage is low, the maximum collector voltage of the transistor is also low. This can be further reduced by making the conduction time of the transistor as short as possible. So it is obvious that some degree of freedom is needed. One degree of freedom, the transformer ratio between two coils of an inductive element, is useful to some extent. One of the two coils is connected between the terminal of the supply voltage power source and the junction point of the collector and the second diode, and another coil coupled to the coil is connected to the third diode. This is because the above-described selection of the transformer ratio makes it possible to select the trace voltage more freely. However, the other two problems, in particular the problem of the maximum collector voltage, are not solved by doing so.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit arrangement having one or more degrees of freedom so that the maximum allowable collector voltage can be freely determined. For this purpose, a circuit arrangement according to the present invention is described above by means of an inductive element via a third diode. And a series coupling of a series capacitor and a portion of the transformer coil. The introduction of new parameters not only allows the maximum collector voltage to be reduced without affecting the trace voltage, but also allows the supply voltage variation to be adjusted to a larger range. Thus, in the step according to the present invention, it is possible to design a circuit device in which discordant requirements can be simultaneously satisfied. In a possible embodiment where the inductive element has a coil, the circuit arrangement is characterized in that the coil of the inductive element is wound around the transformer core.

An embodiment of the present invention will be described with reference to the accompanying drawings.

The circuit arrangement shown in FIG. 1 includes one drive stage Dr, which receives a signal from a pre-generator (not shown in the drawing) and transmits switching pulses to the base of the switching transistor Tr. To pass.

One end of the primary coil L ₁ of the transformer T ₁ is connected to the collector of the npn type transistor Tr, and the other end is connected to the positive terminal of the DC voltage power source B and the power source B The emitter of the transistor Tr is connected to the negative terminal of). This negative terminal may be connected to the ground of the circuit arrangement. The trace capacitor Ct is connected in series with the line deflection coil Ly of the water phase device, and the series coupling is distributed by the diode D ₁ (polarity as shown in the figure) and the retrace capacitor Cr. The capacitor Cr may be connected in parallel with the coil Ly.

The four elements described above represent a schematic circuit diagram including only the basic elements of the deflection section. The deflections can be equipped with transformers above the limit for mutual coupling of the elements, for example, by known methods, as well as central and linear correction devices.

The secondary coil L ₂ of the transformer T ₁ is connected to both stations of the diode D ₃ and the anode of the diode D ₂ is connected to the junction A of the elements D ₁ , Cr, Ly. . The cathode of the diode D ₂ is connected to the collector of the transistor Tr, while the cathode of the diode D ₃ is connected to the tap on the coil L ₃ of the transformer T ₂ . One end of the coil L ₃ is connected to the point A and the other end is grounded via the capacitor C ₁ . The core of the transformer T ₂ comprises further coils in which voltages are generated to provide a supply voltage for the other components of the water phase device.

FIG. 1 shows a coil L ₄ of the above-described coils, which generates a (±) DC voltage across the smoothing capacitor C ₂ by the rectifier D ₄ .

Among the coils, for example, the coil L ₄ is a high voltage coil, so the voltage applied to the capacitor C ₂ is a high voltage with respect to the final accelerating anode of the water pipe (not shown). The free ends of the coils L ₂ and L ₄ are grounded, and the coil winding method of the coils in the figure is indicated by poles in the figure. The operation of the circuit device is summarized as follows.

The diode D ₁ conducts during the first part of the sun trace section. The voltage applied to the capacitor Ct is supplied to the deflection coil Ly, through which the sawtooth wave deflection current i _y flows. And that the transistor (Tr) to conduct at a certain moment, when changing the current (i _y) direction from the middle of the trace interval diode (D ₁₎ a current (i _y) since the blocking diode (D ₂₎ and the transistor It flows through (Tr). At the end of the trace period, the transistor Tr is cut off. As a result, a retrace pulse oscillation is generated in the capacitor Cr, while the energy stored in the coil L ₁ originating from the power source B causes the current to flow through the diode D ₃ . When the voltage across the capacitor Cr becomes zero again, the diode D ₁ conducts, which is the beginning of a new trace period. A diode (D ₃₎ and is in the conductive state until the transistor (Tr) conducting, the energy stored in the coil (L ₂₎ is passed to the coil (L _1). Stabilization is achieved by feeding back the voltage across the capacitor Ct to the drive circuit Dr. The drive circuit Dr has a comparator and a modulator, which change the conduction time of the transistor Tr, Keep the amplitude constant. Compared with the known case in which the cathode of the diode D ₃ is connected to the point A instead of the tap, the operation is different, the difference being as follows. In the known case, the current passing through the diode D ₃ flows to the ground terminal via the diode D ₁ during the first part of the trace interval. However, in the apparatus shown in FIG. 1 during the interval energy it is stored in the series combination of L ₃ and C _1.

The voltage V _A applied to the capacitor Cr, the voltage V _C at the collector of the transistor Tr, the voltage V ₁ applied to the coil L ₁ , and the like are shown in FIGS. 2A, 2B, and 2C, respectively. It is shown as a function of time.

T denotes a line period, τ ₁ denotes a retrace section, τ ₂ denotes a portion in which the transistor Tr does not conduct, and τ ₃ = δ _T denotes a portion in which the transistor Tr conducts. δ is the ratio between the time τ ₃ and the period T. The voltage V _A consists of a retrace pulse of amplitude V during time τ ₁ and is zero during time τ ₂ . At the moment when transistor Tr becomes conductive, that is, at the transition time t ₁ between τ ₂ and τ ₃ , the voltage V _C is actually zero. Thus, the voltage V _B of the power supply B is applied across the coil L ₁ .

In the circuit arrangement of FIG. 1, two ratios are very important: one is the ratio of the transformation between the coils L ₁ and L ₂ : 1 and the other is the total number of turns of the coil L ₃ and the capacitor C ₁ . The ratio of the number of turns of this coil L ₃ portion between the connected terminal and the tab is 1: m. First, it is assumed that the points (Ｑ and A) are assumed to be coincident points (m = 1).

The voltage across coil L ₂ during time τ ₃ is -PV _B.

이다. 만약에 콘덴서(Ct)의 용량이 충분히 큰 경우에는 V₀를 콘덴서(Ct)에 걸리는 직류전압으로, S 보정의 목적상 비교적 적은 용량의 경우에는 V₀를 콘덴서(Ct)에 걸리는 전압의 직류전압 성분으로 간주하면, 어느 경우든지 V₀는 전압(V_A)의 평균치와 같은데, 왜냐하면 어떠한 직류전압 성분도 코일(Ly) 양단에 걸릴 수 없기 때문이다. 콘덴서(C₁)은 큰 용량을 갖고있기 때문에 V₀와 같은 직류전압이 이 콘덴서 양단에 걸리며, 다음 방정식이 적용된다.During time τ ₁ , the voltage V _C

to be. If the capacitance of the capacitor Ct is large enough, V ₀ is the DC voltage across the capacitor Ct. For the purpose of S correction, V ₀ is the DC voltage of the voltage across the capacitor Ct. Regarding components, in any case V ₀ is equal to the average value of voltage V _A , because no DC voltage component can be applied across coil Ly. Since capacitor C ₁ has a large capacity, a DC voltage such as V ₀ is applied across this capacitor, and the following equation applies.

Since the average value of the voltage across the coil L ₃ is also zero, the following equation applies;

If you solve the integral from the above two expressions,

V _O T = PV _B τ ₃ , ie V _O = PδV _B ---------------------------- (1)

Becomes At a given value of δ and P the diode D ₂ will conduct for τ 1. Since the diode D ₃ is also conducting during this time, the coils L ₁ and L ₂ are short-circuited by the diodes D ₂ and D ₃ , and the retryo pulses applied to the capacitor Cr are clipped. (Clip) and the deflection current is distorted. Our co-pending Dutch Patent Application No. 7,303,252 (PHN 6794) (Korean Application 74-1700) describes steps to eliminate such effects. For example, it is possible by connecting a transistor which is blocked for τ ₁ in series with the diode D ₂ . The condenser C _{3 is} connected between the ends of the coils L ₁ and L ₂ or the intermediate taps for the purpose of preventing parasitic oscillation which may be caused by the leakage inductance between the coils, and thus the condenser C _3. ) There is no line frequency voltage at both ends. FIG. 1 shows the case where P <1.

The maximum value of the collector voltage V _C of the transistor is as follows.

는

값이고, 이것은 리트레이스비

에 달려 있다. V_C의 최대값은 V_B가 최대값 V_Bmax를 가질 때 얻어지며, 이때 δ는 δmin이 된다. 관계식(1)로부터 전압(V₀)가 일정하기 때문에 δ와 V_B는 역비례한다. 전압(V₀)는 P를 석택함으로서 정해질 수 있기 때문에 편향전류(i_y)는 주어진 편향코일(L_y)에 대해 정해진다. 그러나 트랜지스터에 대해 매우 임계적인 전압(V_C)의 최대값은 제어할 수 없다. 게다가 관계식 (1)은 다음과 같이 쓸 수 있다.here

Is

Value, this is the retrace ratio

Depends on The maximum value of V _C is obtained when the V _B have a maximum value V _B max, wherein δ is the δmin. Since voltage V ₀ is constant from relation (1), δ and V _B are inversely proportional. Since the voltage V ₀ can be determined by selecting P, the deflection current i _y is determined for a given deflection coil L _y . However, the maximum value of the very critical voltage (V _C ) for the transistor cannot be controlled. Furthermore, relation (1) can be written as

V _O = Pδ min x V _B max = Pδ max V _B min

Where VB min is the minimum value of VB, where δ = δmin.

이다. 만약 t1이 트레이스 구간의 중간에 일치되는 경우에는 δmin은 최소값(δ₁)을 가지며, t₁이 트레이스 구간의 개시부분(t₀)와 일치하는 경우에는 δmax는 최대값(δ₂)을 갖는다. 그래서 상기한 비율(δ)은 2를 넘을 수 없기 때문에 장치는 전압(V_B)의 더 큰 변화들을 조정할 수 없게 된다.From the above equation

to be. If the t1 is in this case matched to the middle of the trace period, δmin has a minimum value (δ _1), t ₁ matches the start portion of a trace interval (t ₀₎ it has δmax has a maximum value (δ _2). Thus, the ratio δ cannot exceed 2, so that the device cannot adjust larger changes in voltage V _B.

According to the present invention, the point A and the point do not coincide. Since the voltage across coil L ₃ is V _A -V ₀ , the voltage at point V _Q is V _Q = V ₀ + m (V _A -V ₀ ) = _m V _A + (1- m) V ₀ .

With the help of the waveform of the voltage V _{A in} FIG. 2a, the waveform of the voltage V ₁ across the positive terminal of the power supply B and the collector of the transistor Tr, ie across the coil L ₁ , is ( 2c) can be shown, taking into account the fact that diode D ₃ conducts during times τ ₁ and τ ₂ . so

Using the condition that the average value of the voltage (V ₁ ) is 0, the following results are obtained.

[mV+(1-m) V₀]+V_Bmax이 되고, 그것으로부터 다음과 같은 결과를 얻는다.The maximum value of the collector voltage (V _C ) is V _C max =

[mV + (1-m) V ₀ ] + V _B max, and the following results are obtained.

This function shows that m decreases continuously.

7.8이 된다. 도면에서는 m을 1 보다 작게 함으로써 최대 콜렉터 전압의 감소가 얻어지는데, 이 결과는 P와는 무관하다.This is depicted in Figure 3a when Z = 0.2 and delta min = δ ₁ = 1/2 (1-Z) = 0.4. From it

7.8. In the figure, a decrease in the maximum collector voltage is obtained by making m smaller than 1, which is independent of P.

From equation (2) the following equation is derived.

이 2를 초과하기 때문이다. 앞서의 경우와 유사하게 전압(V₀)는 p를 선택함으로서 정해질 수 있다. 만약 위에서 언급된 공동 출원중인 네델란드 특허출원 7,302,252(한국출원 74-1700호)에 명시된 방법들이 필요없게 된다면, 상한선이 P에 정해질 수 있음이 발견된다. 만약 실제로 측정되는 전압(V_C)의 최소값, 즉 V_Cmin=

[mV+(1-m)V₀]+V_Bmin이 전압(V)와 같다면, 다이오드(D₂)는 τ₁동안 꼭 전도할 것이다.This function is also independent of p and increases when m decreases. This is plotted in Figure 3b for δ min = δ ₁ = 0.4 and δ max = δ ₂ = 0.8 (Z = 0.2), while the full range of δ is used, while the figure shows that a larger range of supply voltage variations can be adjusted. Shows that there is. Because when m is less than 1

This is because it exceeds 2. Similar to the above case, the voltage V ₀ may be determined by selecting p. It is found that the upper limit can be set at P if the methods specified in the co-pending Dutch patent application 7,302,252 (Korean application 74-1700) mentioned above are not necessary. If the actual value of the measured voltage V _C , ie V _C min =

If [mV + (1-m) V ₀ ] + V _B min is equal to the voltage V, the diode D ₂ will necessarily conduct for τ ₁ .

이 되고, 이로부터 우리는 다음 식을 유도할 수 있다.From the above formula, by the formula (2),

From this we can derive the following equation.

The above will be explained by two formal examples.

은 2 보다 작고 그래서 이것은 별 문제를 제기치 않는다.If the voltage V _B can vary between 230V and 345V (main voltage is 220V),

Is less than 2 so this raises no problem.

If the transistor Tr cannot tolerate a voltage exceeding 1,200V, it can be seen from FIG. 3a that m = 0.64.

From equation (2)

Therefore, δmax = 0.56 <δ ₂ .

따라서, V₀=0.87×161=140V이다.From equation (5)

Therefore, V ₀ = 0.87 × 161 = 140V.

=3이다.If the voltage (V _B ) can vary between 115V and 345V (mains voltage 110V or 220V)

= 3.

인반면,

따라서, V₀=0.54×183=99V이다.It can be seen that m = 0.38 in FIG. 3b and V _C max = 2.9 × 345 = 1,000V in FIG. 3a. From equation (2)

Photography,

Therefore, V ₀ = 0.54 × 183 = 99V.

Since m cannot increase, if a higher voltage (V ₀ ) is required, P must exceed 0.54 and the steps according to the patent application mentioned above should be used.

)대신에 다른 코일을 추가로 코일(L₃)와 같은 코어에 감을 수도 있다. 여기서 추가코일은 코일(L₃)보다 권수가 적고 다이오드(D₃)의 음극과 L₃와 C₁의 접함점과의 사이에 포함되어야 한다.Similar to the case of our co-pending Dutch patent application 7,307,631 (PHN 6967) (Korean application 74-6902), the cores of the transformers T ₁ and T _{2 in} FIG. 1 can be one and the same core. In other words, the coils L ₁ , L _2, and L ₃ may be coupled to each other despite different waveforms of voltages applied thereto. This is because the aforementioned waveforms are not affected by the combination. In other words, the voltages V ₀ and V _B are hard, ie supplied externally, so that they are not affected by the coupling. However, the currents flowing through the coils are affected. The aforementioned patent application shows that the operation of the circuit arrangement is not adversely affected by them, but on the contrary, important advantages are obtained. You can also tap

Alternatively, another coil may be further wound on the same core as coil L ₃ . Wherein additional coils are to be included between the cathode and the tangent point of L ₃ and C ₁ of the coil winding number is less than (L ₃₎ a diode (D _3).

)사이의 인덕턴스(L₅)로서 보여진다. 인덕턴스(L₅)는 급격한 전류 전이를 방지하는데 그것은 표유용량과 함께 링깅을 일으킬 수 있다. 이것은 점(A)와 점(

)사이에 콘덴서(C₄)를 연결하고, 코일(L₃)와 콘덴서(C1)의 접합점과 점(

)의 사이에 콘덴서(C₅)를 연결함으로써 피할 수 있다. 만약에 C₄와 C₅의 리액턴스 사이의 비율이 코일(L₃)의 상부와 하부의 권수의 비율과 같다면, 인덕턴스(L₅)양단에는 어떠한 교류 전압도 발생될 수 없고 따라서 어떠한 링깅현상도 일어날 수가 없게된다. 콘덴서(Cr)과 회로망(C₄, C₅)의 회로장치 유도성분들과의 병렬연결은 공진주파수의 주기가 시간(

₁)의 약 2배와 같게되는 결과를 초래한다.Equation (5) shows that m should not be too small, because in this case p is also small, resulting in a large current flowing on the secondary side of transformer T ₁ . In addition, a large amount of current flows through the leakage inductance of the transformer T ₁ , causing ringing at the instant t ₁ . Another difficult problem arises in designing the above-mentioned embodiment using one transformer. If for this reason it is not possible to follow Eq. (5), that is, if P becomes larger than Pmax, then the steps according to the aforementioned patent application 7,303,252 (Korean application 74-1700) should be used. In this case, an additional transistor is needed, which is expensive, or an additional diode is required, which cannot prevent the occurrence of high Vcmax. On the other hand, getting low Vcmax was the purpose of using low m. In practice there is a leakage inductance between the two parts of the coil L ₃ . In the showing only a portion of the circuit device 4 also has such a leakage inductance coil (L ₃₎ virtual tab (Q ') and that on the (

Is shown as the inductance (L ₅ ) between Inductance L ₅ prevents rapid current transitions, which can cause ringing with stray capacitance. This is the point (A) and point (

Connect the condenser (C ₄ ) between them and connect the coil (L ₃ ) with the condenser (C1)

This can be avoided by connecting the capacitor C ₅ between them. If the ratio between the reactances of C ₄ and C ₅ is equal to the ratio of the number of turns of the upper and lower parts of the coil L ₃ , no alternating voltage can be generated across the inductance L ₅ and therefore no ringing phenomenon You can't get up. The parallel connection between the capacitor (Cr) and the circuit device inductive components of the network (C ₄ , C ₅ ) has a period of resonant frequency

Results in equal to about 2 times ₁ ).

In the above, it is assumed that the capacity of the capacitor C ₁ is large enough so that the voltage applied to it is regarded as a constant value (˜V ₀ ). It should also be noted that this is only necessary if one or more auxiliary voltages generated by the coils of the transformer T ₂ are obtained by trace rectification.

Claims (1)

A circuit device for generating a sawtooth wave deflection current through a line deflection coil in an aquatic device, comprising a deflection network (Ly, Ct, Cr), a first diode (D ₁ ), a second diode (D ₂ ), and a control switch ( Tr), inductive elements (L ₁ , L ₂ ), transformer (T ₂ ), second diode (D ₃ ), and the like. The deflection network includes a deflection coil (Ly), a trace capacitor (Ct), and a retrace. Condenser (Cr), the deflection current (iy) is the first part of the trace section (

₂ ) flows through the first diode D ₁ and the remaining portion of the trace section (

₃ ) flows through the second diode (D ₂ ) and the control switch (Tr), the control switch (Tr) and the second diode (D ₂ ) is connected in parallel with the first diode (D ₁ ), the induction element ( L ₁ , L ₂ is connected to the switch Tr and coupled to the deflection network via the third diode D ₃ , the transformer T ₂ has a magnetic core and its winding L ₃ is the condenser C _1. Coupled to the deflection network in series with Induction elements (L ₁ , L ₂ ) is connected via a third diode (D ₃ ) in series coupling of the capacitor (C ₁ ) and the winding of the winding (L ₃ ) described above, the induction elements (L ₁ , L ₂ ) is a sawtooth deflection current generating circuit device of a line deflection coil, characterized in that the coil wound around the transformer (T | ₁ ) core.

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