KR790000814B1 - Circuit arrangement for generating a sawtooth deflection current through a line deflection coil - Google Patents

Abstract

A circuit for generating a sawtooth deflection current, was composed of a sawtooth circuit in which a coil was co-operated with a trace condencer for trace time of the sawtooth current and with a retrace condencer for retrace time, a switching device which was cut off for the duration of the supplied voltage source and retrace, a RF tuning device(1), an ANT(2), an IF amplifier(3), a detector(4), a color decorder(5), a color display tube(6), an acceleration anode(7), a horizontal (Ly) and vertical (Ly') deflection coil.

Description

Sawtooth wave deflection current generating circuit device

1 is a circuit diagram showing a television display device having one embodiment of a sawtooth wave deflection current generating circuit arrangement according to the present invention;

2 to 7 are circuit diagrams showing another embodiment of the sawtooth wave deflection current generating circuit arrangement according to the present invention, respectively.

The present invention relates to a circuit arrangement for generating a sawtooth deflection current flowing through a linear deflection coil by a sawtooth circuit consisting of a diode and a coil, wherein the above-mentioned coils work together with a trace capacitor during the trace time of the sawtooth current and It works with the retrace capacitor during the trace time, and the circuit arrangement includes a switching device and a voltage power source that are cut off during the retrace time.

Such circuit arrangements are described in US Pat. No. 3,444,426. To correct raster diotortion in the horizontal direction, i.e. to perform so-called east-west correction of the displayed image on a television display device, the supply voltage is applied to the direct current voltage and the feed frequency parabolic voltage. The sum voltage of This parabolic voltage originates from the feed deflection current generator forming part of the television display device. As a result, the linear deflection current is subjected to the feedback frequency modulation necessary for the above correction.

In the conventional circuit arrangement, there is a drawback that the retrace pulse existing between both terminals of the inductor provided between the switching device and the voltage power supply during the retrace time is feed frequency modulated. The inductor is coupled with a winding so that the retrace pulse described above is boosted and supplied to a rectifier for generating a special high voltage (EHT) for an accelerated anode of a television display device. Because of this, the special high voltage is unnecessarily modulated. In addition, the auxiliary voltage generated by a known method is also unnecessarily modulated by another winding coupled to the inductor described above.

Known circuit arrangements are provided with highly stable circuits for supply voltages, so that even if the voltage supplied from the main circuit is supplied to the stabilization circuit described above or the load of the above-mentioned windings varies, the DC voltage and its frequency frequency components are changed. There is a drawback to keeping it constant. The drawback of the former is that the two generators are used, and at least one signal is modulated at the same time by one generator, and these generators can be removed from a known circuit arrangement by combining them as a bridge circuit. In this case a transformer is required and the equilibrium as a bridge coil must be adjusted and this parallelism must be maintained under all conditions.

It is an object of the present invention to provide a circuit arrangement without a bridge circuit, which does not require stabilization of the supply voltage and furthermore does not need to frequency frequency modulate this voltage. To this end, the circuit arrangement of the present invention has the following characteristics: at least one second sawtooth wave circuit having a second diode and a second coil is installed, and the second coil includes a second slice capacitor and a second retrace. It works together with the capacitor, and the retrace time of the current flowing in the second coil is about the same as the retrace time of the deflection current, and the two sawtooth circuits are interconnected to interconnect the two diodes in series and simultaneously The two are set in the same conducting direction, the series arrangement of these two diodes is connected in parallel with the switching device, and the voltage between both terminals of the trace capacitor can be controlled by the control element.

In the technical means according to the invention there is no need to limit to simultaneous correction, but for example to stabilize the supply voltage fluctuations or to generate a correction difference current, or generally with a horizontal deflection coil. It can be used to obtain the characteristics of the deflection current which deviate from the characteristics of the voltage between both the actuating trace capacitors and the characteristics of the supply voltage. In one embodiment of the circuit arrangement of the present invention, a trace capacitor is formed as a plurality of capacitors, and one of the capacitors constitutes a trace capacitor that works together with a coil of another sawtooth circuit.

The present invention will be described in detail with reference to the drawings.

In the television display device of FIG. 1, 1 is a radio frequency tuning device, 2 is an antenna connected to a radio frequency tuning device, 3 is an intermediate frequency amplifier, 4 is a detector, 5 is a color decoder installed in an image amplifier, 6 is a color receiver. The above-described color decoder 5 supplies a color signal to the color receiving tube 6. This color water tube 6 has an accelerating anode 7 which also has a coil Ly for horizontal deflection (line frequency) and a coil L'y for vertical deflection (pile frequency).

The line sync pulses supplied to the starter 9 and the feed sync pulses supplied to the feed oscillator 10 are separated from the output signal of the detector 4 by the sync separator 8. The feed oscillator 10 controls the feed output terminal 11 to thereby supply a deflection current to the coil L'y. In addition, the drive stage Dr (driver stage) is controlled by the starter 9, and the drive stage supplies a switching pulse to a control switch such as a switching transistor Tr of a line deflection output circuit, which will be described later, for example.

The trace capacitor Ct is arranged in series with the deflection coil Ly and the diode D having a predetermined conduction direction, and the retrace capacitor Cr is connected in parallel with the series circuit described above. In addition, the capacitor Cr may be connected in parallel between both terminals of the coil Ly. These four elements are for displaying the main circuit diagram together with the main components of the deflection section. This deflection section can be provided with, for example, one or more transformers, i.e., centering and linear correction circuits, for coupling each of these elements, as is known.

One terminal of the primary winding L ₁ of the transformer T or the collector of the intermediate wrap nPn transistor Tr is connected to the junction A of the elements D, Cr, and Ly. Connect the (+) terminal of DC voltage power supply (B) to the other terminal of the winding (L ₁ ) and ground the (-) terminal.

The terminal not connected to the deflection coils Ly of the elements D, Cr and Ct is connected to the junction of the diode D 'and the coil L' of the capacitor Cr '. The capacitor Ct 'is connected in series with the coil L' and connected to the junction of the rest L 'of the elements D', Cr 'and Ct'. The capacitor Ct 'is connected in series with the coil L', and the remaining terminals of the elements D ', Cr' and Ct 'are grounded. The conduction direction of the diode D 'is the same as the conduction direction of the diode D. That is, the anode of the diode D 'is grounded. A circuit having the same structure as the network having the elements D ', L', Cy 'and Ct' and configured as the elements D, Ly, Cy and Ct may be formed, but the impedance may be set to a different value.

The modulation source M ₁ is arranged in parallel with the capacitor Ct '. In this modulation source, the transistor Tr is installed, the emitter is grounded, the collector is connected to the junction of the coil L 'and the capacitor Ct', and the driving stage D'r is again installed to provide the transistor T'r. The drive stage Dr 'is connected to the feed output terminal 11 at the same time as controlling the base. This drive stage D'r derives a feed frequency modulation control signal that changes parabolic from the signal of the feed output stage 11. This control signal is used to correct east and west raster of the line deflection current. This control signal changes to the feed frequency, but it can be considered to take a constant value during one ship cycle. Since the raster distortion to be corrected is generally failure type, the modulation technique used here is that the amplitude of the linear deflection current changes to a parabolic envelope, while the peak value of the parabola is in the middle of the feed trace time. It is necessary to make a technique to generate and to match the maximum amplitude.

The other winding is wound around the core of the transformer T, and a voltage which acts as a supply voltage between both ends of this winding is generated and supplied to another part of the television display device. One of these windings, the winding L _{2 of} FIG. ₁ , works with the EHT rectifier to provide a special high voltage (EHT) for the accelerated anode 7 of the television receiving tube 6 across the smoothing capacitor C ₁ . Generate. The auxiliary supply voltage and EHT thus obtained shall not be subjected to the frequency modulation as with the horizontal deflection current.

Diodes D and D 'conduct after the start of the trace time. At this time, a voltage between the terminals of the capacitors Ct and C't is supplied to the coils Ly and L ', respectively, so that a sawtooth current flows through each coil. In this case, the current iY flowing in the coil Ly is a linear deflection current. Before reaching the middle of the trace time, a control signal is supplied to the base of the transistor Tr to challenge it. Nearly in the middle of the trace time, the two currents described above are reversed in direction. When the current iY is greater than the current i 'flowing through the coil L', the current iY flows through the transistor Tr, while the difference current iY-i 'is the diode D'. Flows through. Since the diode D is connected in parallel to the series arrangement of the transistor Tr and the diode D 'in the ground state, no voltage is applied even when the diode D is not conducting. On the contrary, when the current i 'is larger than the current iY, the current i' flows through the transistor Tr, the difference current i'-iy flows through the diode D, and the diode D ') No current flows and no voltage is applied. At the end of the trace time, the conductive diode is cut off according to the transistor Tr. For this reason, a substantially sinusoidal retrace voltage is generated between both terminals of the capacitors Cr and Cr '. At the moment when these voltages become zero again, the diodes D and D 'simultaneously conduct a challenge. This means the start of a new trace time. As a result, the retrace time determined as the diodes D and D 'and the elements Cr, Ly, Ct, and C'r, L', C't becomes almost the same, in which case the resonant frequency of each circuit is the same. Thus, the retrace time becomes a known function of the resonant frequency.

Since the transistor T'r is connected in parallel to the capacitor C't, the feed frequency variable load is present at the voltage V 'existing between both terminals of the capacitor. When the capacitance of the capacitor is appropriately selected so that the impedance at the feed frequency is not so small as to be negligible compared to the output impedance of the modulation source M ₁ , the voltage between the terminals of the voltage V 'and the capacitor Ct ( V) changes at the feed frequency when the capacitor is selected under the same conditions for the capacitor C't. The sum of the average values of the voltages V and V 'is equal to the voltage V _B of the power source B. This is because the DC voltage cannot remain between both terminals of the inductors L ₁ , Ly, and L '. The amplitude of the current iy changes to be equal to the voltage V. The control signal of the transistor T'r needs to be selected so that the feed frequency envelope of the voltage V and the current iy becomes a predetermined shape as described above.

The voltage V is almost equal to the average value of the voltage between both terminals of the capacitor Cr. This voltage V is proportional to the retrace voltage between both terminals of this capacitor. Similarly, the voltage V 'is approximately equal to the average value of the voltage between both terminals of the capacitor C'r, and this voltage V' is proportional to the retrace voltage between both terminals of the capacitor. As described above, according to the present invention, the retrace times of the networks D, Cr, Ly, and Ct and the networks D'C'r, L ', and C; t are almost the same. Thus, both retrace voltages have the same shape and their proportional constants. The voltage V _A at the point A is equal to the sum of the voltages between both terminals of the capacitors Cr and C'r, and the peak value and the average value of this voltage V _A , that is, the voltage of the power source B ( The relationship with V _B ) is the same between the retrace voltage between the terminals of the capacitors Cr and C'r and the voltages V and V '. If the voltage V _B is constant, the peak value of the voltage V _A is also constant. Accordingly, the amplitude of the voltage between both terminals of the winding L ₁ is also constant, and the EHT and the auxiliary supply voltage of the electrode 7 are not subjected to the feedback frequency modulation despite the modulation of the deflection current iy.

The variation in voltage V 'is opposite to the variation in voltage V such that voltage V' is minimized in the middle of the feed trace time.

As a result, the modulation source M ₁ is not arranged in parallel with the capacitor C't, but in parallel with the capacitor Ct, so that the polarity of the control signal of the transistor T'r is controlled in FIG. This can be achieved by reversing the case. In another method, the transistor T'r is provided not as a variable load but as a current power supply or a voltage power supply. In this case, the transistor T'r may be disposed as, for example, an emitter follower.

In practice, the ratio of inductances of the coils Ly and L 'is chosen to be approximately equal to the ratio of the average trace voltages required between these terminals. For example, if the sum of the trace voltages (V + V ') is about 150V, and the average DC voltage component of the voltage (V') is about 30V, the inductance of the coil (L ') is 1/1 of the inductance of the coil (Ly). Equal to 4. In practical examples it is about 270 μH and 1.2 mH. By adjusting the DC voltage component of the voltage V ', the width of the displayed image is adjusted, and at the same time, the amplitude of the feed frequency component is adjusted to obtain an image without distortion.

So far, it has been assumed that the voltage V _B is constant. This means that this voltage needs to be stabilized against fluctuations in the mains, ie possible fluctuations in other loads of the transformer T and hum voltages resulting from the wire. The illustrated embodiment of FIG. 2 does not require such stabilization. 2 shows only the important components of the apparatus of the present invention. This circuit arrangement includes circuits D, Cr, Ly, and Ct, networks D ', Cr', L ', and Ct' and a modulation source M ₁ as in the embodiment of FIG. The junction A between these networks and the collector of the transistor Tr is connected to the power source B via the choke L ₃ . In addition, this circuit is provided with a third similar network D ", Cr", L ", Ct", which is connected in series between each of the above-described networks and ground, and is connected to the third network. The stabilization circuit S having the same retrace time as the two circuits described above is connected in a similar manner to the modulation source M ₁ . The terminal 12 is provided in this stabilization circuit S, and the terminal has a voltage V + V variation or a series circuit arrangement (D, Cr, Ly, Ct and D ', Cr', L ', Ct'). Information about any of fluctuations in the peak value of the voltage V _A between both terminals of By providing a reference voltage power supply in this stabilization circuit S and comparing the above-mentioned information to it, the capacitor C't is made constant while the voltage V _A is made constant without making the collector voltage of the transistor Tr constant. The variation of the voltage V " between both terminals of < RTI ID = 0.0 >) can be obtained. ≪ / _RTI > Ct ') in parallel with the insulating capacitor, which causes the EHT and auxiliary supply power to be independent of the change in voltage V _{B. As} in the case of the embodiment of FIG. The circuit arrangement in FIG. 2 is a monochrome television without network D ', Cr', L ', C't, for example without simultaneous modulation. Obviously, it can be used in a display device, in which case the voltage (V) is kept constant so that the retrace voltage generates EHT. Be appropriate to Sikkim.

3 is a view showing an embodiment of the present invention without the need to stabilize the voltage V _B as in the embodiment of FIG. In this figure, a circuit arrangement, a combination circuit of a line deflection circuit and a switch supply voltage stabilization circuit, described in the magazine "IEEE Transactions on Broadcast & Television Recevers", August 1972, BTR 18, No. 3, pages 177-182. use. A diode D ₂ having the same conducting direction as the collector current of the transistor is disposed in series between the point A and the transistor Tr, and the primary winding L ₁ of the transformer T is supplied with the power source B And a junction between the transistor Tr and the diode D ₂ . The series circuit arrangement between the diode D ₃ and the secondary winding L ₄ of the transformer T is arranged between the point A and the ground, and the cathode of the diode P ₃ is placed at the point A. Connect. As shown in the figure, the polar direction of the winding of the transformer T is indicated by a dot. The driving circuit Dr can be provided with a comparison stage and a modulator to control the conduction time of the transistor Tr.

In the embodiment of FIG. 3, when the voltage at the junction of the coil Ly and the capacitor Ct is supplied to the comparison terminal of the driving circuit Dr through the low pass filter F, the variation of the voltage V _B and The peak value of the voltage V _A can be kept constant despite the frequency modulation of the voltages V and V '. This filter is shown in dashed lines in the figure. The output signal from the low pass filter F is actually the average value of the voltage V + V '.

For this reason, the condition is that the filter F does not pass the line frequency component but passes the existing feed frequency component. In this way, the voltage V _A can be supplied to the filter F.

In the embodiment of FIG. 3, control is performed. The reason is that the voltage between both terminals of the secondary winding L ₅ of the transformer T is rectified by using the peak rectifiers D ₄ and C ₂ , and the DC voltage thus obtained is supplied to the driving circuit Dr so that the transistor This is because the conduction time of (Tr) is controlled. The amplitude of the voltage between both terminals of the winding L ₅ and thus the amplitude of the voltage V _A proportional thereto is kept constant by controlling the above-described conduction time. In this way, the voltage V _A may be supplied to the peak rectifier.

In the embodiments of FIG. 2 and FIG. 3, predetermined fluctuations may be made to the voltage V _A by controlling the circuits S and Dr. FIG. The present invention can also be used in the embodiment of FIG. 4A in which the left portion (not shown) of the point A can be formed as in the case of FIG. 1 or FIG. In FIG. 4a, the linear deflection coil Ly is divided into two equally coiled portions Ly ₁ and Ly ₂ and each of these coils is divided into two identical networks d ₁ , Cr ₁ , Ly ₁ , Ct ₁ and d. ₂ , Cr ₂ , Ly ₂ , Ct ₂ ). Original modulating these networks and (M ₁₎ a capacitor (C't) with simultaneous correction of the network are connected in parallel _{(D 1 ', Cr',} L ', C't) and connected in parallel. The modulation source (M ₂ ) is connected in parallel with the capacitor (Ct ₂ ) to vary the voltage between the terminals of the capacitor, so that the correction difference current (ik) is applied to the deflection current (iy) at one coil _half (eg, Ly ₁ ). At the same time, the other coil _half (eg, Ly ₂ ) generates a four-pole correction that eliminates the deflection error.

Such four theaters are described in the specification of US Patent No. 3,440,483, in which case the instantaneous intensity of the current ik is proportional to the product of the instantaneous strengths of the two deflection currents. In this case, the deflection error of anisotropic astigmatism can be eliminated. The peak value of the voltage V _A between both terminals of the serial arrangement of these three networks is kept constant as described with reference to FIGS. 1, 2 and 3.

The embodiment of FIG. 4A has the drawback that the direct current component of the correction current ik flows through the coil _half Ly ₂ and does not flow through the other coil _half Ly ₁ which causes an error. In the embodiment of FIG. 4B, such a defect can be eliminated. In other words in this embodiment, the modulation source (M ₂₎ the area wookeu (L ₆₎ a via a diode (d ₁ and d ₂₎ also connected to the junction and at the same time one block line frequency signal as a coil (L ₆₎ of the blood Ile frequency Do not block the signal. The output voltage from the modulation source M ₂ has a sawtooth wave shape of the feed frequency. A capacitor Ct ₂ is provided between the junction of the coil L ₆ and the coils Ly ₁ and Ly ₂ to form part of two networks as this capacitor. A feed frequency modulated line frequency pulsating wave voltage is generated at junctions of diodes d ₁ and d ₂ . The envelope of the retrace voltage between both terminals of the diode (eg d ₂ ) is a sawtooth wave, and the envelope of the retrace voltage between both terminals of the other diode (eg d ₁ ) increases and It is sawtooth wave. The sum of these voltages shown in the figures is substantially constant. The current generated by these voltages passing through the coils Ly ₁ and Ly ₂ is proportional to the integral of the line frequency voltage between both terminals of the coil and is sawtooth shaped. These currents thus become predetermined currents (iy + ik and iy-ik). It is also apparent that other known correction difference currents can be generated in a similar manner.

5 shows a modified embodiment of the apparatus of the present invention, which is configured to generate a current for the vertical direction correction, the so-called North-North Correction, of the image displayed from the circuit apparatus of the present invention. Doing. The deflection network (D, Cr, Ly, Ct) is connected in series with the east-west correction network (D ', Cr', L ', Ct') and the third network (D ", C" r, L ", Ct). Connect in series with "). The modulation source M ₂ is forwarded in parallel with a capacitor C "t having a feed frequency sawtooth signal and the modulation source M ₁ has a capacitor C't and C" t having a feed frequency parabolic signal. Continue in parallel with the series circuit of. The sum of the voltages between both terminals of the capacitors Ct, C't and C "t is constant (a constant DC voltage component of = voltage (V _A )), and moreover the amount of capacitors C't and C" t. Since the sum of the voltages between the terminals changes parabolic, the voltage between both terminals of the capacitor Ct changes parabolic, and this voltage does not contain any sawtooth wave component. Therefore, the saw-wave component of the feed frequency does not exist in the line deflection current. A line frequency pulsating wave voltage with a feed frequency sawtooth envelope occurs between both terminals of the winding L ″ ₂ coupled to the winding L ″ ₁ . The line frequency pulsating wave voltage having a constant amplitude formed by the winding L ₇ of the transformer T is subtracted from the above-mentioned voltage. These waveforms are as shown in FIG. The winding L ″ ₂ is connected in series with the feed deflection coil L'y and the coil L ₈ in contact with the feed deflection current generator 11. One end of the capacitor C ₃ is coiled ( connected to the junction of L and L'y ₈₎ and, and simultaneously grounding the other terminal of the capacitor, the generator (1 ") coil (1'y) connection terminals frequency signal absorption circuit (13 a line of the) grounded via a and a ground via the winding (L _"2) and the coil (L ₈₎ to avoid the winding of Ile frequency signals with a junction point (L _2" and L ₇₎ (absorption circuit). winding (L ₂ " ) And the voltage present between the junction of the coil L ₈ is the line frequency pulsating plate voltage with a feed frequency sawtooth envelope that becomes zero in the middle of the feed trace time. A line frequency sinusoidal voltage having a feed frequency sawtooth envelope is generated between both terminals of the capacitor C ₃ by a known method, which generates a cosine current in the feed deflection coil L'y. This current is superimposed on the feed deflection current and becomes a predetermined parabolic. Thus, this current becomes the north-south correction current.

In the above embodiment, no requirements are required except for the capacitors Ct and C't so that their impedance is not too small at the feed frequency. In practice, so-called S correction is performed using the capacitor Ct. For example, in the magazine "Philps Application Information No. 268 All Trans: istor 100 ° Colour Televsion, the linearity of the line deflection is improved by modulating the S correction more east-west than the deflection current that can be achieved with the same embodiment as in FIG. It is known that in this figure the capacitor C't forms part of the two networks D, Cr, Ly, Ct and D ', Cr, L', Ct ', while the benzoone ( M ₁ ) is connected to the junction of diodes D and D 'via coil Lp The capacitance ratio of capacitors Ct and C't can be obtained by modulating S correction as required. It is determined by the geometrical characteristics of the television receiver.

The embodiment in FIG. 1 is not possible in this case. This is because the junction of the capacitor Ct and the coil L 'is grounded during the sun trace time.

This is different from the case of the embodiment of FIG. 6 having a capacitor C't. As in the case of the embodiment of FIG. 4B, no direct current flows through the coil L 'shown in FIG.

In the above-described embodiment, no inductor connected between the point A and the positive terminal of the power source B, that is, connected in parallel to the network is not considered. As long as this inductor has a large impedance at the line frequency, this inductor need not be considered. However, if there is a non-negligible parasitic capacitance between the terminals of this inductor, for example, choke L _{3 of} FIG. 2, the above-described parallel impedance cannot be considered to be infinitely large. And this parasitic capacitance is generated by the circuit arrangement around the switch such as transistor Tr or thyrister and EHT rectification circuit. As a result, the resonant frequencies of each network no longer have the same value, resulting in the same retrace time of these circuits.

When the resonant frequency of the circuit composed of the above-described inductor and the capacitance existing between both terminals of the inductor is equal to the resonant frequency of the network, these retrace times become equal.

However, since the actual capacitance Cp is large, the aforementioned resonance frequency is very low. During the retrace time, the capacitance Cp and the primary inductor Lp of the transformer T of FIG. 1 are in series circuit arrangements Cr, C'r and Ly, L '(capacitors Ct and Ct'It's so big that it has no inherent effect). Since the condenser voltage divider is formed with the capacitors Cr and C'r, a circuit having an inductive voltage divider can be used instead of using the circuit described above. This is illustrated well in the embodiment of FIG. The capacitor C ₄ is disposed between the point A and the ground, and the capacitor C ₅ is disposed between the middle tap of the winding L ₁ and the junction point of the diodes D and D '. In this case, the capacitors Cr and Cr 'are omitted. The position of the capacitor intermediate tap of the capacitors C ₄ and C ₅ can be determined as a simple method in consideration of the capacitors Cp and the capacitors Cr and C'r. The capacitors C ₄ and C ₅ serve as retrace capacitors of two networks.

In the embodiment in FIG. 7, the series circuit arrangements Ly and Ct are connected to the middle tap of the coil L 'without connecting to the junction of the elements Ct' and L '. This is because east-west modulation is most severe in the middle of the feed trace time. In addition, as described above, when the S correction is modulated more than the deflection current, the current flowing through the diode D 'can be made negative without going through this step. That is, the conduction of the diode D 'can be stopped. In the case of using the above-described steps, a current flows through this diode, which is the sum of the current in the original embodiment and the current proportional to the current iy, so that the current has a higher intensity. Big. The position of the intermediate tap can be determined so that the conduction of the diode D 'continues under any condition during the first half of the sun trace time. Such a step may be performed in the embodiments of FIGS. 4B and 6 in which the retrace capacitor is formed as in the embodiment of FIG. 7 or in another method (for example, the capacitor and the coil L connected in parallel with the coil Ly). It is a matter of course that the present invention can also be applied to the embodiment of the invention) formed by a capacitor connected between the middle tab of the ')' and the ground.

Claims (1)

It has a diode and a coil, which has a sawtooth circuit which acts with the trace capacitor during the trace time of the sawtooth current and with the retrace capacitor during the retrace time. In the arrangement of the sawtooth wave deflection current generating circuit having the switching device interrupted in time, at least one second sawtooth wave circuit having a second coil and a second diode which works together with the second trace capacitor and the second retrace capacitor is provided. The retrace time of the current flowing through the second coil is approximately equal to the retrace time of the deflection current, and the two sawtooth circuits are interconnected to each other so that the two diodes are in series with each other. In the same conduction direction, a series arrangement of these two diodes Connected in series, and saw-tooth arrangement deflection current generating circuit, it characterized in that the enabling control the voltage across the trace capacitor the terminals as the control element.

Images