KR20240134374A - 3D memory device and method for forming the same - Google Patents

Abstract

A 3D memory device includes memory arrays stacked in a first direction. Each memory array includes a stack structure including interleaved conductive layers and a first dielectric layer extending in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions. The conductive layers include a word line and a drain select gate line, and the drain select gate line is separated by the second dielectric layer in the second direction.

Description

3D memory device and method for forming the same

This application claims priority to Chinese application No. 202210202193.3, filed March 3, 2022, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a memory device and a method of forming a memory device.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar process and manufacturing technology become difficult and expensive. As a result, the memory density of the planar memory cell approaches the upper limit.

A three-dimensional (3D) memory architecture can solve the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuits that facilitate the operation of the memory array.

In one aspect, a 3D memory device is disclosed. The 3D memory device includes memory arrays stacked in a first direction. Each memory array includes a stack structure including interleaved conductive layers and a first dielectric layer extending in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions. The conductive layers include a word line and a drain select gate line, wherein the drain select gate line is separated by the second dielectric layer in the second direction.

In some implementations, each memory array further includes a first channel structure extending in a first direction through the word line and the drain select gate line.

In some implementations, each memory array further includes a second channel structure extending in the first direction through the word line.

In some implementations, the second dielectric layer is disposed over the second channel structure.

In some implementations, the first length of the first channel structure in the first direction is longer than the second length of the second channel structure in the first direction.

In some implementations, each memory array further includes a first semiconductor layer disposed over the first channel structure and a second semiconductor layer disposed over the second dielectric layer.

In some implementations, the memory array includes a first memory array and a second memory array disposed over the first memory array, wherein in a plan view of the 3D memory device, a second dielectric layer of the first memory array at least partially overlaps a second dielectric layer of the second memory array.

In some implementations, in a plan view of the 3D memory device, the second semiconductor layer of the first memory array at least partially overlaps the second semiconductor layer of the second memory array.

In some implementations, the first channel structure of the second memory array is in contact with the first semiconductor layer of the first memory array.

In some implementations, the second channel structure of the second memory array is in contact with the second semiconductor layer of the first memory array.

In some implementations, a top surface of the first semiconductor layer is coplanar with a top surface of the second semiconductor layer in the second direction.

In another aspect, a system is disclosed. The system includes a 3D memory device configured to store data and a memory controller. The 3D memory device includes memory arrays stacked in a first direction. Each memory array includes a stack structure including interleaved conductive layers and a first dielectric layer extending in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions. The conductive layers include a word line and a drain select gate line, the drain select gate line being separated by the second dielectric layer in the second direction. The memory controller is coupled to the 3D memory device and is configured to control operation of the channel structure via the select gate line and the word line.

In another aspect, a 3D memory device is disclosed. The 3D memory device includes a first stack structure including interleaved first conductive layers and a first dielectric layer extending in a first direction and a second direction perpendicular to the first direction, first channel structures extending in a third direction perpendicular to the first direction and the second direction through the first stack structure, interleaved second conductive layers and a second dielectric layer extending in the first direction and the second direction, a second stack structure disposed over the first stack structure, second channel structures extending in the third direction through the second stack structure, a first cutting structure disposed between the first channel structures, and a second cutting structure disposed between the second channel structures.

In some implementations, the 3D memory device further includes a first dummy channel structure extending within the first stack structure in a third direction, and a second dummy channel structure extending within the second stack structure in the third direction over the first dummy channel structure. The first cut structure is disposed between the first dummy channel structure and the second dummy channel structure.

In a plan view of the 3D memory device, the first dummy channel structure, the first cut structure, and the second dummy channel structure can at least partially overlap.

In some implementations, the first conductive layer of the first stack structure includes a word line and a drain select gate line, and the drain select gate line is separated by the first cut structure.

In some implementations, the second conductive layer of the second stack structure includes a word line and a drain select gate line, and the drain select gate line is separated by the second cut structure.

In some implementations, the first cut structure includes a third dielectric layer.

In some implementations, the 3D memory device further includes a semiconductor layer disposed between the first cut structure and the second dummy channel structure.

In some implementations, the semiconductor layer is a doped semiconductor layer.

In another aspect, a system is disclosed. The system includes a 3D memory device configured to store data and a memory controller. The 3D memory device includes a first stack structure including interleaved first conductive layers and a first dielectric layer extending in a first direction and a second direction perpendicular to the first direction, first channel structures extending in a third direction perpendicular to the first direction and the second direction through the first stack structure, interleaved second conductive layers and a second dielectric layer extending in the first direction and the second direction, a second stack structure disposed over the first stack structure, second channel structures extending in the third direction through the second stack structure, a first cut structure disposed between the first channel structures, and a second cut structure disposed between the second channel structures. The memory controller is coupled to the 3D memory device and is configured to control operation of the channel structures via a select gate line and a word line.

In another aspect, a method of forming a 3D memory device is disclosed. A first memory array is formed including a first cut structure between first channel structures. A second memory array is formed over the first memory array. The second memory array includes a second cut structure between second channel structures.

In some implementations, a first dielectric stack is formed including interleaved first dielectric layers and a first sacrificial layer stacked in a first direction. First channel structures are formed through the first dielectric stack in the first direction. A first cut structure is formed on a topmost layer of the first sacrificial layer. The first sacrificial layer is replaced with a first conductive layer.

In some implementations, a second dielectric stack is formed on the first memory array, the second dielectric stack including interleaved second dielectric layers and a second sacrificial layer stacked in a first direction. Second channel structures are formed through the second dielectric stack in the first direction. A second cut structure is formed on an uppermost layer of the second sacrificial layer.

In some implementations, the second sacrificial layer is replaced by a second conductive layer.

In some implementations, a first stack structure is formed including a first word line and a first drain select gate line, and the first word line and the first drain select gate line are stacked in a first direction. A first cut structure is formed to cut the first drain select gate line. First channel structures are formed to extend in the first direction within the first stack structure.

In some implementations, a second stack structure is formed on the first stack structure, the second stack structure including a second word line and a second drain select gate line, the second word line and the second drain select gate line being stacked in a first direction. A second cutting structure is formed that cuts the second drain select gate line. Second channel structures are formed to extend in the first direction within the second stack structure.

In some implementations, the semiconductor layer is formed on the first channel structure.

In some implementations, the second cut structure is formed to at least partially overlap the first cut structure in the plan view of the 3D memory device.

In some implementations, a third memory array is formed over the second memory array, and the third memory array includes a third cut structure between the third channel structures.

In a plan view of the 3D memory device, the first cut structure, the second cut structure, and the third cut structure at least partially overlap.

The accompanying drawings, which are incorporated in and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, serve to further explain the disclosure and to enable a person skilled in the art to make and use the present disclosure.
Figures 1a and 1b illustrate schematic diagrams of a cross-section of a 3D memory device.
FIGS. 2A through 2F illustrate schematic diagrams of cross-sections of 3D memory devices according to some aspects of the present disclosure.
FIG. 3 illustrates a block diagram of a system having a memory device according to some aspects of the present disclosure.
FIG. 4a illustrates a diagram of a memory card having a memory device according to some aspects of the present disclosure.
FIG. 4b illustrates a diagram of a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure.
FIG. 5 illustrates a diagram of a memory device having peripheral circuitry according to some aspects of the present disclosure.
FIG. 6 illustrates a block diagram of a memory device having peripheral circuitry according to some aspects of the present disclosure.
FIG. 7 illustrates a flowchart of a method for forming a 3D memory device according to some aspects of the present disclosure.
FIGS. 8A through 8F illustrate manufacturing processes for forming a 3D memory device according to some aspects of the present disclosure.
FIG. 9 illustrates a flowchart of a method for forming a 3D memory device according to some aspects of the present disclosure.
The present disclosure is described with reference to the attached drawings.

In general, a term can be understood, at least in part, by its usage in a context. For example, the term "one or more" as used herein can be used, at least in part, to describe any feature, structure, or characteristic in the singular, or can be used, depending on the context, to describe a combination of features, structures, or characteristics in the plural. Likewise, terms such as "a," "an," or "the" can be understood, at least in part, to convey either a singular usage or a plural usage, depending on the context. Additionally, the term "based on" is not necessarily intended to convey an exclusive set of factors, but instead can be understood, at least in part, to allow for the presence of additional factors that need not be explicitly described, depending on the context.

It should be readily understood that the meaning of "on", "above" and "over" in this disclosure is to be interpreted in the broadest sense so that "on" means not only "directly above", but also means that there are intermediate features or layers therebetween, and that "on" or "over" should be interpreted in the broadest sense to include not only the meaning of "upon" or "over", but also "over" or "up" (i.e., directly above something) without any intermediate features or layers therebetween.

Additionally, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used for convenience of description to describe one element or a feature's relationship to another element(s) or feature(s) as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptions used herein may likewise be interpreted accordingly.

In this specification, the term "layer" means a portion of material that includes a region having a thickness. The layer may extend throughout the entirety of an underlying or overlying structure, or may have a thickness less than that of the underlying or overlying structure. Additionally, the layer may be a region of a homogeneous or non-uniform continuous structure having a thickness less than that of the continuous structure. For example, the layer may be located between a top surface and a bottom surface of the continuous structure, or between any pair of horizontal planes on that surface. The layer may extend along horizontal, vertical, and/or tapered surfaces. The substrate may be a layer, and may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (wherein interconnect lines and/or via contacts are formed) and one or more dielectric layers.

The term "substrate" as used herein means a material to which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

As used herein, the term "3D memory device" refers to a semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) on a laterally oriented substrate such that the memory strings extend perpendicular to the substrate. The term "vertically/vertically" as used herein means nominally perpendicular to a lateral surface of the substrate.

In some 3D memory devices, such as 3D NAND memory devices, a stack of gate electrodes may be arranged over a substrate, and a plurality of semiconductor channels may be arranged to pass through and cross a word line and be implanted into the substrate. The bottom/lower gate electrode or electrodes function as a source select gate line, which is also referred to as a bottom select gate (BSG) in some cases. The top/upper gate electrode or electrodes function as a drain select gate line, which is also referred to as a top select gate (TSG) in some cases. A gate electrode between the top/upper select gate electrode and the bottom/lower gate electrode functions as a word line (WL). The intersection of the word line and the semiconductor channel forms a memory cell.

FIGS. 1A and 1B illustrate schematic diagrams of a cross-section of a 3D memory device. Referring to FIG. 1A , in some implementations, the 3D memory includes a substrate (100), a first stack structure (110a) and a second stack structure (110b) stacked in a direction perpendicular to the substrate (100). The second stack structure (110b) further includes a TSG (111) positioned on a side of the second stack structure (110b) that is relatively distant from the substrate (100), a first channel structure (130a) penetrating the first stack structure (110a), and a second channel structure (130b) penetrating the second stack structure (110a). The first channel structure (130a) is electrically connected to the second channel structure (130b). A TSG cut line (120) separates the TSG (111). In some implementations, the TSG cut line (120) may be referred to as a dielectric layer or a cut structure.

Referring to FIG. 1B, the 3D memory device may include a plurality of stack structures, such as a third stack structure, a fourth stack structure, and an nth stack structure (n is a natural number). The nth stack structure is a stack structure that is relatively distant from the substrate (100), and the TSG (111) is positioned in the nth stack structure. In some implementations, the 3D memory device may include a third channel structure, a fourth channel structure, and an nth channel structure, where n is a natural number.

In some implementations, as illustrated in FIG. 1b using n=3 as an example, the first channel structure (130a), the second channel structure (130b), and the third channel structure (130c) are arranged in a stacked manner and are electrically connected to each other. In some implementations, the TSG cut line (120) may be arranged only in the third stack structure (110c), and the first stack structure (110a) and the second stack structure (110b) may not be provided with the TSG cut line. In some implementations, the TSG cut line (120) penetrates the TSG (111) to divide the memory device into different memory blocks. The first channel structure (130a), the second channel structure (130b), and the third channel structure (130c) are stacked and electrically connected to each other, and the first channel structure (130a), the second channel structure (130b), and the third channel structure (130c) are arranged in the same memory block.

When performing layer-by-layer read/write/erase operations on a single memory block, three channel structures stacked on the same memory block must operate. As the number of memory layers of the memory block increases, the internal resistance also increases, and the operating voltage of the read/write/erase operations must be increased to meet the operating requirements. Therefore, due to the increase in the operating voltage, programming interference between memory blocks increases, and each memory block cannot be accurately controlled, thereby reducing the stability of the memory device. The present disclosure provides a 3D memory device and a manufacturing method for solving at least one or more of the above problems.

FIG. 2A illustrates a schematic diagram of a cross-section of a 3D memory device according to some aspects of the present disclosure. As depicted in FIG. 2A, the 3D memory device includes a substrate (100) and at least two memory arrays stacked in a direction perpendicular to the substrate (100). In some implementations, each memory array includes a stack structure (110), the stack structure (110) including a TSG (111), the TSG (111) positioned on an opposite side of the stack structure (110) from the substrate (100). Each memory array further includes a plurality of channel structures (130) penetrating the stack structure (110) and a TSG cut line (120) separating the TSGs (111). The TSG cut line (120) is positioned between two adjacent channel structures (130) in a direction parallel to the substrate (100). The channel structures (130) are arranged in a stacked manner in the at least two memory arrays and are electrically connected.

In some implementations, the material of the substrate (100) may include single crystal silicon (e.g., silicon or germanium), a III-V semiconductor material, a II-VI semiconductor material, an organic semiconductor material, or other suitable semiconductor material. In some implementations, the material of the TSG (111) may include, but is not limited to, tungsten, cobalt, nickel, titanium, polysilicon, or other suitable material. In some implementations, the material of the TSG cut line (120) may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable material.

It is understood that the memory array of the present disclosure is not limited to the three layers illustrated in FIG. 2a, and a different number of memory arrays may be stacked depending on design and process requirements. In each memory array, the stack structure includes alternately stacked gate layers and insulating layers, the gate layers serve as word lines of the memory array, and read/write/erase operations can be implemented by applying different control voltages to the word lines. In some implementations, the number of gate layers of the stack structure may include 8 layers, 16 layers, 32 layers, 64 layers, 96 layers, 128 layers, and the like, and the implementation of the present disclosure is not particularly limited thereto.

In some implementations, each stack structure (110) of each memory array can have a TSG (111), and the TSG (111) can be a conductive layer parallel to the substrate (100), and a plurality of channel structures (130) can share the same TSG (111). The TSG (111) acts as a control gate of the top select transistor, and the top select transistor is turned on or off by controlling the voltage of the TSG (111) to control the channel structure (130) to implement read/write/erase operations. The TSG (111) is divided into two electrically insulated regions by a TSG cut line (120) penetrating the TSG (111), so that each memory array is divided into two electrically insulated memory blocks (210).

As illustrated in FIG. 2b, each memory block (210) may include one or more channel structures (130). In some implementations, one TSG cut line (120) is disposed in each memory array. It is understood that the number of TSG cut lines (120) is not limited to one as illustrated in FIG. 2a, and may be changed to multiple TSG cut lines (120) that divide the memory array into multiple memory blocks.

As illustrated in FIG. 2a, memory arrays are stacked in the Z direction, and channel structures (130) of adjacent memory arrays are stacked in the Z direction. Adjacent stacked channel structures (130) are electrically connected in the Z direction. The electrical connection method may include direct contact between two adjacent channel structures (130) along the Z direction to form an electrical connection, or may include providing a conductive structure (e.g., a conductive portion (140)) between two adjacent channel structures in the Z direction, wherein the conductive structure makes direct contact with two adjacent channel structures (130).

In some implementations, the memory arrays are stacked in a direction perpendicular to the substrate, each memory array is provided with a TSG cutting line, and the TSG of each memory array is divided into a plurality of regions that are insulated from each other. By controlling on and off of the upper select transistor of the memory array, the memory blocks of each memory array can be independently controlled. For example, when a read/write/erase operation is performed on a memory block of the n-th memory array, the memory block of the (n+1)-th memory array may not be used to perform the read/write/erase operation.

By utilizing this structure, the number of memory blocks can be increased in the direction perpendicular to the substrate while increasing the number of memory layers, thereby defining more memory blocks on the same substrate to obtain more precise control over the memory device. Compared to the prior art in which channel structures stacked on each other constitute a memory block, the present disclosure reduces the number of memory layers of each memory block, thereby reducing the internal resistance of the memory block and reducing programming interference between the memory blocks. In addition, when performing a read/write/erase operation on the memory block, the number of times the memory unit is executed can be reduced because the number of memory layers is reduced, thereby further extending the life of the memory device.

In some implementations, a plurality of memory arrays are stacked to increase the number of memory layers, and a TSG cut line is provided for each memory array, and each memory array is divided into insulated memory blocks. The total number of memory layers is increased, and the memory blocks included in each memory array of the stacked memory arrays can independently perform read/write/erase operations, thereby facilitating more precise control of the memory device and improving operational efficiency. In addition, by reducing the number of memory layers of the memory blocks in each memory array, programming interference between the memory blocks can be reduced, the number of times the memory unit performs read/write/erase operations can be reduced, the lifespan of the memory device can be shortened, and the stability of the memory device is improved.

In some implementations, as illustrated in FIG. 2A, the 3D memory device further includes a semiconductor layer, e.g., a conductive portion (140), positioned between two adjacent memory arrays and configured to electrically connect the two stacked channel structures (130). In the Z direction, the conductive portion (140) is positioned between the two adjacent channel structures (130) and contacts an upper end of one channel structure (130) and a lower end of one channel structure (130), thereby electrically connecting the two channel structures (130). In some implementations, the two channel structures (130), which are positioned at the upper end and the lower end of the conductive portion (140), respectively, need not be perfectly aligned. In some implementations, the critical dimensions (diameters) of the top and bottom of the same channel structure (130) do not need to be completely consistent, and the electrical connection of the two channel structures (130) can be formed simply by contacting the conductive portions (140). By utilizing the conductive portions (140), the electrical connection area can be increased, the difficulty of the alignment process between the two stacked channel structures (130) can be reduced, and the manufacturing process window of the channel structure (130) can be increased.

In some implementations, the material of the conductive portion (140) can include tungsten, cobalt, nickel, titanium, polysilicon, or other suitable materials. As illustrated in FIG. 2A, the material of the semiconductor channel (131) in the channel structure (130) can include polysilicon, and the material of the conductive portion (140) can be the same as the semiconductor channel (131), which increases the adhesion between the conductive portion (140) and the semiconductor channel (131) of the channel structure (130) and reduces the contact resistance, thereby improving the electrical connection performance.

In some implementations, the polysilicon material of the conductive portion (140) may also be ion-doped to increase the carrier density of the conductive portion (140) and improve conductivity. In some implementations, n-type doping may be performed on the polysilicon of the conductive portion (140).

In some implementations, as illustrated in FIG. 2a, projections of TSG cut lines (120) of at least two memory arrays may overlap in a direction perpendicular to the substrate (100). Each TSG cut line (120) cuts the TSG (111) to divide each memory array into two memory blocks, thereby enabling separate read/write/erase operations for the memory blocks included in each memory array. The positions of the TSG cut lines (120) in each memory array may be different from, but are not limited to, the positions of the TSG cut lines (120) in other memory arrays.

In some implementations, since the projections of the TSG cut lines (120) in each memory array overlap, the formation positions of the TSG cut lines (120) in each memory array become the same, thereby reducing manufacturing costs. In some implementations, in the process of forming the TSG cut lines (120) on top of different memory arrays, the positions of the TSG cut lines (120) can be determined using a photoetching development technique, and the TSG cut lines (120) in the same position can use the same mask, thereby reducing manufacturing costs.

In some implementations, as illustrated in FIG. 2a, the stack structure (110) may further include alternately stacked gate layers (112) and insulating layers (113), wherein the insulating layers (113) electrically insulate the TSG (111) from the adjacent gate layers (112). In some implementations, the memory array further includes a dummy channel structure (150) penetrating the gate layers (112) and insulating layers (113) and positioned beneath the TSG cut lines (120).

In some implementations, the material of the gate layer (112) may include tungsten, cobalt, nickel, titanium, polysilicon, or other suitable material. In some implementations, the material of the insulating layer (113) may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable material.

A dummy channel structure (150) is positioned below a TSG cut line (120), and the dummy channel structure (150) of an adjacent memory array is electrically insulated by the TSG cut line (120), and a read/write/erase operation is not performed on the dummy channel structure (150). The dummy channel structure (150) is used to support the stack structure (110). The dummy channel structure (150) may have the same structure as the channel structure (130) and may be formed simultaneously with the channel structure (130), so that the process steps may be simplified and the manufacturing cost may be reduced.

In some implementations, as illustrated in FIG. 2A, the dummy conductive portion (180) can be positioned between adjacent memory arrays in the Z direction perpendicular to the substrate (100), and the dummy conductive portion (180) can be positioned between adjacent TSG cut lines (120) and dummy channel structures (150). In the Z direction perpendicular to the substrate (100), a projection of the dummy conductive portion (180) can overlap a projection of the TSG cut lines (120). The dummy conductive portion (180) is not used as an electrical connection to the dummy channel structure (150), but is used to support the dummy channel structure (150). The dummy conductive portion (180) can be formed simultaneously with the conductive portion (140), which can simplify the forming process and reduce manufacturing costs.

In some implementations, as illustrated in FIG. 2c, since the dummy channel structure (150) and the dummy conductive portion (180) are used to support the 3D memory device, there is no need to serve as an electrical connection. Therefore, in some implementations, the dummy conductive portion (180) can be omitted and only the dummy channel structure (150) can be provided, thereby reducing manufacturing costs.

As illustrated in FIG. 2c, multiple stack structures stacked in the Z direction are expressed with different labels to distinguish their related positions. For example, stack structures (110a), stack structures (110b), and stack structures (110c) are illustrated in FIG. 2c, and stack structures (110a), stack structures (110b), and stack structures (110c) may have the same structure but may be arranged at different positions.

In some implementations, the bottom of the dummy channel structure (150) may be in direct contact with the TSG cut line (120). The bottom of the dummy channel structure (150) may extend into the insulation layer between two adjacent stack structures and not contact the TSG cut line (120). For example, as illustrated in FIG. 2c, the bottom of the dummy channel structure (150) located in the stack structure (110b) is in direct contact with the TSG cut line (120) of the stack structure (110a). As another example, as illustrated in FIG. 2c, the bottom of the dummy channel structure (150) of the stack structure (110c) may extend only into the insulation layer between the stack structure (110c) and the stack structure (110b).

In some implementations, as illustrated in FIG. 2d, the 3D memory device is supported by a gate layer (112) and an insulating layer (113), and the dummy channel structure (150) and the dummy conductive portion (180) illustrated in FIGS. 2a and 2c may be omitted to reduce manufacturing costs.

As illustrated in FIG. 8a, in a manufacturing process of a stack structure (110), a stack structure (170a) formed by alternately stacking gate sacrificial layers (172) and insulating layers (173) may be first formed, and then the gate sacrificial layer (172) of the stack structure (170a) may be removed to form a gap, and then a gate layer (112) may be formed in the gap, for example, in the stack structure (110) illustrated in FIGS. 2a to 2d. In other words, the stack structure (110) may be formed by a gate-after process. When the gate sacrificial layer (172) is removed, in order to prevent collapse and deformation of the insulating layer (173) (i.e., the insulating layer (113) of FIGS. 2c and 2d), a dummy channel structure (150) is formed to support the 3D memory device and improve device yield.

In some implementations, the stack structure (110) can be formed by alternately stacking gate layers (112) and insulating layers (113) without forming the gate sacrificial layer (172), and the stack structure (110a) can be formed by a gate-first process. In some implementations, the arrangement of the dummy channel structure (150) of FIG. 2c can be omitted, and the gate layer (112) and insulating layer (113) of the stack structure (110) can be supported, thereby reducing the manufacturing cost.

In some implementations, as illustrated in FIG. 2b, the memory array further includes at least two gate line slit (GLS) structures (160), the GLS structures (160) being arranged in parallel. Each GLS structure (160) penetrates the stack structure, and at least one TSG slit line (120) is disposed between two adjacent GLS structures (160). A channel structure (130) is disposed between the GLS structure (160) and the TSG slit line (120).

In some implementations, each memory array includes at least two GLS structures (160) penetrating the stacked structures (110). In the Z direction perpendicular to the substrate (100), the projections of the GLS structures (160) of two adjacent memory arrays overlap each other. In some implementations, multiple stacked memory arrays share multiple GLS structures (160). For example, as an example with one GLS structure (160), in the direction perpendicular to the substrate (100), the GLS structure (160) is configured to penetrate all of the stacked structures (110).

In some implementations, a GLS structure (160) penetrating the stack structure (110) divides the memory array into different memory regions, and channel structures (130) located in the middle of two GLS structures (160) together form a memory region. The GLS structure (160) may serve as an insulating structure that insulates and supports the memory array. The GLS structure (160) may also include a conductive core portion for supplying power to a common source electrode of the channel structure (130). A TSG cut line (120) is disposed between two adjacent GLS structures (160), and the memory region is further divided into different sub-arrays, each sub-array being a memory block (210), and each memory block (210) can independently perform read/write/erase operations.

It should be understood that the number of GLS structures (160) and TSG cut lines (120) illustrated in the present disclosure is merely exemplary, and that the number of GLS structures (160) and TSG cut lines (120) may be set differently to divide the memory array into a plurality of memory blocks, and each memory block may include one or more channel structures depending on design requirements and manufacturing processes. Therefore, the division and independent control of the memory blocks can achieve finer programming control for the memory device and improve operational efficiency. In addition, the number of simultaneously controlled channel structures is reduced, so that programming interference of the memory device is reduced, and the stability of the memory device is improved.

As illustrated in FIG. 2b, the channel structures (130) between two adjacent GLS structures (160) are periodically arranged in an array manner. The TSG cut line (120) and the GLS structures (160) divide the array into sub-arrays, and each sub-array has the same number of channel structures (130). Since the channel structures (130) between two adjacent GLS structures (160) are periodically arranged in an array manner, the layout density of the channel structures (130) can be increased, and the alignment and contact between the bit line and the top of the channel structure (s130) can also be facilitated.

As illustrated in FIG. 2b, in the X direction parallel to the substrate, the TSG cut lines (120) and the GLS structures (160) divide the memory array into different sub-arrays, and each sub-array can have the same number of channel structures (130), for example, four rows or eight rows. Each sub-array is arranged with the channel structures (130) having the same number of rows, which is advantageous for balancing the operating voltages of each sub-array, facilitating read/write/erase operations, and improving the stability of the memory device. A plurality of channel structures (130) and GLS structures (160) arranged along the extension direction of the TSG cut lines (120) form a row of the channel structures (130). For example, as illustrated by the dashed lines in FIG. 2b, a plurality of channel structures (130) arranged side by side along the Y direction may be referred to as a row of channel structures (130), and each sub-array includes four rows of channel structures (130). In some implementations, the Y direction may be an extension direction of a word line, and the X direction may be an extension direction of a bit line.

In some implementations, as illustrated in FIG. 2a, the channel structure (130) includes a semiconductor channel (131) and a memory film (132) surrounding the semiconductor channel (131). The semiconductor channels (131) arranged in a stacked manner in two adjacent memory arrays are electrically connected by conductive portions (140). The plurality of conductive portions (140) are electrically insulated from each other in a direction parallel to the substrate (100).

In the Z direction perpendicular to the substrate (100), adjacent stacked semiconductor channels (131) are electrically connected by conductive portions (140) to implement conduction of each semiconductor channel (131). The conductive portion (140) may include ion-doped polysilicon, and the doping type includes n-type doping to increase carrier density of the conductive portion (140) and improve conductivity. In some implementations, the Z direction may be an extension direction of the semiconductor channel (131).

FIG. 2E illustrates a schematic diagram of a channel structure (130) according to some aspects of the present disclosure. As illustrated in FIG. 2E, the memory film (132) includes a blocking layer (135), a storage layer (134), and a tunneling layer (133) along the radial direction of the channel structure (130). The blocking layer (135) may include silicon oxide, silicon oxynitride, a high-k material, or any combination thereof. The storage layer (134) may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling layer (133) may include silicon oxide, silicon oxynitride, or a combination thereof. In some implementations, the memory film (132) may be a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO).

In some implementations, the tunneling layer (133) is located between the semiconductor channel (131) and the storage layer (134). The storage layer (134) is also called a charge trapping layer, and the switching state of the semiconductor channel is determined by the storage or removal of charges in the charge trapping layer. Charges move between the storage layer (134) and the semiconductor channel (131) through the tunneling effect of the tunneling layer (133), thereby implementing turning on/off of the semiconductor channel (131), and implementing storage and erasure through programming. The storage layer (134) can store charges, and when the memory device is powered off, charges can be stored in the storage layer (134). The blocking layer (135) is located between the storage layer (134) and the gate layer for insulation. When the memory device is powered off, charges in the storage layer (134) are blocked from moving to the gate layer, thereby preventing data loss.

In some implementations, as illustrated in FIG. 2f, the 3D memory device includes a substrate (100); a first stack structure (110a) including a first TSG (111a), wherein the first TSG (111a) is positioned on a side of the first stack structure (110a) that is relatively distant from the substrate (100); a plurality of first channel structures (130a) penetrating the first stack structure (110a); a first TSG cut line (120a) dividing the first TSG (111a), wherein the first TSG cut line (120a) is positioned between two adjacent first channel structures (130a) in a direction parallel to the substrate; a second stack structure (110b) including a second TSG (111b), wherein the second TSG (111b) is positioned on a side of the second stack structure (110b) that is relatively distant from the substrate (100); A plurality of second channel structures (130b) penetrating the second stack structure (110b); a second TSG cutting line (120b) dividing the first TSG (111b), wherein the second TSG cutting line (120b) is positioned between two adjacent second channel structures (130b) in a direction parallel to the substrate, wherein the first stack structure (110a) and the second stack structure (110b) are stacked in a direction perpendicular to the substrate, and the stacked first channel structures (130a) are electrically connected to the second channel structures (130b).

In some implementations, as illustrated in FIG. 2f, in the Z direction perpendicular to the substrate (100), the second stack structure (110b) can be positioned over the first stack structure (110a). The first stack structure (110a) and the second stack structure (110b) illustrated in FIG. 2f are merely exemplary, and the 3D memory device may further include more stack structures. For example, in the Z direction, a third stack structure can be stacked on the second stack structure (110b), and a fourth stack structure can be stacked on the third stack structure. The number of stack structures is not limited in the present disclosure.

As illustrated in FIG. 2f, in the Z direction, the adjacent first and second channel structures (130a, 130b) are electrically connected. It is understood that the first channel structure (130a) and the second channel structure (130b) can be electrically connected by direct contact. For example, the semiconductor channel contacts in the first channel structure (130a) and the second channel structure (130b) are electrically connected. As another example, the electrical connection can also include providing a conductive structure (e.g., the conductive portion (140)) between the first channel structure (130a) and the second channel structure (130b) that are adjacent in the Z direction. The conductive structure is in direct contact with the first channel structure (130a) and the second channel structure (130b). It should be noted that the first channel structure (130a) and the second channel structure (130b) are both channel structures, and the structures can be the same or different, and their positions can also be different.

In some implementations, as illustrated in FIG. 2f, the 3D memory device may further include a conductive portion (140) positioned between the first stack structure (110a) and the second stack structure (110b) to electrically connect the first channel structure (130a) and the second channel structure (130b).

As illustrated in FIG. 2f, in the Z direction, the conductive portion (140) is formed between adjacent first channel structures (130a) and second channel structures (130b), and contacts the upper end of the first channel structure (130a) and the lower end of the second channel structure (130b), thereby implementing an electrical connection between the first channel structure (130a) and the second channel structure (130b). The conductive portion (140) can increase an electrical connection area between the first channel structure (130a) and the second channel structure (130b), reduce the difficulty of aligning the first channel structure (130a) and the second channel structure (130b), and facilitate expansion of a process window for forming the first channel structure (130a) and the second channel structure (130b).

In some implementations, as illustrated in FIG. 2f, in a direction perpendicular to the substrate (100), the projection of the first TSG cut line (120a) and the projection of the second TSG cut line (120b) may overlap. Since the formation location of the first TSG cut line (120a) in the first stack structure (110a) may be the same as the formation location of the second TSG cut line (120b) in the second stack structure (110b), the projections of the second TSG cut line (120b) and the first TSG cut line (120a) overlap in the Z direction. Therefore, in the manufacturing process of the first TSG cut line (120a) and the second TSG cut line (120b), the manufacturing cost can be reduced by using the same mask.

In some implementations, the 3D memory device may further include a first dummy channel structure (150a) penetrating the first stack structure (110a) and positioned below the first TSG cut line (120a); and a second dummy channel structure (150b) penetrating the second stack structure (110b) and positioned below the second TSG cut line (120b).

The first dummy channel structure (150a) and the second dummy channel structure (150b) are not used to store data, but are used to support the 3D memory device, thereby improving the structural stability of the memory device, reducing collapse and deformation conditions of the first stack structure (110a) and the second stack structure (110b), and improving the stability of the memory device.

FIG. 3 illustrates a block diagram of a system (300) having a memory device according to some aspects of the present disclosure. The system (300) may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As illustrated in FIG. 3 , the system (300) may include a memory system (302) having a host (308) and one or more memory devices (304) and a memory controller (306). The host (308) may be a processor of the electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host (308) may be configured to transmit or receive data to or from the memory device (304).

The memory device (304) may be any memory device disclosed in the present disclosure. As described in detail above, the memory device (304), such as a NAND flash memory device, may have a controlled and predefined discharge current in a discharge operation that discharges a bit line. In some implementations, a memory controller (306) is coupled to the memory device (304) and the host (308) and is configured to control the memory device (304). The memory controller (306) may manage data stored in the memory device (304) and communicate with the host (308). For example, the memory controller (306) may be coupled to the memory device (304) and the memory controller (306) may be configured to control operation of the channel structure via a peripheral device.

In some implementations, the memory controller (306) is designed to operate in low duty cycle environments, such as with secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the memory controller (306) is designed to operate in high duty cycle environments, such as with solid-state drives (SSDs) or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, enterprise storage arrays, and the like. The memory controller (306) can be configured to control operations of the memory device (304), such as read, erase, and program operations. The memory controller (306) may also be configured to manage various functions relating to data stored or to be stored in the memory device (304), including but not limited to bad-block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller (306) is further configured to process error correction code (ECC) with respect to data read from or written to the memory device (304). Any other suitable functions, such as formatting the memory device (304), may also be performed by the memory controller (306). The memory controller (306) may communicate with an external device, such as the host (308), according to a particular communication protocol. For example, the memory controller (306) may communicate with an external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a PCI (peripheral component interconnection) protocol, a PCI-E (PCI-express) protocol, an ATA (advanced technology attachment) protocol, a serial ATA protocol, a parallel ATA protocol, a SCSI (small computer small interface) protocol, an ESPI (an enhanced small disk interface) protocol, an IDE (integrated drive electronic) protocol, a Firewire protocol, and the like.

The memory controller (306) and one or more memory devices (304) may be integrated into various types of storage devices, and may be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package, for example. That is, the memory system (302) may be implemented and packaged into different types of end electronic products. In one example, as illustrated in FIG. 4A , the memory controller (306) and a single memory device (304) may be integrated into a memory card (402). The memory card (402) may include a PC card (PCMCIA, personal computer memory card international association), a CF card, a SM (smart media) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, or the like. The memory card (402) may further include a memory card connector (404) that couples the memory card (402) to a host (e.g., the host (308) of FIG. 3 ). In another example, as illustrated in FIG. 4b, a memory controller (306) and a plurality of memory devices (304) may be integrated into an SSD (406). The SSD (406) may further include an SSD connector (408) that couples the SSD (406) to a host (e.g., the host (308) of FIG. 3). In some implementations, the storage capacity and/or operating speed of the SSD (406) is greater than that of the memory card (402).

FIG. 5 illustrates a schematic circuit diagram of a memory device (500) including peripheral circuitry according to some aspects of the present disclosure. The memory device (500) may include a memory cell array (501) and peripheral circuitry (502) coupled to the memory cell array (501). A 3D memory device (304) may be an example of the memory device (500).

The memory cell array (501) may be a NAND flash memory cell array in which memory cells (506) are provided in the form of an array of NAND memory strings (508) that each extend vertically above a substrate (not shown in FIG. 5). In some implementations, each NAND memory string (508) includes a plurality of memory cells (506) that are coupled in series and stacked vertically. Each memory cell (506) may hold a continuous analog value, such as an electrical voltage or charge, that varies depending on the number of electrons trapped within a region of the memory cell (506). Each memory cell (506) may be a floating-gate type memory cell including a floating-gate transistor or a charge trap type memory cell including a charge-trap transistor.

In some implementations, each memory cell (506) is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell (506) is a multi-level cell (MLC) that can store more than a single bit of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also called a triple-level cell (TLC)), or four bits per cell (also called a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels in the erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

As illustrated in FIG. 5, each NAND memory string (508) may include a source select gate (SSG) transistor (510) at its source terminal and a drain select gate (DSG) transistor (512) at its drain terminal. The SSG transistors (510) and the DSG transistors (512) may be configured to activate a selected NAND memory string (508) (a column of the array) during read and program operations. In some implementations, the SSG transistors (510) of the NAND memory strings (508) in the same block (504) are coupled to a same source line (SL) (514), for example, to ground, via a common SL. Each DSG transistor (512) of each NAND memory string (508) is coupled to a respective bit line (516) from which data can be read or programmed via an output bus (not shown), depending on some implementations. In some implementations, each NAND memory string (508) is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the DSG transistors (512)) or a deselect voltage (e.g., 0 V) to the respective DSG transistors (512) via one or more DSG lines (513) and/or by applying a select voltage (e.g., higher than the threshold voltage of the SSG transistors (510)) or a deselect voltage (e.g., 0 V) to the respective SSG transistors (510) via one or more SSG lines (515).

As illustrated in FIG. 5, a NAND memory string (508) may be composed of a number of blocks (504), each of which may have a common source line (514). In some implementations, each block (504) is a basic data unit for an erase operation, i.e., all memory cells (506) on the same block (504) are erased simultaneously. Memory cells (506) of adjacent NAND memory strings (508) may be coupled via word lines (518) that select which row of memory cells (506) is affected by the read and program operations. In some implementations, each word line (518) is coupled to a page (520) of memory cells (506), which is a basic data unit for the program and read operations. The size of one page (520) in bit units may correspond to the number of NAND memory strings (508) coupled by word lines (518) in one block (504). Each word line (518) may include a plurality of control gates (gate electrodes) and gate lines coupling the control gates in each memory cell (506) of an individual page (520).

The peripheral circuit (502) may be coupled to the memory cell array (501) via the bit line (516), the word line (518), the source line (514), the SSG line (515), and the DSG line (513). As described above, the peripheral circuit (502) may include any suitable circuitry that facilitates operation of the memory cell array (501) by applying voltage signals and/or current signals to each target memory cell (506) via the bit line (516) and detecting voltage signals and/or current signals from each target memory cell (506) via the word line (518), the source line (514), the SSG line (515), and the DSG line (513). The peripheral circuit (502) may include various types of peripheral circuits formed using CMOS technology. For example, FIG. 6 illustrates some peripheral circuitry (502) including a page buffer (604), a column decoder/bit line driver (606), a row decoder/word line driver (608), a voltage generator (610), control logic (612), a register (614), an interface (I/F) (616), and a data bus (618). It is to be understood that in some examples, additional peripheral circuitry (502) may also be included.

The page buffer (604) may be configured to buffer data read from or programmed into the memory cell array (501) according to a control signal of the control logic (612). In one example, the page buffer (604) may store one page of program data (write data) to be programmed into one page (520) of the memory cell array (501). In another example, the page buffer (604) may also perform a program verify operation to verify that data is properly programmed into the memory cell (506) coupled to the selected word line (518).

The row decoder/word line driver (608) may be controlled by the control logic (612) and configured to select a block (504) of the memory cell array (501) and select a word line (518) of the selected block (504). The row decoder/word line driver (608) may further be configured to drive the memory cell array (501). For example, the row decoder/word line driver (608) may drive a memory cell (506) coupled to the selected word line (518) using a word line voltage generated from the voltage generator (610).

The column decoder/bit line driver (606) may be controlled by the control logic (612) and configured to select one or more 3D NAND memory strings (508) by applying bit line voltages generated from the voltage generator (610). For example, the column decoder/bit line driver (606) may apply a column signal to select a set of N bits of data from the page buffer (604) to be output in a read operation.

The control logic (612) may be coupled to each peripheral circuit (502) and configured to control the operation of the peripheral circuit (502). The register (614) may be coupled to the control logic (612) and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit (502).

The interface (616) may be coupled to the control logic (612) and configured to interface the memory controller (not shown) with the memory cell array (501). In some implementations, the interface (616) may act as a control buffer that buffers and relays control commands received from the memory controller and/or a host (not shown) to the control logic (612), and buffers and relays status information received from the control logic (612) to the memory controller and/or the host. The interface (616) may also be coupled to the page buffer (604) and the column decoder/bit line driver (606) via the data bus (618), and may act as an I/O interface and data buffer that buffers and relays program data received from the memory controller and/or the host to the page buffer (604), and buffers and relays data read from the page buffer (604) to the memory controller and/or the host. In some implementations, the interface (616) and data bus (618) are part of the I/O circuitry of the peripheral circuit (502).

The voltage generator (610) may be configured to generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, and verify voltage) and bit line voltages to be supplied to the memory cell array (501) under control of the control logic (612). In some implementations, the voltage generator (610) is part of a voltage source that provides voltages at various levels to different peripheral circuits (502), as described in detail below. Consistent with the scope of the present disclosure, in some implementations, the voltages provided by the voltage generator (610) to, for example, the row decoder/word line driver (608), the column decoder/bit line driver (606), and the page buffer (604) are higher than a particular level sufficient to perform memory operations. For example, the voltage provided to the page buffer circuit of the page buffer (604) and/or the logic circuit of the control logic (612) may be between +1.3 V and 5 V, such as 3.3 V, and the voltage provided to the driving circuit in the row decoder/word line driver (608) and/or the column decoder/bit line driver (606) may be between 5 V and 30 V.

FIG. 7 illustrates a flow chart of a method for forming a 3D memory device according to some aspects of the present disclosure. FIGS. 8A to 8F illustrate a manufacturing process for forming a 3D memory device according to some aspects of the present disclosure. As illustrated in FIGS. 7 and 8A to 8F, the method includes the following steps:

S100: As illustrated in FIG. 8a, a first stack structure (170a) having a TSG sacrificial layer (171) is formed on a substrate (100), and the TSG sacrificial layer (171) is formed on a side of the first stack structure (170a) that is relatively distant from the substrate (100).

S200: As shown in FIG. 8b, in the first stack structure (170a), a first TSG cutting line (120) is formed to separate the TSG sacrificial layer (171).

S300: As shown in FIG. 8c, a plurality of channel structures (130) penetrating the first stack structure (170a) are formed.

S400: As shown in FIG. 8c, a second stack structure (170b) is formed covering the first stack structure (170a) in a direction perpendicular to the substrate (100).

S500: As shown in FIG. 8d, a second TSG cutting line (120) is formed in the second stack structure (170b).

S600: As illustrated in FIG. 8e, a plurality of channel structures (130) are formed that penetrate the second stack structure (170b) and are electrically connected to the channel structures in the first stack structure.

In some implementations, the material of the TSG sacrificial layer (171) may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, single crystal silicon, polysilicon, or other suitable materials.

As illustrated in FIG. 8e, the memory device includes a first stack structure (170a) and a second stack structure (170b), and each stack structure is formed with a TSG cleavage line (120), a channel structure (130), and a conductive portion (140). The TSG cleavage line (120) divides the channel structure (130) within each stack structure into insulated memory blocks, and read/write/erase operations can be individually performed on the memory blocks.

Here, it should be noted that in the Z direction, the channel structure (130) of the first stack structure (170a) and the channel structure (130) of the second stack structure (170b) are stacked on each other. In the Z direction, adjacent stacked channel structures (130) are electrically connected to each other. The electrical connection may include direct contact between the channel structures (130) to form an electrical connection such that the semiconductor channels of the two channel structures (130) are in contact with each other. In some implementations, the manner of electrically connecting may also include providing a conductive structure (e.g., a conductive portion (140)) between the two channel structures (130) in the Z direction.

As illustrated in FIG. 8e, the stack structure includes alternately stacked gate sacrificial layers (172) and insulating layers (173). To form the stack structure (110) illustrated in FIG. 2a, the gate sacrificial layer (172) of the stack structure is replaced with a gate layer (112).

It is to be understood that in the present disclosure, the first stack structure (170a) and the second stack structure (170b) are merely examples and are not limited to two stack structures. In some implementations, a third stack structure, a fourth stack structure, and an nth stack structure may also be formed, where n is a natural number not less than 2. In each stack structure, the number of layers to be stacked may include 8, 16, 32, 64, 96, 128, and the like, and is not particularly limited.

Depending on design and process requirements, in some implementations, steps (S400), (S500) and (S600) may be repeated, and more stack structures may be stacked, with each stack structure having a TSG cut line (120) and a channel structure (130) formed therein, to increase the memory density of the 3D memory device.

In some implementations, steps (S200) and (S500) may also provide multiple TSG cut lines (120) in each stack structure, dividing the TSG sacrificial layer (171) into multiple insulated regions to secure more memory blocks that can independently perform read/write/erase operations.

It should be noted that in the Z direction perpendicular to the substrate (100), the memory blocks of the stack structure can independently perform read/write/erase operations and are not subject to interference from upper and lower adjacent memory blocks. For example, when a read/write/erase operation is performed on a memory block of the first stack structure (170a), the memory blocks of the second stack structure (170b) and the memory blocks of the third stack structure (170c) may not perform the read/write/erase operations. In this manner, more precise control of the memory device can be realized, the operating efficiency is improved, the programming interference between the memory blocks is reduced, and the stability of the memory device is improved.

In some implementations, as illustrated in FIG. 8e, the projection of the second TSG cut line (120) overlaps the projection of the first TSG cut line (120) in a direction perpendicular to the substrate (100). In the process of forming the TSG cut line (120), the TSG cut line (120) is formed by using a photolithography technique and then performing an etching process and a deposition process. Since the formation position of the first TSG cut line (120) in the first stack structure (170a) may be the same as the formation position of the second TSG cut line (120) in the second stack structure (170b), the projections of the first TSG cut line (120) and the second TSG cut line (120) overlap in the Z direction. Therefore, in the manufacturing processes of the first TSG cut line (120) and the second TSG cut line (120), the manufacturing cost can be reduced by using the same mask.

In some implementations, as illustrated in FIGS. 8b and 8d , in steps S200 and S500 , the method of forming the TSG cleavage line (120) may include forming a first trench (121) penetrating the TSG sacrificial layer (171) in the stack structure, and filling the first trench (121) with a dielectric material to form the TSG cleavage line (120). In some implementations, the dielectric material may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable material. In some implementations, the process of forming the first trench may include a dry etch, a wet etch, or other suit process. It should be understood that the TSG sacrificial layer (171) may be a single layer of material, or may include multiple TSG sub-layers to increase the depth of the first trench (121) and improve the partition and insulation performance of the formed TSG cut line (120).

As illustrated in FIG. 8f, a first trench (121) is formed in the first stack structure (170a), and then the first trench (121) is filled to form an insulated TSG cut line (120). It is understood that the method of forming the TSG cut line (120) in the second stack structure (170b), the third stack structure (170c), and the nth stack structure may be the same as the method of forming the TSG cut line (120) in the first stack structure (170a). In some implementations, after filling the first trench with a dielectric material and forming the TSG cut line, the dielectric material may overflow from the first trench to change the surface flatness of the stack structure, and the surface may be further processed using a chemical mechanical polishing (CMP) process to improve the flatness.

In some implementations, prior to performing step (S400), as illustrated in FIGS. 8c and 8e , the method may further include a step of forming a plurality of conductive portions (140) on the first stack structure (170a), wherein the conductive portions (140) are electrically connected to the channel structures (130) in the first stack structure (170a). After the second stack structure (170b) is formed, the conductive portions (140) are electrically connected to two channel structures (130) stacked in the first stack structure (170a) and the second stack structure (170b).

As illustrated in FIG. 8e, in the Z direction, a conductive portion (140) is formed between two adjacent channel structures (130) arranged in a stacked manner, and contacts the top of one channel structure (130) and the bottom of the other channel structure (130), thereby realizing electrical connection of the two channel structures (130). The conductive portion (140) can increase the electrical connection area of the two channel structures (130), reduce the difficulty of aligning the two channel structures (130), and facilitate expansion of the process window for forming the channel structures (130).

In some implementations, the material of the conductive portion (140) may include tungsten, cobalt, nickel, titanium, polysilicon, or other suitable material. In some implementations, the material of the conductive portion (140) may include a polysilicon material, and the polysilicon material may also be ion-doped to increase the carrier density of the conductive portion (140) and improve conductivity. In some implementations, n-type doping may be performed on the polysilicon of the conductive portion (140) to form an n-type polysilicon semiconductor, and the doping ions may include phosphorus, arsenic, antimony, or other suitable material.

In some implementations, as illustrated in FIGS. 8c and 8e , the channel structure (130) includes a semiconductor channel (131) and a memory film (132) disposed around the semiconductor channel (131). In steps (S300) and (S600), the method of forming the channel structure (130) includes a step of forming a channel hole penetrating the stack structure, a step of forming a memory film (132) covering a sidewall of the channel hole, and a step of forming a semiconductor channel (131) covering the memory film (132), wherein the semiconductor channels (131) stacked on each other in the two stack structures are electrically connected by a conductive portion (140).

In some implementations, the process for forming the channel holes includes dry etching, wet etching, or other suitable processes. In some implementations, the process for forming the memory film (132) and the semiconductor channel (131) can be any process known in the art, such as a low-temperature chemical vapor deposition (LPCVD) process, a low pressure chemical vapor deposition (LPCVD) process, a rapid thermal chemical vapor deposition (ALD) process, an atomic layer deposition (ALD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or other suitable processes.

In the Z direction perpendicular to the substrate (100), adjacent stacked semiconductor channels (131) are electrically connected through the conductive portion (140), so that conduction of each semiconductor channel (131) can be implemented.

Additionally, prior to the step of forming the conductive portion (140), the method may further include the step of forming an insulating layer (174) covering the first stack structure (170a) and the TSG cut line (120), and the step of forming a plurality of conductive portions (140) on the insulating layer (174), wherein the plurality of conductive portions (140) are electrically insulated from each other in a direction parallel to the substrate (100). In some implementations, the material of the insulating layer (174) may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable material.

An insulating layer (174) is formed on the top of the first stack structure (170a) and the top of the TSG cut line (120), and a plurality of conductive portions (140) are formed on the insulating layer (174), so that the plurality of conductive portions (140) are insulated from each other by the insulating layer (174) in the X direction parallel to the substrate (100), thereby reducing programming interference between the conductive portions (140). In some implementations, a groove is formed in the insulating layer (174) by an etching operation, and then the groove is filled with a conductive material to form the conductive portion (140). Since the insulating layer (174) can provide a flatter contact surface that is advantageous for deposition of a material, the second stack structure (170b) formed on the insulating layer (174) becomes more uniform, which is advantageous for forming more stack structures and increases the number of memory layers.

In some implementations, as illustrated in FIGS. 8a and 8e , in steps (S100) and (S400), the method of forming the stack structure includes the steps of alternately stacking gate sacrificial layers (172) and insulating layers (173) on a substrate (100) and forming a TSG sacrificial layer (171) on a side of the stack structure opposite to the substrate (100). The insulating layer (173) electrically insulates the TSG sacrificial layer (171) and the adjacent gate sacrificial layer (172).

In some implementations, step (S300) may be performed before step (S200). In some implementations, step (S600) may be performed before step (S500). For example, the channel structure (130) may be formed first, and then the TSG cut line (120) may be formed in the stack structure.

As illustrated in FIGS. 8c and 8e , the method may further include a step of forming a dummy channel hole penetrating the gate sacrificial layers (172) and the insulating layer (173) alternately stacked below the TSG cutting line (120), a step of forming a dummy memory film (152) covering the dummy channel hole, a step of forming a dummy semiconductor channel (151) covering the dummy memory film (152), and a step of forming an insulating layer (173) between the TSG sacrificial layer (171) and the gate sacrificial layer (172) to form electrical insulation to prevent over-etching of the TSG sacrificial layer (171) and destruction of the gate sacrificial layer (172) that affects the stability of the memory device during the formation of the TSG cutting line (120) extending to the gate sacrificial layer (172).

A dummy channel structure (150) is formed under a TSG cut line (120), and dummy channel structures (150) of adjacent memory arrays are electrically insulated by the TSG cut line (120). No read/write/erase operations are performed on the dummy channel structure (150), and the dummy channel structure (150) is used to support the stack structure. The dummy channel structure (150) can be formed simultaneously using the same manufacturing process as the channel structure (130) of steps (S300) and (S600), and can have the same structure, thereby simplifying the process steps and reducing the manufacturing cost.

In some implementations, after step (S600), a second trench can be formed penetrating each stack structure. The second trench can extend into the substrate. The gate sacrificial layer (172) and the TSG sacrificial layer (171) are removed based on the second trench to form a gap between adjacent insulating layers (173). As illustrated in FIG. 2B, the gap is filled with a conductive material to form a gate layer (112) and a TSG (111). The gate layer (112) is used as a word line, and different operating voltages are applied to the word line to turn on and/or turn off a semiconductor channel, thereby performing a read/write/erase operation of the memory device. The TSG (111) is used as a control gate of a top select transistor, and by applying different operating voltages, the semiconductor channel is turned on and/or turned off, thereby implementing a read/write/erase operation of the memory device.

In some implementations, as illustrated in FIG. 2A, the 3D memory device may include memory arrays stacked in a first direction, e.g., the Z direction. Each memory array may include a stack structure including interleaved conductive layers and a first dielectric layer, e.g., an insulating layer (113), extending in a second direction perpendicular to the first direction, e.g., the X direction, and a third direction perpendicular to the first and second directions, e.g., the Y direction. The conductive layers may include a word line, e.g., a gate layer (112), and a drain select gate line, e.g., a TSG (111). In some implementations, the drain select gate line is separated in the second direction by a second dielectric layer, e.g., a TSG cut line (120).

In some implementations, the first channel structure, for example, the channel structure (130), can extend in the first direction through the word line and the drain select gate line. In some implementations, the second channel structure, for example, the dummy channel structure (150), can extend in the first direction through the word line. Note that the channel structure (130) can penetrate all of the gate layer (112), the insulating layer (113), and the TSG (111), and the dummy channel structure (150) can penetrate only the gate layer (112) and the insulating layer (113). Accordingly, as illustrated in FIG. 2A, the first length of the channel structure (130) in the first direction is longer than the second length of the dummy channel structure (150) in the first direction. In some implementations, the TSG cut line (120) is disposed over the dummy channel structure (150).

In some implementations, a first semiconductor layer, for example a conductive portion (140), may be disposed over the channel structure (130), and a second semiconductor layer, for example a dummy conductive portion (180), may be disposed over the TSG cut line (120).

In some implementations, the memory device may include one or more memory arrays stacked together, as illustrated in FIG. 2A. For example, the memory device may include a first memory array and a second memory array disposed over the first memory array. A TSG cut line (120) of the first memory array may at least partially overlap a TSG cut line (120) of the second memory array. In some implementations, as illustrated in FIG. 2B, in a plan view of the 3D memory device, the TSG cut line (120) of the first memory array may completely overlap the TSG cut line (120) of the second memory array.

In some implementations, in a plan view of the 3D memory device, the dummy conductive portion (180) of the first memory array can at least partially overlap with the dummy conductive portion (180) of the second memory array. In some implementations, in a plan view of the 3D memory device, the dummy conductive portion (180) of the first memory array can completely overlap with the dummy conductive portion (180) of the second memory array.

In some implementations, the channel structures (130) of the first memory array and the second memory array are in electrical contact with the conductive portion (140) disposed between the first memory array and the second memory array. In some implementations, the channel structures (130) of the first memory array and the second memory array are in direct contact with the conductive portion (140) disposed between the first memory array and the second memory array. In other words, the channel structures (130) of the first memory array and the second memory array are electrically connected by the conductive portion (140) disposed between the first memory array and the second memory array.

In some implementations, after forming each memory array structure, a planarization operation, such as a CMP operation, may be performed to make the top surface flat. In other words, in some implementations, the top surface of the conductive portion (140) may be coplanar with the dummy conductive portion (180) in the X-direction and the Y-direction.

In some implementations, as illustrated in FIG. 2A, the 3D memory device may include memory arrays stacked in a first direction, e.g., the Z direction. For example, the 3D memory device may include a first stack structure and a second stack structure. The first stack structure may include interleaved first conductive layers and a first dielectric layer, such as a gate layer (112) and a TSG (111), and an insulating layer (113), which extend in the X and Y directions. The second stack structure may also include interleaved first conductive layers and a first dielectric layer, such as a gate layer (112) and a TSG (111), and an insulating layer (113), which extend in the X and Y directions. In some implementations, the structure of the first stack structure may be identical to the second stack structure, and the first stack structure and the second stack structure are stacked in the Z direction.

The memory device may also include one or more first channel structures, e.g., channel structures (130), extending in the Z direction through the first stack structure, and one or more second channel structures, e.g., channel structures (130), extending in the Z direction through the second stack structure.

The memory device may further include at least one first severing structure, for example, a TSG severing line (120), disposed between the first channel structures, and at least one second severing structure, for example, a TSG severing line (120), disposed between the second channel structures. In other words, as illustrated in FIG. 2A, each and every stack structure may separately include a TSG severing line (120). Accordingly, each stack structure (110) of each memory array may have a TSG (111), and the TSG (111) may be a conductive layer parallel to the substrate (100), and a plurality of channel structures (130) may share the same TSG (111). The TSG (111) serves as a control gate of the top select transistor, and controls the voltage of the TSG (111) to turn on or off the top select transistor, thereby controlling the channel structure (130) to implement read/write/erase operations. Each memory array is divided into two electrically isolated memory blocks (210) by the TSG (111) being divided into two electrically isolated regions by the TSG cut line (120) penetrating the TSG (111).

In some implementations, the memory device may include a first dummy channel structure, e.g., a dummy channel structure (150), extending within the first stack structure in the Z direction, and a second dummy channel structure, e.g., a dummy channel structure (150), extending within the second stack structure in the Z direction over the first dummy channel structure. A first cut structure, e.g., a TSG cut line (120), is positioned between the first dummy channel structure and the second dummy channel structure.

In some implementations, the first dummy channel structure, the first cut structure, and the second dummy channel structure may at least partially overlap in a plan view of the 3D memory device.

FIG. 9 illustrates a flow diagram of a method of forming a 3D memory device according to some aspects of the present disclosure. As depicted in step (902) of FIG. 9, a first memory array is formed including a first cut structure between first channel structures.

In some implementations, as illustrated in FIG. 8a, a first dielectric stack, for example, a stack structure (170a), is formed. The first dielectric stack includes interleaved first dielectric layers, for example, an insulating layer (173), stacked in the z direction, and first sacrificial layers, for example, a gate sacrificial layer (172) and a TSG sacrificial layer (171).

A first channel structure, for example, a channel structure (130), is formed through a first dielectric stack in the Z direction. A first cut structure, for example, a TSG cut line (120), is formed on an uppermost layer of a first sacrificial layer. In some implementations, the first channel structure may be formed prior to the first cut structure. In some implementations, the first cut structure may be formed prior to the first channel structure. The first sacrificial layer is then replaced with a first conductive layer. In some implementations, the first conductive layer may include a gate layer (112) and a TSG (111).

In some implementations, a first stack structure can be formed. The first stack structure can include a first word line and a first drain select gate line. The first word line and the first drain select gate line are stacked in the Z direction. Then, a first cutting structure is formed to cut the first drain select gate line. A first channel structure is formed to extend in the Z direction within the first stack structure.

In some implementations, a semiconductor layer, for example a conductive portion (140), may be formed on the first channel structure.

As illustrated in step (904) of FIG. 9, a second memory array is formed over the first memory array, and the second memory array includes a second cut structure between the second channel structures.

In some implementations, as illustrated in FIG. 8d, a second dielectric stack, for example, a stack structure (170b), is formed. The second dielectric stack includes interleaved second dielectric layers, for example, an insulating layer (173), stacked in the z direction, and second sacrificial layers, for example, a gate sacrificial layer (172) and a TSG sacrificial layer (171).

As illustrated in FIG. 8e, a second channel structure, for example, a channel structure (130), is formed through the second dielectric stack in the Z direction. A second cut structure, for example, a TSG cut line (120), is formed on an uppermost layer of the second sacrificial layer. In some implementations, the second channel structure may be formed before the second cut structure. In some implementations, the second cut structure may be formed before the second channel structure. The second sacrificial layer is then replaced with a second conductive layer. In some implementations, the second conductive layer may include a gate layer (112) and a TSG (111).

In some implementations, a second stack structure can be formed. The second stack structure can include a second word line and a second drain select gate line. The second word line and the second drain select gate line are stacked in the Z direction. Then, a second cut structure is formed to cut the second drain select gate line. A second channel structure is formed to extend in the Z direction within the second stack structure.

In some implementations, the TSG cut line (120) of the first memory array may at least partially overlap the TSG cut line (120) of the second memory array. In some implementations, as illustrated in FIG. 2B, in a plan view of the 3D memory device, the TSG cut line (120) of the first memory array may completely overlap the TSG cut line (120) of the second memory array.

In some implementations, a third memory array can be additionally formed over the second memory array. The third memory array can include a third cut structure between the third channel structures. In some implementations, the structures of the first memory array, the second memory array, and the third memory array can be identical.

Using the method disclosed in the implementations, each stack structure (110) of each memory array can have a TSG (111), and the TSG (111) can be a conductive layer parallel to the substrate (100), and a plurality of channel structures (130) can share the same TSG (111). The TSG (111) acts as a control gate of the top select transistor, and controls the voltage of the TSG (111) to turn on or off the top select transistor, thereby controlling the channel structure (130) to implement read/write/erase operations. The TSG (111) is divided into two electrically isolated regions by a TSG cut line (120) penetrating the TSG (111), whereby each memory array is divided into two electrically isolated memory blocks (210).

The above description of a specific implementation can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and scope of the equivalency of the disclosed implementation, based on the teachings and guidance presented herein.

The breadth and scope of this disclosure should not be limited by any of the implementations described above, but should be defined only in accordance with the following claims and their equivalents.

Although specific configurations and arrangements are discussed, it should be understood that they are done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of the present disclosure. Furthermore, the subject matter described in the present disclosure may be used in various other applications. The functional and structural features described in the present disclosure may be combined, adjusted, modified, and rearranged with one another in a manner consistent with the scope of the present disclosure.

Claims (32)

As a three-dimensional (3D) memory device,
Comprising a memory array stacked in a first direction,
Each memory array,
A stack structure comprising interleaved conductive layers and a first dielectric layer extending in a second direction perpendicular to the first direction and in a third direction perpendicular to the first direction and the second direction, wherein the conductive layers include a word line and a drain select gate line, and the drain select gate line is separated by the second dielectric layer in the second direction.
A 3D memory device comprising: In the first paragraph,
Each memory array,
A first channel structure extending in the first direction through the word line and the drain selection gate line.
A 3D memory device further comprising: In the second paragraph,
Each memory array,
A second channel structure extending in the first direction through the word line
A 3D memory device further comprising: In the third paragraph,
A 3D memory device, wherein the second dielectric layer is disposed over the second channel structure. In the third paragraph,
A 3D memory device, wherein a first length of the first channel structure in the first direction is longer than a second length of the second channel structure in the first direction. In the third paragraph,
Each memory array,
A first semiconductor layer disposed on the first channel structure; and
A second semiconductor layer disposed on the second dielectric layer
A 3D memory device further comprising: In Article 6,
A 3D memory device, wherein the memory array includes a first memory array and a second memory array disposed over the first memory array, wherein in a plan view of the 3D memory device, a second dielectric layer of the first memory array at least partially overlaps a second dielectric layer of the second memory array. In Article 7,
A 3D memory device, wherein in a plan view of the 3D memory device, the second semiconductor layer of the first memory array at least partially overlaps the second semiconductor layer of the second memory array. In Article 7,
A 3D memory device, wherein the first channel structure of the second memory array is in contact with the first semiconductor layer of the first memory array. In Article 7,
A 3D memory device, wherein the second channel structure of the second memory array is in contact with the second semiconductor layer of the first memory array. In Article 6,
A 3D memory device, wherein the upper surface of the first semiconductor layer is coplanar with the upper surface of the second semiconductor layer in the second direction. As a system,
A three-dimensional (3D) memory device configured to store data, wherein the 3D memory device comprises memory arrays stacked in a first direction, each memory array comprising a stack structure including interleaved conductive layers and a first dielectric layer extending in a second direction perpendicular to the first direction and in a third direction perpendicular to the first direction and the second direction, the conductive layers including a word line and a drain select gate line, the drain select gate line being separated by the second dielectric layer in the second direction; and
A memory controller coupled to the 3D memory device and configured to control operation of the memory array through the drain select gate line and the word line.
A system including: As a three-dimensional (3D) memory device,
A first stack structure comprising interleaved first conductive layers and first dielectric layers extending in a first direction and a second direction perpendicular to the first direction;
First channel structures extending in a third direction perpendicular to the first direction and the second direction through the first stack structure;
A second stack structure comprising an interleaved second conductive layer and a second dielectric layer extending in the first direction and the second direction, and disposed on the first stack structure;
Second channel structures extending in the third direction through the second stack structure;
a first cutting structure disposed between the first channel structures; and
A second cutting structure disposed between the above second channel structures
A 3D memory device comprising: In Article 13,
a first dummy channel structure extending within the first stack structure in the third direction; and
On the first dummy channel structure, a second dummy channel structure extending within the second stack structure in the third direction.
Including more,
A 3D memory device, wherein the first cut structure is positioned between the first dummy channel structure and the second dummy channel structure. In Article 14,
A 3D memory device, wherein in a plan view of the 3D memory device, the first dummy channel structure, the first cut structure, and the second dummy channel structure at least partially overlap. In Article 14,
A 3D memory device, wherein the first conductive layer of the first stack structure includes a word line and a drain select gate line, and the drain select gate line is separated by the first cut structure. In Article 14,
A 3D memory device, wherein the second conductive layer of the second stack structure includes a word line and a drain select gate line, the drain select gate line being separated by the second cut structure. In Article 14,
A 3D memory device, wherein the first cut structure comprises a third dielectric layer. In Article 14,
A semiconductor layer disposed between the first cutting structure and the second dummy channel structure
A 3D memory device further comprising: In Article 19,
A 3D memory device, wherein the semiconductor layer is a doped semiconductor layer. As a system,
A three-dimensional (3D) memory device configured to store data, said 3D memory device comprising:
A first stack structure comprising interleaved first conductive layers and first dielectric layers extending in a first direction and a second direction perpendicular to the first direction;
First channel structures extending in a third direction perpendicular to the first direction and the second direction through the first stack structure;
A second stack structure comprising an interleaved second conductive layer and a second dielectric layer extending in the first direction and the second direction, and disposed on the first stack structure;
Second channel structures extending in the third direction through the second stack structure;
a first cutting structure disposed between the first channel structures; and
A second cutting structure disposed between the above second channel structures
including -; and
A memory controller coupled to the 3D memory device and configured to control the operation of the 3D memory device.
A system including: A method for forming a three-dimensional (3D) memory device,
forming a first memory array including a first cutting structure between first channel structures; and
A step of forming a second memory array on the first memory array, wherein the second memory array includes a second cut structure between second channel structures.
A method for forming a 3D memory device comprising: In Article 22,
The step of forming a first memory array including a first cutting structure between the first channel structures comprises:
A step of forming a first dielectric stack including interleaved first dielectric layers and a first sacrificial layer laminated in a first direction;
forming the first channel structures through the first dielectric stack in the first direction; and
A step of forming the first cutting structure on the uppermost layer of the first sacrificial layer
A method for forming a 3D memory device, comprising: In Article 23,
A step of replacing the first sacrificial layer with a first conductive layer
A method for forming a 3D memory device further comprising: In Article 23,
The step of forming a second memory array on the first memory array comprises:
A step of forming a second dielectric stack on the first memory array, the second dielectric stack including interleaved second dielectric layers and a second sacrificial layer stacked in the first direction;
forming the second channel structures through the second dielectric stack in the first direction; and
A step of forming the second cutting structure on the uppermost layer of the second sacrificial layer
A method for forming a 3D memory device, comprising: In Article 25,
A step of replacing the second sacrificial layer with a second conductive layer
A method for forming a 3D memory device further comprising: In Article 22,
The step of forming a first memory array including a first cutting structure between the first channel structures comprises:
A step of forming a first stack structure including a first word line and a first drain select gate line, wherein the first word line and the first drain select gate line are stacked in a first direction;
A step of forming the first cutting structure to cut the first drain selection gate line; and
A step of forming the first channel structures extending in the first direction within the first stack structure.
A method for forming a 3D memory device, comprising: In Article 27,
The step of forming a second memory array on the first memory array comprises:
A step of forming a second stack structure on the first stack structure, wherein the second stack structure includes a second word line and a second drain select gate line, and the second word line and the second drain select gate line are stacked in the first direction;
a step of forming a second cutting structure to cut the second drain selection gate line; and
A step of forming the second channel structures extending in the first direction within the second stack structure.
A method for forming a 3D memory device, comprising: In any one of Articles 22 to 28,
A step of forming a semiconductor layer on the first channel structure
A method for forming a 3D memory device further comprising: In Article 22,
The step of forming a second memory array on the first memory array comprises:
A step of forming the second cut structure at least partially overlapping the first cut structure in a plan view of the 3D memory device.
A method for forming a 3D memory device, comprising: In Article 22,
A step of forming a third memory array on the second memory array, wherein the third memory array includes a third cut structure between third channel structures.
A method for forming a 3D memory device further comprising: In Article 31,
The step of forming a third memory array on the second memory array is:
A step of at least partially overlapping the first cut structure, the second cut structure and the third cut structure in a plan view of the 3D memory device.
A method for forming a 3D memory device, comprising: