KR20240133403A - Display device - Google Patents

Abstract

A display device according to one embodiment of the present specification includes a substrate including a display area including a plurality of sub-pixels and a plurality of gate driving areas extending in a first direction between the plurality of sub-pixels, and a non-display area surrounding the display area, a plurality of transistors respectively disposed in the plurality of sub-pixels, a gate driving unit disposed in the plurality of gate driving areas, a power supply wire extending in the first direction, and a plurality of auxiliary power supply wires extending in a second direction intersecting the first direction and connected to the power supply wires, wherein each of the plurality of auxiliary power supply wires includes a plurality of first portions disposed in the plurality of gate driving areas and a plurality of second portions connecting the plurality of first portions. Accordingly, electrostatic induced charging can be minimized.

Description

DISPLAY DEVICE

This specification relates to a display device, and more specifically, to a display device using an LED (Light Emitting Diode).

Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting displays (OLEDs) that emit light on their own, and liquid crystal displays (LCDs) that require a separate light source.

The application range of display devices is expanding beyond computer monitors and TVs to include personal mobile devices, and research is being conducted on display devices that have a large display area while also having reduced volume and weight.

In addition, display devices including LEDs (Light Emitting Diodes) have recently been attracting attention as next-generation display devices. Since LEDs are made of inorganic materials rather than organic materials, they are highly reliable and have a longer lifespan than liquid crystal displays or organic light-emitting diodes. In addition, LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, are highly impact-resistant, have excellent stability, and can display high-brightness images.

The problem that this specification seeks to solve is to provide a display device capable of implementing zero bezel.

Another problem that this specification seeks to solve is to provide a display device capable of preventing wire breakage due to electrostatic induced charging.

The tasks of this specification are not limited to those mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to one embodiment of the present specification includes a substrate including a display area including a plurality of sub-pixels and a plurality of gate driving areas extending in a first direction between the plurality of sub-pixels, and a non-display area surrounding the display area, a plurality of transistors respectively disposed in the plurality of sub-pixels (SP), a gate driving unit disposed in the plurality of gate driving areas, a power supply wire extending in the first direction, and a plurality of auxiliary power supply wires extending in a second direction intersecting the first direction and connected to the power supply wires, wherein each of the plurality of auxiliary power supply wires includes a plurality of first portions disposed in the plurality of gate driving areas and a plurality of second portions connecting the plurality of first portions.

Specific details of other embodiments are included in the detailed description and drawings.

A display device according to one embodiment of the present specification positions a gate driver within a display area of a display panel, forms side wiring that connects signal wiring on a front surface of the display panel to pad electrodes on a rear surface of the display panel, and bonds a flexible film and a printed circuit board to the rear surface of the display panel, thereby enabling implementation of a zero bezel by minimizing a non-display area on the front surface of the display panel.

A display device according to one embodiment of the present specification can minimize electrostatic induced charging by configuring a plurality of auxiliary power wires connected to power wires as a plurality of first parts arranged in a gate driving region and a plurality of second parts connecting the plurality of first parts.

The effects according to this specification are not limited to the contents exemplified above, and more diverse effects are included in this specification.

FIG. 1 is a schematic configuration diagram of a display device according to one embodiment of the present specification.
FIG. 2A is a partial cross-sectional view of a display device according to one embodiment of the present specification.
FIG. 2b is a perspective view of a tiling display device according to one embodiment of the present specification.
FIG. 3 is a plan view of a display panel of a display device according to one embodiment of the present specification.
FIGS. 4A and 4B are plan views of a pixel area of a display device according to one embodiment of the present specification.
FIG. 5 is a cross-sectional view of a display device according to one embodiment of the present specification.
FIG. 6 is a plan view of a display panel of a display device according to one embodiment of the present specification.
Figure 7 is an enlarged plan view of area A of Figure 6.
Fig. 8 is a cross-sectional view taken along line VIII-VIII' of Fig. 7.
Fig. 9 is a cross-sectional view taken along IX-IX' of Fig. 7.

The advantages and features of the present specification and the method for achieving them will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the embodiments are provided only to make the disclosure of the present specification complete and to fully inform a person having ordinary skill in the art to which the present specification belongs of the scope of the specification.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative and therefore the present specification is not limited to the matters illustrated. The same reference numerals refer to the same components throughout the specification. In addition, in describing the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When the terms “includes,” “has,” “consists of,” etc. are used in the present specification, other parts may be added unless “only” is used. When a component is expressed in the singular, it includes a case where the plural is included unless there is a specifically explicit description.

When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

When describing a positional relationship, for example, when the positional relationship between two parts is described as 'on', 'upper', 'lower', 'next to', etc., one or more other parts may be located between the two parts, unless 'right' or 'directly' is used.

When an element or layer is referred to as being "on" another element or layer, it includes both instances where the other element is directly on top of the other element or layer, or instances where there is another layer or element intervening therebetween.

Also, although the terms first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component mentioned below may also be a second component within the technical scope of this specification.

Throughout the specification, identical reference numerals refer to identical components.

The area and thickness of each component shown in the drawing are shown for convenience of explanation, and this specification is not necessarily limited to the area and thickness of the component shown.

The individual features of the various embodiments of this specification may be partially or wholly combined or combined with each other, and may be technically interconnected and operated in various ways, and each embodiment may be implemented independently of each other or implemented together in a related relationship.

Hereinafter, the present specification will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a display device according to one embodiment of the present specification. FIG. 2a is a partial cross-sectional view of a display device according to one embodiment of the present specification. FIG. 2b is a perspective view of a tiling display device according to one embodiment of the present specification. For convenience of explanation, only a display panel, a gate driver, a data driver, and a timing controller among various components of the display device are illustrated in FIG. 1.

Referring to FIG. 1, a display device (100) includes a display panel (PN) including a plurality of sub-pixels (SP), a gate driver (GD) and a data driver (DD) that supply various signals to the display panel (PN), and a timing controller (TC) that controls the gate driver (GD) and the data driver (DD).

The gate driver (GD) supplies a plurality of scan signals to a plurality of scan lines (SL) according to a plurality of gate control signals provided from a timing controller (TC). In Fig. 1, one gate driver (GD) is illustrated as being spaced apart from one side of the display panel (PN), but the number and arrangement of the gate drivers (GD) are not limited thereto.

The data driver (DD) converts image data input from the timing controller (TC) into data voltages using a reference gamma voltage according to multiple data control signals provided from the timing controller (TC). The data driver (DD) can supply the converted data voltages to multiple data lines (DL).

The timing controller (TC) aligns image data input from the outside and supplies it to the data driving unit (DD). The timing controller (TC) can generate a gate control signal and a data control signal using a synchronization signal input from the outside, such as a dot clock signal, a data enable signal, and a horizontal/vertical synchronization signal. In addition, the timing controller (TC) can control the gate driving unit (GD) and the data driving unit (DD) by supplying the generated gate control signal and data control signal to each of the gate driving unit (GD) and the data driving unit (DD).

The display panel (PN) is configured to display an image to a user and includes a plurality of sub-pixels (SP). In the display panel (PN), a plurality of scan lines (SL) and a plurality of data lines (DL) intersect each other, and each of the plurality of sub-pixels (SP) is connected to the scan lines (SL) and the data lines (DL). In addition, although not shown in the drawing, each of the plurality of sub-pixels (SP) may be connected to a high-potential power line (VL1), a low-potential power line (VL2), a reference line, etc.

A display panel (PN) may define a display area (AA) and a non-display area (NA) surrounding the display area (AA).

The display area (AA) is an area in which an image is displayed in the display device (100). A plurality of sub-pixels (SP) constituting a plurality of pixels (PX) and a circuit for driving the plurality of sub-pixels (SP) may be arranged in the display area (AA). The plurality of sub-pixels (SP) are the minimum units constituting the display area (AA), and n sub-pixels (SP) may form one pixel. A light-emitting element (130) and a thin film transistor for driving the light-emitting element (130) may be arranged in each of the plurality of sub-pixels (SP). The plurality of light-emitting elements (130) may be defined differently depending on the type of the display panel (PN). For example, when the display panel (PN) is an inorganic light-emitting display panel, the light-emitting element (130) may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

In the display area (AA), a plurality of wires are arranged to transmit various signals to a plurality of sub-pixels (SP). For example, the plurality of wires may include a plurality of data wires (DL) that supply a data voltage to each of the plurality of sub-pixels (SP), a plurality of scan wires (SL) that supply a scan signal to each of the plurality of sub-pixels (SP), etc. The plurality of scan wires (SL) may extend in one direction in the display area (AA) and be connected to the plurality of sub-pixels (SP), and the plurality of data wires (DL) may extend in a direction different from the one direction in the display area (AA) and be connected to the plurality of sub-pixels (SP). In addition, a low-potential power wire (VL2), a high-potential power wire (VL1), etc. may be further arranged in the display area (AA), but are not limited thereto.

The non-display area (NA) is an area where an image is not displayed, and can be defined as an area extending from the display area (AA). Link wiring and pad electrodes for transmitting signals to sub-pixels (SP) of the display area (AA), or driver ICs such as gate driver ICs and data driver ICs, can be placed in the non-display area (NA).

However, the non-display area (NA) may be located on the back surface of the display panel (PN), i.e., on a surface where there are no sub-pixels (SP), or may be omitted, and is not limited to that shown in the drawing.

Meanwhile, driving units such as a gate driver (GD), a data driver (DD), and a timing controller (TC) can be connected to the display panel (PN) in various ways. For example, the gate driver (GD) can be mounted in a non-display area (NA) in a GIP (Gate In Panel) manner, or can be mounted between a plurality of sub-pixels (SP) in a GIA (Gate In Active area) manner in the display area (AA). For example, the data driver (DD) and the timing controller (TC) can be formed on separate flexible films and printed circuit boards, and the data driver (DD) and the timing controller (TC) can be electrically connected to the display panel (PN) by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area (NA) of the display panel (PN).

If the gate driver (GD) is mounted in the GIP method and the data driver (DD) and the timing controller (TC) transmit signals to the display panel (PN) through the pad electrodes of the non-display area (NA), a certain level or larger area of the non-display area (NA) is required to place the gate driver (GD) and the pad electrodes, and thus the bezel may increase.

In contrast, when the gate driver (GD) is mounted inside the display area (AA) in the GIA manner and side wiring (SRL) is formed to connect the signal wiring on the front surface of the display panel (PN) to the pad electrode on the back surface of the display panel (PN), and a flexible film and a printed circuit board are bonded to the back surface of the display panel (PN), the non-display area (NA) on the front surface of the display panel (PN) can be minimized. That is, when the gate driver (GD), the data driver (DD), and the timing controller (TC) are connected to the display panel (PN) in the above manner, a zero bezel implementation in which there is virtually no bezel can be possible.

Specifically, referring to FIGS. 2A and 2B, a plurality of pad electrodes for transmitting various signals to a plurality of sub-pixels (SP) are arranged in a non-display area (NA) of a display panel (PN). For example, a first pad electrode (PAD1) for transmitting signals to a plurality of sub-pixels (SP) is arranged in a non-display area (NA) on the front side of the display panel (PN), and a second pad electrode (PAD2) electrically connected to driving components such as a flexible film and a printed circuit board is arranged in a non-display area (NA) on the back side of the display panel (PN). That is, on the front side of the display panel (PN) where an image is displayed, only a pad area in which a first pad electrode (PAD1) is arranged among the non-display area (NA) can be formed at a minimum.

In this case, although not shown in the drawing, various signal wires connected to a plurality of sub-pixels (SP), such as scan wires (SL) or data wires (DL), may extend from the display area (AA) to the non-display area (NA) and be electrically connected to the first pad electrode (PAD1).

And a side wiring (SRL) is arranged along the side surface of the display panel (PN). The side wiring (SRL) can electrically connect a first pad electrode (PAD1) on the front surface of the display panel (PN) and a second pad electrode (PAD2) on the back surface of the display panel (PN). Accordingly, a signal from a driving component on the back surface of the display panel (PN) can be transmitted to a plurality of sub-pixels (SP) through the second pad electrode (PAD2), the side wiring (SRL), and the first pad electrode (PAD1). Accordingly, a signal transmission path between the side surface and the back surface of the display panel (PN) is formed on the front surface of the display panel (PN), so that the area of the non-display area (NA) on the front surface of the display panel (PN) can be minimized.

And referring to Fig. 2b, a tiling display device (TD) having a large screen can be implemented by connecting a plurality of display devices (100). At this time, when the tiling display device (TD) is implemented using a display device (100) with a minimized bezel as illustrated in Fig. 2a, the seam area where an image is not displayed between the display devices (100) can be minimized, thereby improving the display quality.

For example, a plurality of sub-pixels (SP) can form one pixel, and the spacing (D1) between the outermost pixel of one display device (100) and the outermost pixel of another adjacent display device (100) can be implemented to be the same as the spacing (D1) between pixels within one display device (100). Accordingly, the spacing (D1) between pixels between display devices (100) can be configured to be constant, so that the depth area can be minimized.

However, FIGS. 2A and 2B are exemplary, and the display device (100) according to one embodiment of the present specification may be a general display device (100) having a bezel, but is not limited thereto.

FIG. 3 is a plan view of a display panel of a display device according to an embodiment of the present specification. FIGS. 4A and 4B are plan views of a pixel area of a display device according to an embodiment of the present specification. FIG. 5 is a cross-sectional view of a display device according to an embodiment of the present specification. For convenience of explanation, FIG. 4A illustrates only a plurality of light-emitting elements, a driving transistor of a pixel circuit, and a plurality of wires, and FIG. 4B illustrates only a plurality of reflectors and a plurality of light-emitting elements.

First, referring to FIGS. 3 to 5, the display panel (PN) includes a first substrate (110). The first substrate (110) is a substrate that supports components arranged on the upper portion of the display device (100) and may be an insulating substrate. A plurality of pixels (PX) are formed on the first substrate (110) so that an image can be displayed. For example, the first substrate (110) may be made of glass or resin, etc. In addition, the first substrate (110) may be made of a polymer or plastic. In some embodiments, the first substrate (110) may be made of a plastic material having flexibility.

Referring to FIG. 3, a plurality of pixel areas (UPAs), a plurality of gate driving areas (GAs), and a plurality of pad areas are arranged on the first substrate (110). Among these, the plurality of pixel areas (UPAs) and the plurality of gate driving areas (GAs) may be included in the display area (AA) of the display panel (PN).

First, the plurality of pixel areas (UPAs) are areas in which a plurality of pixels (PXs) are arranged. The plurality of pixel areas (UPAs) can be arranged in a plurality of rows and a plurality of columns. Each of the plurality of pixels (PXs) arranged in the plurality of pixel areas (UPAs) includes a plurality of sub-pixels (SPs). Each of the plurality of sub-pixels (SPs) includes a light-emitting element (130) and a pixel circuit and can independently emit light.

A plurality of gate driving areas (GA) are areas where gate driving units (GDs) are arranged. The gate driving units (GDs) can be mounted in a GIA (Gate In Active area) manner in a display area (AA). For example, the gate driving areas (GAs) can be formed along a row direction and/or a column direction between a plurality of pixel areas (UPAs). The gate driving units (GDs) formed in the gate driving areas (GAs) can provide scan signals to a plurality of scan lines (SLs).

A gate driver (GD) arranged in a gate driving region (GA) may include a circuit for outputting a scan signal. At this time, the gate driver may include, for example, a plurality of transistors and/or capacitors. Here, the active layers of the plurality of transistors may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but are not limited thereto. At this time, the active layers of the plurality of transistors may be made of the same material or may be made of different materials. In addition, the active layers of the transistors of the gate driver may be made of the same material as the active layers of various transistors of the pixel circuit or may be made of different materials.

The plurality of pad areas are areas where a plurality of first pad electrodes (PAD1) are arranged. The plurality of first pad electrodes (PAD1) can transmit various signals as various wires extending in the column direction from the display area (AA). For example, the plurality of first pad electrodes (PAD1) include a data pad that transmits a data voltage to a data wire (DL), a gate pad that transmits a clock signal, a start signal, a gate low voltage, a gate high voltage, etc. for driving a gate driver (GD) to the gate driver (GD), a high-potential power pad (VP1) that transmits a high-potential power voltage to a high-potential power wire (VL1), and a low-potential power pad (VP2) that transmits a low-potential power voltage to a low-potential power wire (VL2).

The plurality of pad areas include a first pad area (PA1) located at an upper edge of the display panel (PN) and a second pad area (PA2) of the display panel (PN). At this time, different types of first pad electrodes (PAD1) may be arranged in the first pad area (PA1) and the second pad area (PA2). For example, among the plurality of first pad electrodes (PAD1), a data pad, a gate pad, and a high-potential power pad (VP1) may be arranged in the first pad area (PA1), and a low-potential power pad (VP2) may be arranged in the second pad area (PA2).

At this time, each of the plurality of first pad electrodes (PAD1) may be formed with a different size. For example, the plurality of data pads that are connected one-to-one with the plurality of data lines (DL) may have a relatively narrow width, and the high-potential power pad (VP1), the low-potential power pad (VP2), and the gate pad may have a relatively wide width. However, the widths of the data pad, the gate pad, the high-potential power pad (VP1), and the low-potential power pad (VP2) illustrated in FIG. 3 are exemplary, and the size of the first pad electrode (PAD1) may be configured in various ways and is not limited thereto.

Meanwhile, in order to reduce the bezel of the display panel (PN), the edge of the display panel (PN) may be cut and removed. A plurality of pixels (PX), a plurality of wirings, and a plurality of first pad electrodes (PAD1) may be formed on an initial first substrate (110i), and an edge portion of the initial first substrate (110i) may be ground to reduce the bezel area. In the grinding process, a portion of the initial first substrate (110i) may be removed, so that a first substrate (110) having a smaller size may be formed. At this time, portions of the plurality of first pad electrodes (PAD1) and wirings arranged at the edge of the first substrate (110) may be removed. Accordingly, only a portion of the plurality of first pad electrodes (PAD1) may remain on the first substrate (110).

Next, a plurality of data lines (DL) extending in the column direction from a plurality of first pad electrodes (PAD1) are arranged on a first substrate (110) of a display panel (PN). The plurality of data lines (DL) may extend from a plurality of data pads of the first pad area (PA1) toward a plurality of pixel areas (UPAs). The plurality of data lines (DL) may extend in the column direction and may be arranged to overlap the plurality of pixel areas (UPAs). Accordingly, the plurality of data lines (DL) may transmit a data voltage to a pixel circuit of each of the plurality of sub-pixels (SP).

A plurality of high-potential power lines (VL1) extending in the column direction are arranged on a first substrate (110) of a display panel (PN). Some of the plurality of high-potential power lines (VL1) extend from the high-potential power pad (VP1) of the first pad area (PA1) toward the plurality of pixel areas (UPAs) to transmit a high-potential power voltage to the light-emitting elements (130) of each of the plurality of sub-pixels (SP). In addition, other some of the plurality of high-potential power lines (VL1) may be electrically connected to other high-potential power lines (VL1) via auxiliary high-potential power lines (AVL1) to be described later. In FIG. 3, for convenience of explanation, one high-potential power line (VL1) and one high-potential power pad (VP1) are illustrated as being arranged, but a plurality of high-potential power lines (VL1) and high-potential power pads (VP1) may be arranged.

A plurality of low-potential power lines (VL2) extending in the column direction are arranged on a first substrate (110) of a display panel (PN). At least some of the plurality of low-potential power lines (VL2) extend from a low-potential power pad (VP2) of a second pad area (PA2) toward a plurality of pixel areas (UPAs) to transmit a low-potential power voltage to a pixel circuit of each of a plurality of sub-pixels (SP). In addition, other some of the plurality of low-potential power lines (VL2) may be electrically connected to other low-potential power lines (VL2) via auxiliary low-potential power lines (AVL2) to be described later.

A plurality of scan lines (SL) extending in the row direction are arranged on a first substrate (110) of a display panel (PN). The plurality of scan lines (SL) extend in the row direction and can be arranged across a plurality of pixel areas (UPAs) and a plurality of gate driving areas (GA). The plurality of scan lines (SL) can transmit scan signals from a gate driving unit (GD) to pixel circuits of a plurality of sub-pixels (SP).

A plurality of auxiliary high-potential power lines (AVL1) extending in a row direction are arranged on a first substrate (110) of a display panel (PN). The plurality of auxiliary high-potential power lines (AVL1) may be arranged in an area between a plurality of pixel areas (UPAs). The plurality of auxiliary high-potential power lines (AVL1) extending in the row direction are electrically connected to the plurality of high-potential power lines (VL1) extending in the column direction through contact holes, and may form a mesh structure. Accordingly, the plurality of auxiliary high-potential power lines (AVL1) and the plurality of high-potential power lines (VL1) are configured to form a mesh structure, so that voltage drop and voltage deviation can be minimized.

A plurality of auxiliary low-potential power lines (AVL2) extending in a row direction are arranged on a first substrate (110) of a display panel (PN). The plurality of auxiliary low-potential power lines (AVL2) may be arranged in an area between a plurality of pixel areas (UPAs). The plurality of auxiliary low-potential power lines (AVL2) extending in the row direction may be electrically connected to the plurality of low-potential power lines (VL2) extending in the column direction through contact holes to form a mesh structure. Accordingly, the plurality of auxiliary low-potential power lines (AVL2) and the plurality of low-potential power lines (VL2) are configured to form a mesh structure, thereby reducing the resistance of the lines and minimizing voltage deviation.

Referring to FIGS. 3 and 4A, a plurality of gate driving wires (GVL) extending in the row direction and the column direction are arranged on a first substrate (110) of a display panel (PN). Some of the gate driving wires (GVL) extend from a gate pad of a first pad area (PA1) to a gate driving area (GA) and can transmit signals to a gate driving unit (GD). Others of the plurality of gate driving wires (GVL) extend in the row direction and can transmit signals to the gate driving units (GD) of the plurality of gate driving areas (GA). Accordingly, various signals from the gate driving wires (GVL) can be transmitted to the gate driving unit (GD) and the gate driving unit (GD) can be driven.

A plurality of gate drive lines (GVL) may include lines that transmit clock signals, start signals, gate high voltages, gate low voltages, etc. to the gate driver (GD). Accordingly, various signals may be transmitted from the gate drive lines (GVL) to the gate driver (GD), so that the gate driver (GD) may be driven.

For example, referring to FIG. 4A, the plurality of gate driving wires (GVL) may include gate power wires that transmit a power voltage to a gate driving unit (GD) of a gate driving region (GA). The plurality of gate power wires include a first gate power wire (VGHL) that transmits a gate high voltage to the gate driving unit (GD) and a second gate power wire (VGLL) that transmits a gate low voltage to the gate driving unit (GD).

A plurality of alignment keys are arranged in an area between a plurality of pixel areas (UPAs) in a display panel (PN). The plurality of alignment keys are used for alignment in a manufacturing process of the display panel (PN). The plurality of alignment keys include a first alignment key and a second alignment key.

The first align key may be placed in a gate driving area (GA) among the areas between the plurality of pixel areas (UPAs). The first align key may be used to check the alignment positions of the plurality of light emitting elements (130). For example, the first align key may be formed in a cross shape, but is not limited thereto.

The second align key may be arranged to overlap the high-potential power wiring (VL1) in an area between the plurality of pixel areas (UPAs). A hole overlapping the second align key is formed in the high-potential power wiring (VL1), so that the second align key and the high-potential power wiring (VL1) can be distinguished. The second align key may be used to align the display panel (PN) and the donor. The display panel (PN) and the donor may be aligned using the second align key, and the plurality of light-emitting elements (130) of the donor may be transferred to the display panel (PN). For example, the second align key may be formed in a circular ring shape, but is not limited thereto.

Hereinafter, a plurality of sub-pixels (SP) of a pixel area (UPA) will be described in more detail with reference to FIGS. 4a to 5.

Referring to FIGS. 4A and 4B, a plurality of sub-pixels (SP) forming a pixel are arranged in a pixel area (UPA). For example, the plurality of sub-pixels (SP) may include a first sub-pixel (SP1), a second sub-pixel (SP2), a third sub-pixel (SP3), and a fourth sub-pixel (SP4) that emit light of different colors. For example, the first sub-pixel (SP1) and the second sub-pixel (SP2) may be red sub-pixels, the third sub-pixel (SP3) may be green sub-pixels, and the fourth sub-pixel (SP4) may be blue sub-pixels, but is not limited thereto.

In the following description, it is assumed that one pixel includes one first sub-pixel (SP1), one second sub-pixel (SP2), one third sub-pixel (SP3), and one fourth sub-pixel (SP4), that is, two red sub-pixels, one green sub-pixel, and one blue sub-pixel; however, the configuration of the pixel is not limited thereto.

Referring to FIG. 4A, as described above, a plurality of wires are arranged to supply various signals to a plurality of sub-pixels (SP) in a plurality of pixel areas (UPAs) of the first substrate (110). For example, a plurality of data wires (DL), a plurality of high-potential power wires (VL1), and a plurality of low-potential power wires (VL2) extending in the column direction may be arranged on the first substrate (110). For example, a plurality of light-emitting control signal wires, a plurality of auxiliary high-potential power wires (AVL1), a plurality of auxiliary low-potential power wires (AVL2), a plurality of first scan wires (SL1), and a plurality of second scan wires (SL2) extending in the row direction may be arranged on the first substrate (110). In addition, the high-potential power wires (VL1) extending in the column direction may be electrically connected to the auxiliary high-potential power wires (AVL1) extending in the row direction through a contact hole. At this time, the light emission control signal wiring transmits the light emission control signal to the pixel circuits of the plurality of sub-pixels (SP), thereby controlling the light emission timing of each of the plurality of sub-pixels (SP).

And some of the gate drive lines (GVL) that transmit signals to each of the plurality of gate drivers (GDs) arranged spaced apart from each other with the pixel area (UPA) therebetween may extend in the row direction and be arranged across the pixel area (UPA). For example, a first gate power line (VGHL) that provides a gate high voltage to the gate driver (GD) and a second gate power line (VGLL) that provides a gate low voltage may be arranged across the pixel area (UPA).

Meanwhile, although the plurality of scan wires (SL) are illustrated as including the first scan wire (SL1) and the second scan wire (SL2), the configuration of the plurality of scan wires (SL) may vary depending on the pixel circuit configuration of the sub-pixel (SP), and is not limited thereto.

A pixel circuit for driving a light-emitting element (130) is arranged in each of a plurality of sub-pixels (SP) on a first substrate (110). The pixel circuit may include a plurality of thin film transistors and a plurality of capacitors. In FIGS. 4A and 5, only a driving transistor (DT), a first capacitor (C1), and a second capacitor (C2) among the configurations of the pixel circuit are illustrated for convenience of explanation, but the pixel circuit may further include a switching transistor, a sensing transistor, a light-emitting control transistor, and the like, but is not limited thereto.

First, a light-blocking layer (BSM) is disposed on the first substrate (110). The light-blocking layer (BSM) can block light incident on the active layer (ACT) of a plurality of transistors to minimize leakage current. For example, the light-blocking layer (BSM) can be disposed under the active layer (ACT) of the driving transistor (DT) to block light incident on the active layer (ACT). If light is irradiated on the active layer (ACT), leakage current may occur, which may deteriorate the reliability of the transistor. Therefore, a light-blocking layer (BSM) that blocks light can be disposed on the first substrate (110) to improve the reliability of the driving transistor (DT). The light-blocking layer (BSM) can be composed of an opaque conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

A buffer layer (111) is arranged on the light-shielding layer (BSM). The buffer layer (111) can reduce the penetration of moisture or impurities through the first substrate (110). The buffer layer (111) may be composed of a single layer or multiple layers of, for example, silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer (111) may be omitted depending on the type of the first substrate (110) or the type of the thin film transistor, and is not limited thereto.

A driving transistor (DT) including an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE) is placed on a buffer layer (111).

First, an active layer (ACT) of a driving transistor (DT) is arranged on a buffer layer (111). The active layer (ACT) may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto. In addition, although not shown in the drawing, other transistors such as a switching transistor, a sensing transistor, or a light-emitting control transistor other than the driving transistor (DT) may be additionally arranged, and the active layers of these transistors may also be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but are not limited thereto. In addition, the active layers of the transistors included in the pixel circuit, such as the driving transistor (DT), the switching transistor, the sensing transistor, and the light-emitting control transistor, may be made of the same material or may be made of different materials.

A gate insulating layer (112) is arranged on the active layer (ACT). The gate insulating layer (112) is an insulating layer for electrically insulating the active layer (ACT) and the gate electrode (GE), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A gate electrode (GE) is disposed on the gate insulating layer (112). The gate electrode (GE) may be composed of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

A first interlayer insulating layer (113) and a second interlayer insulating layer (114) are arranged on a gate electrode (GE). Contact holes are formed in the first interlayer insulating layer (113) and the second interlayer insulating layer (114) for connecting a source electrode (SE) and a drain electrode (DE) to an active layer (ACT), respectively. The first interlayer insulating layer (113) and the second interlayer insulating layer (114) are insulating layers for protecting a lower configuration, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

A source electrode (SE) and a drain electrode (DE) electrically connected to an active layer (ACT) are arranged on a second interlayer insulating layer (114). The source electrode (SE) is connected to a second capacitor (C2) and a first electrode (134) of a light-emitting element (130), and the drain electrode (DE) is connected to another component of a pixel circuit. The source electrode (SE) and the drain electrode (DE) may be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

Next, a first capacitor (C1) is placed on the gate insulating layer (112). The first capacitor (C1) includes a 1-1 capacitor electrode (C1a) and a 1-2 capacitor electrode (C1b).

First, a first-first capacitor electrode (C1a) is placed on the gate insulating layer (112). The first-first capacitor electrode (C1a) may be formed integrally with the gate electrode (GE) of the driving transistor (DT).

A first-second capacitor electrode (C1b) is arranged on the first interlayer insulating layer (113). The first-second capacitor electrode (C1b) is arranged to overlap the first-first capacitor electrode (C1a) with the first interlayer insulating layer (113) interposed therebetween.

Accordingly, the first capacitor (C1) is connected to the gate electrode (GE) of the driving transistor (DT) so as to maintain the voltage of the gate electrode (GE) of the driving transistor (DT) for a certain period of time.

Next, a second capacitor (C2) is placed on the first substrate (110). The second capacitor (C2) includes a 2-1 capacitor electrode (C2a), a 2-2 capacitor electrode (C2b), and a 2-3 capacitor electrode (C2c). The second capacitor (C2) includes a 2-1 capacitor electrode (C2a) which is a lower capacitor electrode, a 2-2 capacitor electrode (C2b) which is a middle capacitor electrode, and a 2-3 capacitor electrode (C2c) which is an upper capacitor electrode.

A second-first capacitor electrode (C2a) is placed on the first substrate (110). The second-first capacitor electrode (C2a) is placed on the same layer as the light-shielding layer (BSM) and may be made of the same material.

A second-second capacitor electrode (C2b) is disposed on the buffer layer (111) and the gate insulating layer (112). The second-second capacitor electrode (C2b) is disposed on the same layer as the gate electrode (GE) and may be made of the same material.

A 2-3 capacitor electrode (C2c) is arranged on the first interlayer insulating layer (113). The 2-3 capacitor electrode (C2c) may be composed of a first layer (C2c1) and a second layer (C2c2). The first layer (C2c1) of the 2-3 capacitor electrode (C2c) may be made of the same material as the 1-2 capacitor electrode (C1b) in the same layer. The first layer (C2c1) may be arranged to overlap the 2-1 capacitor electrode (C2a) and the 2-2 capacitor electrode (C2b) with the first interlayer insulating layer (113) therebetween.

The second layer (C2c2) of the second-third capacitor electrode (C2c) is disposed on the second interlayer insulating layer (114). The second layer (C2c2) may be connected to the first layer (C2c1) through a contact hole of the second interlayer insulating layer (114) as a portion extending from the source electrode (SE) of the driving transistor (DT).

Accordingly, the second capacitor (C2) is electrically connected between the source electrode (SE) of the driving transistor (DT) and the light-emitting element (130), so as to increase the capacitance inherent in the light-emitting element (130), and to enable the light-emitting element (130) to emit light of higher brightness.

A first passivation layer (115a) is arranged on the driving transistor (DT), the first capacitor (C1), and the second capacitor (C2). The first passivation layer (115a) is an insulating layer for protecting the structure under the first passivation layer (115a), and may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A first planarization layer (116a) is disposed on the first passivation layer (115a). The first planarization layer (116a) can planarize an upper portion of a pixel circuit including a driving transistor (DT). The first planarization layer (116a) can be composed of a single layer or multiple layers, and can be made of, for example, benzocyclobutene or an acrylic organic material, but is not limited thereto.

Referring to FIGS. 4b and 5 together, a plurality of reflectors (RF) are arranged on the first planarization layer (116a). The reflectors (RF) are configured to reflect light emitted from a plurality of light-emitting elements (130) toward an upper portion of the first substrate (110) and may be formed in a shape corresponding to each of the plurality of sub-pixels (SP). One reflector (RF) may be arranged to cover most of an area of one sub-pixel (SP). The reflector (RF) reflects light emitted from the light-emitting element (130) and may also be used as an electrode electrically connecting the light-emitting element (130) and the pixel circuit. Accordingly, the reflector (RF) may include various conductive layers in consideration of light reflection efficiency and resistance. For example, the reflector (RF) may use a transparent conductive layer such as ITO (Indium Tin Oxide) together with an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, but the structure of the reflector (RF) is not limited thereto.

The reflector (RF) includes a first reflector (RF1) corresponding to the first sub-pixel (SP1), a second reflector (RF2) corresponding to the second sub-pixel (SP2), a third reflector (RF3) corresponding to the third sub-pixel (SP3), and a fourth reflector (RF4) corresponding to the fourth sub-pixel (SP4).

The first reflector (RF1) includes a first-first reflector (RF1a) overlapping most of the first sub-pixel (SP1) and a first-second reflector (RF1b) overlapping the red light-emitting element (130R) of the first sub-pixel (SP1). The first-first reflector (RF1a) can reflect light emitted from the red light-emitting element (130R) toward an upper portion of the red light-emitting element (130R). In addition, the first-first reflector (RF1a) can be electrically connected to a source electrode (SE) of a driving transistor (DT) and a second capacitor (C2) through a first contact hole (CH1) of the first planarization layer (116a) and the first passivation layer (115a). Accordingly, the first-first reflector (RF1a) can electrically connect the driving transistor (DT) and the first electrode (134) of the red light-emitting element (130R). The first-second reflector (RF1b) can reflect light emitted from the red light-emitting element (130R) toward the upper portion of the red light-emitting element (130R). In addition, the first-second reflector (RF1b) can also function as an electrode that electrically connects the second electrode (135) of the red light-emitting element (130R) and the high-potential power wiring (VL1).

The second reflector (RF2) includes a second-first reflector (RF2a) overlapping most of the second sub-pixel (SP2) and a second-second reflector (RF2b) overlapping the red light-emitting element (130R) of the second sub-pixel (SP2). The second-first reflector (RF2a) can reflect light emitted from the red light-emitting element (130R) toward an upper portion of the red light-emitting element (130R). The second-first reflector (RF2a) is electrically connected to a source electrode (SE) of a driving transistor (DT) and a second capacitor (C2) through a first contact hole (CH1) to transmit a driving current from the driving transistor (DT) to a first electrode (134) of the red light-emitting element (130R). And the 2-2 reflector (RF2b) can be used as an electrode that electrically connects the second electrode (135) of the red light-emitting element (130R) and the high-potential power wiring (VL1) while reflecting the light emitted from the red light-emitting element (130R) toward the upper portion of the red light-emitting element (130R).

The third reflector (RF3) may be formed as a single third reflector (RF3) overlapping the entire third sub-pixel (SP3). The third reflector (RF3) may reflect light emitted from the green light-emitting element (130G) of the third sub-pixel (SP3) toward an upper portion of the green light-emitting element (130G). In addition, the third reflector (RF3) may be electrically connected to the source electrode (SE) of the driving transistor (DT) and the second capacitor (C2) through the first contact hole (CH1) to transmit the driving current from the driving transistor (DT) to the first electrode (134) of the green light-emitting element (130G).

The fourth reflector (RF4) may be formed as a single fourth reflector (RF4) overlapping the entire fourth sub-pixel (SP4). The fourth reflector (RF4) may reflect light emitted from the blue light-emitting element (130B) of the fourth sub-pixel (SP4) toward an upper portion of the blue light-emitting element (130B). In addition, the fourth reflector (RF4) may be electrically connected to the source electrode (SE) of the driving transistor (DT) and the second capacitor (C2) through the first contact hole (CH1) to transmit the driving current from the driving transistor (DT) to the first electrode (134) of the blue light-emitting element (130B).

Meanwhile, the first sub-pixel (SP1) and the second sub-pixel (SP2) are described as being composed of two reflectors (RF), and the third sub-pixel (SP3) and the fourth sub-pixel (SP4) are described as being composed of one reflector (RF), but the reflectors (RF) can be designed in various ways. For example, only one reflector (RF) may be arranged in all of the plurality of sub-pixels (SP), like the third sub-pixel (SP3) and the fourth sub-pixel (SP4), or a plurality of reflectors (RF) may be arranged in the first sub-pixel (SP1) and the second sub-pixel (SP2), but the present invention is not limited thereto.

In addition, it has been described that the red light-emitting element (130R) of each of the first sub-pixel (SP1) and the second sub-pixel (SP2) is electrically connected to the high-potential power wiring (VL1) through the first-second reflector (RF1b) and the second-second reflector (RF2b), but the red light-emitting element (130R), the green light-emitting element (130G), and the blue light-emitting element (130B) may all be separately connected to the high-potential power wiring (VL1) without the reflector (RF), and are not limited thereto.

Referring to FIG. 5, a second passivation layer (115b) is arranged on a plurality of reflectors (RF). The second passivation layer (115b) is an insulating layer for protecting the structure under the second passivation layer (115b), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

An adhesive layer (AD) is disposed on the second passivation layer (115b). The adhesive layer (AD) is formed on the front surface of the first substrate (110) and can fix the light-emitting element (130) disposed on the adhesive layer (AD). The adhesive layer (AD) may be made of a photocurable adhesive material that can be cured by light. For example, the adhesive layer (AD) may be made of an acrylic series material containing a photosensitive agent, but is not limited thereto. The adhesive layer (AD) may be formed on the front surface of the first substrate (110) except for a pad area where the first pad electrode (PAD1) is to be disposed.

A plurality of light-emitting elements (130) are arranged in each of a plurality of sub-pixels (SP) on an adhesive layer (AD). The light-emitting element (130) is an element that emits light by current, and may include a red light-emitting element (130R) that emits red light, a green light-emitting element (130G) that emits green light, and a light-emitting element (130) that emits blue light, and a combination of these may implement light of various colors, including white. For example, the light-emitting element (130) may be an LED (Light Emitting Diode) or a micro LED, but is not limited thereto.

One red light-emitting element (130R) is arranged in each of the first sub-pixel (SP1) and the second sub-pixel (SP2), one pair of green light-emitting elements (130G) is arranged in each of the third sub-pixel (SP3), and one pair of blue light-emitting elements (130B) is arranged in each of the fourth sub-pixel (SP4). That is, two red light-emitting elements (130R), two green light-emitting elements (130G), and two blue light-emitting elements (130B) may be arranged in each pixel. At this time, each of the red light-emitting elements (130R) may be individually driven by being connected to the driving transistor (DT) of each of the first sub-pixel (SP1) and the second sub-pixel (SP2). On the other hand, one pair of green light-emitting elements (130G) of the third sub-pixel (SP3) and one pair of blue light-emitting elements (130B) of the fourth sub-pixel (SP4) may be driven by being connected in parallel to one driving transistor (DT).

A plurality of light-emitting elements (130) include a first semiconductor layer (131), a light-emitting layer (132), a second semiconductor layer (133), a first electrode (134), and a second electrode (135).

A first semiconductor layer (131) is disposed on an adhesive layer (AD), and a second semiconductor layer (133) is disposed on the first semiconductor layer (131). The first semiconductor layer (131) and the second semiconductor layer (133) may be layers formed by doping n-type and p-type impurities into a specific material. For example, each of the first semiconductor layer (131) and the second semiconductor layer (133) may be layers in which n-type and p-type impurities are doped into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), and the like. In addition, the p-type impurities may be magnesium, zinc (Zn), beryllium (Be), and the n-type impurities may be silicon (Si), germanium, tin (Sn), and the like, but are not limited thereto.

A light-emitting layer (132) is arranged between the first semiconductor layer (131) and the second semiconductor layer (133). The light-emitting layer (132) can receive holes and electrons from the first semiconductor layer (131) and the second semiconductor layer (133) and emit light. The light-emitting layer (132) can be formed of a single-layer or multi-quantum well (MQW) structure, and can be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

A first electrode (134) is arranged on the first semiconductor layer (131). The first electrode (134) is an electrode for electrically connecting the driving transistor (DT) and the first semiconductor layer (131). In this case, the first semiconductor layer (131) is a semiconductor layer doped with an n-type impurity, and the first electrode (134) may be a cathode. The first electrode (134) may be arranged on an upper surface of the first semiconductor layer (131) exposed from the light-emitting layer (132) and the second semiconductor layer (133). The first electrode (134) may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

A second electrode (135) is disposed on the second semiconductor layer (133). The second electrode (135) may be disposed on the upper surface of the second semiconductor layer (133). The second electrode (135) is an electrode for electrically connecting the high-potential power wiring (VL1) and the second semiconductor layer (133). In this case, the second semiconductor layer (133) is a semiconductor layer doped with a p-type impurity, and the second electrode (135) may be an anode. The second electrode (135) may be composed of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

Next, a sealing film (136) is arranged to surround the first semiconductor layer (131), the light-emitting layer (132), the second semiconductor layer (133), the first electrode (134), and the second electrode (135). The sealing film (136) is made of an insulating material and can protect the first semiconductor layer (131), the light-emitting layer (132), and the second semiconductor layer (133). In addition, a contact hole exposing the first electrode (134) and the second electrode (135) is formed in the sealing film (136), so that the first connection electrode (CE1) and the second connection electrode (CE2) and the first electrode (134) and the second electrode (135) can be electrically connected.

Meanwhile, a part of the side surface of the first semiconductor layer (131) may be exposed from the sealing film (136). The light-emitting element (130) manufactured on the wafer may be separated from the wafer and transferred to the display panel (PN). However, a part of the sealing film (136) may be torn off in the process of separating the light-emitting element (130) from the wafer. For example, a part of the sealing film (136) adjacent to the lower edge of the first semiconductor layer (131) of the light-emitting element (130) may be torn off in the process of separating the light-emitting element (130) and the wafer, so that a part of the lower side surface of the first semiconductor layer (131) may be exposed to the outside. However, even if the lower part of the light-emitting element (130) is exposed from the sealing film (136), the first connection electrode (CE1) and the second connection electrode (CE2) are formed after the second planarization layer (116b) and the third planarization layer (116c) covering the side surface of the first semiconductor layer (131) are formed, so that short-circuit defects can be reduced.

Next, a second planarization layer (116b) and a third planarization layer (116c) are placed on the adhesive layer (AD) and the light-emitting element (130).

The second planarization layer (116b) can overlap part of the side surface of the plurality of light-emitting elements (130) to fix and protect the plurality of light-emitting elements (130). The second planarization layer (116b) can be formed using a halftone mask. Accordingly, the second planarization layer (116b) can be formed to have a step.

Specifically, a portion of the second planarization layer (116b) that is arranged relatively close to the light-emitting element (130) may be formed to have a relatively thin thickness, and a portion that is arranged relatively far from the light-emitting element (130) may be formed to have a relatively thick thickness. A portion of the second planarization layer (116b) that is arranged close to the light-emitting element (130) may be arranged to surround the light-emitting element (130) and may also be in contact with a side surface of the light-emitting element (130). Accordingly, in the process of separating the light-emitting element (130) from the wafer and transferring it to the display panel (PN), a portion of the sealing film (136) that protects the side surface of the first semiconductor layer (131) of the light-emitting element (130) may be torn off, and may be covered with the second planarization layer (116b). As a result, contact and short-circuit defects between the connection electrodes (CE1, CE2) and the first semiconductor layer (131) may be prevented in the future.

The third planarization layer (116c) is formed to cover the second planarization layer (116b) and the upper portion of the light-emitting element (130), and a contact hole through which the first electrode (134) and the second electrode (135) of the light-emitting element (130) are exposed can be formed. The first electrode (134) and the second electrode (135) of the light-emitting element (130) are exposed from the third planarization layer (116c), and the third planarization layer (116c) is partially disposed in the area between the first electrode (134) and the second electrode (135), so as to reduce short-circuit defects. The second planarization layer (116b) and the third planarization layer (116c) can be composed of a single layer or multiple layers, and can be made of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

Meanwhile, the third planarization layer (116c) may cover only the light-emitting element (130) and the area adjacent to the light-emitting element (130). The third planarization layer (116c) is arranged in the area of the sub-pixel (SP) surrounded by the bank (BB) and may be arranged in an island shape. Accordingly, the bank (BB) may be arranged on a part of the upper surface of the second planarization layer (116b), and the third planarization layer (116c) may be arranged on another part of the upper surface of the second planarization layer (116b).

A first connection electrode (CE1) and a second connection electrode (CE2) are arranged on a third planarization layer (116c). The first connection electrode (CE1) is an electrode that electrically connects the second electrode (135) of the light-emitting element (130) and the high-potential power wiring (VL1). The first connection electrode (CE1) can be electrically connected to the second electrode (135) of the light-emitting element (130) through a contact hole formed in the third planarization layer (116c).

The second connection electrode (CE2) is an electrode that electrically connects the first electrode (134) of the light-emitting element (130) and the driving transistor (DT). The second connection electrode (CE2) can be connected to the first-first reflector (RF1a), the first-second reflector (RF1b), the third reflector (RF3), and the fourth reflector (RF4) of each of the plurality of sub-pixels (SP) through contact holes formed in the third planarization layer (116c), the second planarization layer (116b), the adhesive layer (AD), and the second passivation layer (115b). At this time, since the first-first reflector (RF1a), the first-second reflector (RF1b), the third reflector (RF3), and the fourth reflector (RF4) are also connected to the source electrode (SE) of the driving transistor (DT), the source electrode (SE) of the driving transistor (DT) and the first electrode (134) of the light-emitting element (130) can be electrically connected to each other.

Meanwhile, in the drawing, the first electrode (134), the second connection electrode (CE2), and the reflector (RF) are depicted as being electrically connected to the source electrode (SE) of the driving transistor (DT), but the first electrode (134), the second connection electrode (CE2), and the reflector (RF) may be connected to the drain electrode (DE) of the driving transistor (DT), and are not limited thereto.

A bank (BB) is arranged on the second planarization layer (116b) exposed from the first connection electrode (CE1) and the second connection electrode (CE2) and the third planarization layer (116c). The bank (BB) may be arranged to be spaced apart from the light-emitting element (130) by a predetermined distance, and may overlap at least a portion of the reflector (RF). For example, the bank (BB) may cover a portion of the second connection electrode (CE2) formed in the contact hole of the third planarization layer (116c) and the second planarization layer (116b). In addition, the bank (BB) may be arranged on the second planarization layer (116b) at a predetermined distance from the light-emitting element (130), for example. In this case, the bank (BB) and the third planarization layer (116c) may be spaced apart from each other on a portion of the second planarization layer (116b) having a relatively thin thickness. That is, the end of the bank (BB) and the end of the third planarization layer (116c) can be spaced apart from each other on a portion of the second planarization layer (116b) having a relatively thin thickness formed by the halftone mask process.

The bank (BB) may be made of an opaque material to reduce color mixing between multiple sub-pixels (SP), and may be made of, for example, but not limited to, black resin.

Meanwhile, the thickness of a portion formed in the contact hole of the third planarization layer (116c) and the second planarization layer (116b) among the banks (BB) and covering a portion of the second connection electrode (CE2) may be different from the thickness of a portion disposed on the second planarization layer (116b). Specifically, in the case of a portion formed in the contact hole of the third planarization layer (116c) and the second planarization layer (116b) among the banks (BB) and covering a portion of the second connection electrode (CE2), since the contact hole is formed from the second passivation layer (115b) to the third planarization layer (116c), the bank (BB) may be disposed below the light-emitting element (130), that is, at a position lower than the light-emitting element (130). Accordingly, the thickness of the portion of the bank (BB) covering a part of the second connection electrode (CE2) formed within the contact hole of the third flattening layer (116c) and the second flattening layer (116b) may be thicker than the thickness of the portion of the bank (BB) disposed on the second flattening layer (116b).

A first protective layer (117) is arranged on the first connection electrode (CE1), the second connection electrode (CE2), and the bank (BB). The first protective layer (117) is a layer for protecting the configuration under the first protective layer (117), and may be composed of a single layer or multiple layers of a light-transmitting epoxy, silicon oxide (SiOx), or silicon nitride (SiNx), but is not limited thereto.

A plurality of first pad electrodes (PAD1) are arranged on a first pad area (PA1) and a second pad area (PA2) of a first substrate (110). Each of the plurality of first pad electrodes (PAD1) may be formed of a plurality of conductive layers. For example, each of the plurality of first pad electrodes (PAD1) includes a first conductive layer (PE1a), a second conductive layer (PE1b), and a third conductive layer (PE1c).

First, a first conductive layer (PE1a) is disposed on the second interlayer insulating layer (114). The first conductive layer (PE1a) may be made of the same conductive material as the source electrode (SE) and the drain electrode (DE), and may be made of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

A first passivation layer (115a) is disposed on a first conductive layer (PE1a), and a second conductive layer (PE1b) is disposed on the first passivation layer (115a). The second conductive layer (PE1b) may be made of the same conductive material as the reflector (RF), and may be made of, for example, silver (Ag), aluminum (Al), molybdenum (Mo), or an alloy thereof, but is not limited thereto.

A third conductive layer (PE1c) is disposed on the second conductive layer (PE1b). The third conductive layer (PE1c) may be made of the same conductive material as the first connection electrode (CE1) and the second connection electrode (CE2), for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

At this time, although not shown in the drawing, some of the plurality of conductive layers of the first pad electrode (PAD1) may be electrically connected to the plurality of wires on the first substrate (110) to supply various signals to the plurality of wires and the plurality of sub-pixels (SP). For example, the first conductive layer (PE1a) and/or the second conductive layer (PE1b) of the first pad electrode (PAD1) may be connected to the data wire (DL), the high-potential power wire (VL1), the low-potential power wire (VL2), etc. arranged in the display area (AA), to transmit signals to each of them.

And a first metal layer, a second metal layer, and a plurality of insulating layers may be arranged together under the first pad electrode (PAD1). By placing the first metal layer, the second metal layer, and a plurality of insulating layers under the first pad electrode (PAD1), the step of the first pad electrode (PAD1) can be adjusted. For example, a buffer layer (111), a gate insulating layer (112), a first metal layer, a first interlayer insulating layer (113), and a second metal layer may be sequentially arranged between the first pad electrode (PAD1) and the first substrate (110). The first metal layer may be made of the same conductive material as the gate electrode (GE), and the second metal layer may be made of the same conductive material as the first-second capacitor electrode (C1b). However, the plurality of insulating layers and the first metal layer and the second metal layer under the first pad electrode (PAD1) may be omitted depending on the design, and are not limited thereto.

A second substrate (120) is placed under the first substrate (110). The second substrate (120) is a substrate that supports components placed under the display device (100) and may be an insulating substrate. For example, the second substrate (120) may be made of glass or resin, etc. In addition, the second substrate (120) may be made of a polymer or plastic. The second substrate (120) may be made of the same material as the first substrate (110). In some embodiments, the second substrate (120) may be made of a plastic material having flexibility.

A bonding layer (BDL) is arranged between the first substrate (110) and the second substrate (120). The bonding layer (BDL) may be made of a material that can be hardened through various hardening methods to bond the first substrate (110) and the second substrate (120). The bonding layer (BDL) may be arranged only in a portion of the area between the first substrate (110) and the second substrate (120) or may be arranged in the entire area.

A plurality of second pad electrodes (PAD2) are arranged on the back surface of the second substrate (120). The plurality of second pad electrodes (PAD2) are electrodes for transmitting signals from a driving component arranged on the back surface of the second substrate (120) to a plurality of side wirings (SRL), a plurality of first pad electrodes (PAD1) on the first substrate (110), and a plurality of wirings. The plurality of second pad electrodes (PAD2) are arranged at an end portion of the second substrate (120) in a non-display area (NA) and can be electrically connected to a side wiring (SRL) covering the end portion of the second substrate (120).

At this time, a plurality of second pad electrodes (PAD2) may also be arranged corresponding to a plurality of pad areas. Each of a plurality of first pad electrodes (PAD1) may be arranged corresponding to each of a plurality of second pad electrodes (PAD2), and then the first pad electrodes (PAD1) and the second pad electrodes (PAD2) that overlap each other may be electrically connected through the side wiring (SRL).

Each of the plurality of second pad electrodes (PAD2) includes a plurality of conductive layers. For example, each of the plurality of second pad electrodes (PAD2) includes a fourth conductive layer (PE2a), a fifth conductive layer (PE2b), and a sixth conductive layer (PE2c).

First, a fourth conductive layer (PE2a) is placed under the second substrate (120). The fourth conductive layer (PE2a) may be made of a conductive material, and may be composed of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

A fifth conductive layer (PE2b) is disposed below the fourth conductive layer (PE2a). The fifth conductive layer (PE2b) may be composed of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

A sixth conductive layer (PE2c) is arranged below the fifth conductive layer (PE2b). The sixth conductive layer (PE2c) may be formed of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

And a second protective layer (121) is arranged on the remaining area of the second substrate (120). The second protective layer (121) can protect various wirings and driving components formed on the second substrate (120). The second protective layer (121) can be made of an organic insulating material, and for example, can be made of a benzocyclobutene or acrylic organic insulating material, but is not limited thereto.

Meanwhile, although not shown in the drawing, a driving component including a plurality of flexible films and a printed circuit board may be arranged on the back side of the second substrate (120). The plurality of flexible films are components in which various components, such as data driver ICs, are arranged on a flexible base film to supply signals to a plurality of sub-pixels (SP). The printed circuit board is a component that is electrically connected to the plurality of flexible films and supplies signals to the driving IC. Various components for supplying various signals to the driving IC may be arranged on the printed circuit board.

For example, the fourth conductive layer (PE2a) and/or the fifth conductive layer (PE2b) of the second pad electrode (PAD2) may extend toward a plurality of flexible films arranged on the back side of the second substrate (120) and be electrically connected to the plurality of flexible films, and the plurality of flexible films may supply various signals to the plurality of side wirings (SRL), the plurality of first pad electrodes (PAD1), the plurality of wirings, and the plurality of sub-pixels (SP) through the second pad electrode (PAD2). Accordingly, a signal from the driving component may be transmitted to the signal wiring on the front surface of the first substrate (110) and the plurality of sub-pixels (SP) through the plurality of second pad electrodes (PAD2), the side wirings (SRL) of the second substrate (120), and the plurality of first pad electrodes (PAD1) of the first substrate (110).

Next, a plurality of side wirings (SRL) are arranged on the side surfaces of the first substrate (110) and the second substrate (120). The plurality of side wirings (SRL) can electrically connect a plurality of first pad electrodes (PAD1) formed on the upper surface of the first substrate (110) and a plurality of second pad electrodes (PAD2) formed on the back surface of the second substrate (120). The plurality of side wirings (SRL) can be arranged to surround the side surface of the display device (100). Each of the plurality of side wirings (SRL) can cover the first pad electrode (PAD1) of the end surface of the first substrate (110), the side surface of the first substrate (110), the side surface of the second substrate (120), and the second pad electrode (PAD2) of the end surface of the second substrate (120). For example, multiple side wirings (SRLs) can be formed by pad printing using conductive inks, such as those containing silver (Ag), copper (Cu), molybdenum (Mo), and chromium (Cr).

A side insulating layer (140) covering a plurality of side wirings (SRL) is arranged. The side insulating layer (140) can be formed to cover the side wirings (SRL) on the upper surface of the first substrate (110), the side surface of the first substrate (110), the side surface of the second substrate (120), and the back surface of the second substrate (120). The side insulating layer (140) can protect the plurality of side wirings (SRL).

Meanwhile, when the plurality of side wirings (SRL) are made of a metal material, a problem may occur in which external light is reflected from the plurality of side wirings (SRL) or light emitted from the light emitting element (130) is reflected from the plurality of side wirings (SRL) and is visible to the user. Accordingly, the side insulating layer (140) may be configured to include a black material to suppress external light reflection. For example, the side insulating layer (140) may be formed by a pad printing method using an insulating material including a black material, for example, black ink.

A seal member (150) covering the side insulating layer (140) is arranged. The seal member (150) is arranged to surround the side of the display device (100) and can protect the display device (100) from external impact, moisture, oxygen, etc. For example, the seal member (150) may be made of an insulating material of the polyimide (PI), polyurethane, epoxy, and acrylic series, but is not limited thereto.

An optical film (MF) is disposed on the seal member (150), the side insulating layer (140), and the first protective layer (117). The optical film (MF) may be a functional film that protects the display device (100) while implementing a higher-quality image. For example, the optical film (MF) may include, but is not limited to, an anti-scattering film, an anti-glare film, an anti-reflecting film, a low-reflecting film, an OLED transmittance controllable film, or a polarizing plate.

Meanwhile, the edge of the seal member (150) and the edge of the optical film (MF) may be arranged on the same line. During the manufacturing process of the display device (100), an optical film (MF) having a larger size may be attached to the upper portion of the first substrate (110), and the seal member (150) covering the side insulating layer (140) may be formed. Thereafter, a laser may be irradiated to the seal member (150) and the optical film (MF) so as to correspond to the edge of the display device (100), thereby cutting a portion of the seal member (150) and the optical film (MF). Therefore, the size of the display device (100) may be adjusted through the outer cutting process of the seal member (150) and the optical film (MF), and the edge of the display device (100) may be formed flat.

Hereinafter, for a more detailed description of the power supply wires (VL) and a plurality of auxiliary power supply wires (AVL) arranged on the display panel (PN) of the display device, reference will be made to FIGS. 6 to 9.

FIG. 6 is a plan view of a display panel of a display device according to one embodiment of the present specification. FIG. 7 is an enlarged plan view of area A of FIG. 6. FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. 7. FIG. 9 is a cross-sectional view taken along line IX-IX' of FIG. 7.

According to one embodiment of the present specification, a power supply wire (VL) is extended in a first direction, and a plurality of auxiliary power supply wires (AVL) are extended in a second direction intersecting the first direction, so that the power supply wire (VL) and the plurality of auxiliary power supply wires (AVL) form a mesh structure, thereby minimizing voltage drop and voltage deviation.

Additionally, a power wire (VL) extending in a second direction from the top or bottom of the display panel (PN) may be further arranged. The power wire (VL) extending in the second direction from the top or bottom of the panel may be electrically connected to the power wire (VL) extending in the first direction.

For example, the power wiring (VL) extending in the second direction from the top or bottom of the display panel (PN) may be arranged inward of the display panel (PN) relative to the line for grinding the initial first substrate (110i).

The power wiring (VL) can be arranged on the same layer as the source electrodes (SE) and drain electrodes (DE) of multiple transistors.

Meanwhile, as multiple auxiliary power wiring, wiring that extended from one side of the board to the other side and formed in a single layer was used.

However, when using wiring that extends from one side of the substrate to the other side as a plurality of auxiliary power wiring and is formed as a single layer, there was a problem that a large amount of static electricity was generated in the plurality of auxiliary power wiring in the center of the substrate during the process. Specifically, when the substrate was lifted using a lift pin and an insulating layer was subsequently deposited by a CVD process, the load was concentrated near the lift pin located in the center of the substrate, causing the substrate to deform. A large amount of static electricity was generated around the deformed area of the substrate due to peeling electrification, and there was a problem that the plurality of auxiliary power wirings formed as a single layer burst due to the large amount of static electricity. When the plurality of auxiliary power wirings burst due to static electricity, the insulating layer positioned over the plurality of auxiliary power wirings was lost, and there was a problem that the wiring was disconnected when forming wiring made of the same material as the source electrode and drain electrode of the transistor over the plurality of auxiliary power wirings.

Accordingly, in one embodiment of the present specification, as illustrated in FIG. 7, a plurality of auxiliary power lines (AVL) are configured with a plurality of first parts (p1) arranged in a gate driving area (GA) and a plurality of second parts (p2) connecting the plurality of first parts (p1), thereby preventing the problem of a large amount of static electricity being generated in the plurality of auxiliary power lines (AVL) and the problem of wire breakage of the power lines (VL) resulting therefrom.

Specifically, according to one embodiment of the present specification, a plurality of auxiliary power lines (AVL) can be configured to be split so as to be disconnected in a central portion of the substrate, for example, in a gate driving area (GA). For example, the plurality of auxiliary power lines (AVL) can be configured to be split in a gate driving area (GA) arranged between two adjacent pixels (PX).

For example, each of the plurality of auxiliary power lines (AVL) can be configured by dividing into a plurality of first portions (p1) arranged in the gate driving area (GA) and a plurality of second portions (p2) electrically connecting the plurality of first portions (p1).

At this time, the first portion (p1) and the second portion (p2) may be positioned on different layers and may be electrically connected to each other in a bridge structure in the gate driving region (GA). For example, the plurality of second portions (p2) may be formed of the same material in the same layer as the light-shielding layer (BSM), and the plurality of first portions (p1) may be formed of the same material in the same layer as the closest conductive component among the conductive components disposed on the light-shielding layer (BSM), that is, the gate electrodes (GE) of the plurality of transistors.

One or more insulating layers (111, 112) may be arranged between the plurality of first portions (p1) and the plurality of second portions (p2). At this time, a contact hole may be arranged in one or more of the insulating layers (111, 112). For example, the plurality of first portions (p1) and the plurality of second portions (p2) may be electrically connected to each other through contact holes arranged in one or more of the insulating layers (111, 1112). The number of contact holes may be one or more, and for example, as the number of contact holes increases, it may be advantageous in terms of securing a contact area.

That is, by configuring a plurality of auxiliary power lines (AVL) to be divided into a first part (p1) and a second part (p2) in a gate driving area (GA) arranged between two adjacent pixels (PX), and at this time configuring the first part (p1) and the second part (p2) to be electrically connected to each other in a bridge structure, it is possible to prevent a problem in which a large amount of static electricity is generated in the plurality of auxiliary power lines (AVL) and a problem in which the generated static electricity is transferred to another location due to electrostatic charging.

According to one embodiment of the present specification, the power wiring (VL) may include a high-potential power wiring (VL1) and a low-potential power wiring (VL2), and the auxiliary power wiring (AVL) intersecting the power wiring (VL) may include a plurality of auxiliary high-potential power wirings (AVL1) and a plurality of low-potential power wirings (ALV2).

For example, when the power wiring (VL) is a high-potential power wiring (VL1), the plurality of auxiliary power wirings (AVL) may be a plurality of auxiliary high-potential power wirings (AVL1) connected to the high-potential power wiring (VL1).

Referring to FIG. 8 together, the first portion (p1) and the second portion (p2) of the plurality of auxiliary high-potential power lines (AVL1) in the gate driving region (GA) can be electrically connected to each other in one or more contact holes arranged in the buffer layer (111) and the gate insulating layer (112).

For example, when the power wiring (VL) is a low-potential power wiring (VL2), the plurality of auxiliary power wirings (AVL) may be a plurality of auxiliary low-potential power wirings (AVL2) connected to the low-potential power wiring (VL2).

Referring together to FIG. 9, the first portion (p1) and the second portion (p2) of the plurality of auxiliary low-potential power lines (AVL2) in the gate driving region (GA) can be electrically connected to each other in one or more contact holes arranged in the buffer layer (111) and the gate insulating layer (112).

In addition, according to one embodiment of the present specification, a plurality of auxiliary power lines (AVL) may be configured as a first portion (p1) and a second portion (p2), thereby extending from both sides of the substrate (100) to the ends of the substrate (100) to form a mesh structure with a plurality of power lines (VL).

A display device and a method of manufacturing the display device according to various embodiments of the present specification can be described as follows.

A display device according to one embodiment of the present specification includes a substrate including a display area including a plurality of sub-pixels and a plurality of gate driving areas extending in a first direction between the plurality of sub-pixels, and a non-display area surrounding the display area, a plurality of transistors respectively disposed in the plurality of sub-pixels, a gate driving unit disposed in the plurality of gate driving areas, a power supply wire extending in the first direction, and a plurality of auxiliary power supply wires extending in a second direction intersecting the first direction and connected to the power supply wires, wherein each of the plurality of auxiliary power supply wires includes a plurality of first portions disposed in the plurality of gate driving areas and a plurality of second portions connecting the plurality of first portions.

According to another feature of the present specification, the device may further include a shielding layer disposed under the plurality of transistors, the power wiring may be disposed in the same layer as the source electrodes and drain electrodes of the plurality of transistors, and the plurality of second portions may be disposed in the same layer as the shielding layer.

According to another feature of the present specification, the plurality of first portions can be disposed on the same layer as the closest conductive component among the conductive components disposed on the light-shielding layer.

According to another feature of the present specification, the plurality of first portions can be formed of the same material as the gate electrodes of the plurality of transistors.

According to another feature of the present specification, the device may further include one or more insulating layers disposed between the plurality of first portions and the plurality of second portions, and the plurality of first portions and the plurality of second portions may be electrically connected to each other through contact holes of the one or more insulating layers.

According to another feature of the present specification, the power wiring includes a high-potential power wiring, and the plurality of auxiliary power wirings may include a plurality of auxiliary high-potential power wirings connected to the high-potential power wiring.

According to another feature of the present specification, the non-display area of the substrate further includes a plurality of pads arranged and pad areas arranged on one side and the other side of the display area, and the high-potential power wiring can be connected to the high-potential power pads arranged in the pad area on one side of the display area.

According to another feature of the present specification, the power wiring includes a low-potential power wiring, and the plurality of auxiliary power wirings may include a plurality of auxiliary low-potential power wirings connected to the low-potential power wiring.

According to another feature of the present specification, the non-display area of the substrate further includes a plurality of pads arranged and pad areas arranged on one side and the other side of the display area, and the low-potential power wiring can be connected to the low-potential power pads arranged in the pad area on the other side of the display area.

According to another feature of the present specification, the plurality of auxiliary power wires can extend from both sides of the substrate to the ends of the substrate.

Although the embodiments of the present specification have been described in more detail with reference to the attached drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present specification. Accordingly, the embodiments disclosed in the present specification are not intended to limit the technical spirit of the present specification, but to explain, and the scope of the technical spirit of the present specification is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative and not restrictive in all respects.

TD: Tiling Display Device
100: Display device
PN: Display Panel
GD: Gate driver
DD: Data Driven
TC: Timing Controller
AA: Display Area
NA: Non-displayable area
UPA: Pixel Area
GA: Gate drive area
PA1: 1st pad area
PA2: Second pad area
PX: Pixel
SP: Sub Pixel
SP1: First sub-pixel
SP2: Second sub-pixel
SP3: Third sub-pixel
SL: Scan wiring
SL1: 1st scan wiring
SL2: Second scan wiring
DL: Data Wiring
VL: Power Wiring
AVL: Auxiliary Power Wiring
VL1: High potential power wiring
AVL1: Auxiliary high potential power wiring
VL2: Low voltage power wiring
AVL2: Auxiliary low voltage power wiring
GVL: Gate Drive Wiring
VGHL: 1st gate power wiring
VGLL: Second Gate Power Wiring
SRL: Side wiring
BSM: Shading layer
DT: Driver Transistor
ACT: Active layer
GE: Gate electrode
SE: Source electrode
DE: drain electrode
C1: First capacitor
C1a: 1-1 capacitor electrode
C1b: 1-2nd capacitor electrode
C2: Second capacitor
C2a: 2-1 capacitor electrode
C2b: 2nd-2nd capacitor electrode
C2c: 2nd-3rd capacitor electrode
C2c1: 1st floor
C2c2: Second floor
RF: Reflector
RF1: 1st reflector
RF1a: 1-1 reflector
RF1b: 1-2 reflector
RF2: Second Reflector
RF2a: 2-1 reflector
RF2b: 2-2 reflector
RF3: Third Reflector
RF4: 4th Reflector
CE: connecting electrode
CE1: First connecting electrode
CE2: Second connecting electrode
AD: Adhesive layer
BB: Bank
MF: Optical Film
BDL: Bonding Layer
PAD1: First pad electrode
PE1a: First Challenge Layer
PE1b: Second Challenge Layer
PE1c: 3rd Challenge Layer
PAD2: Second pad electrode
PE2a: 4th Challenge Layer
PE2b: 5th Challenge Layer
PE2c: 6th Challenge Layer
DP: Data Pad
GP: Gate Pad
VP1: High potential power pad
VP2: Low voltage power pad
110: 1st substrate
111: Buffer layer
112: Gate insulation layer
113: First interlayer insulation layer
114: Second interlayer insulation layer
115a: 1st passivation layer
115b: Second passivation layer
116a: 1st leveling layer
116b: 2nd flattening layer
116c: 3rd leveling layer
117: 1st protective layer
120: Second substrate
121: Second protective layer
130: Light-emitting element
131: First semiconductor layer
132: Emissive layer
133: Second semiconductor layer
134: First electrode
135: Second electrode
136: End of the envelope
130R: Red light emitting element
130G: Green light emitting element
130B: Blue light emitting element
140: Side insulation layer
150: Absence of seal
CH1: 1st contact hole
p1: Part 1 of the multiple auxiliary power wiring
p2: Second part of the multiple auxiliary power wiring

Claims (10)

A substrate including a display area including a plurality of sub-pixels and a plurality of gate driving areas extending in a first direction between the plurality of sub-pixels, and a non-display area surrounding the display area;
A plurality of transistors arranged in each of the plurality of sub-pixels;
A gate driving unit arranged in the plurality of gate driving areas;
Power wiring extending in the first direction; and
It includes a plurality of auxiliary power wires extending in a second direction intersecting with the first direction and connected to the power wires,
A display device, wherein each of the plurality of auxiliary power wires includes a plurality of first portions arranged in the plurality of gate driving regions and a plurality of second portions connecting the plurality of first portions. In the first paragraph,
Further comprising a light-shielding layer disposed below the plurality of transistors,
The above power wiring is arranged on the same layer as the source electrodes and drain electrodes of the plurality of transistors,
A display device, wherein the second plurality of parts are arranged on the same layer as the light-blocking layer. In the second paragraph,
A display device, wherein the plurality of first parts are arranged on the same layer as the closest conductive component among the conductive components arranged on the light-shielding layer. In the third paragraph,
A display device, wherein the plurality of first parts are made of the same material as the gate electrodes of the plurality of transistors. In the first paragraph,
Further comprising one or more insulating layers disposed between the plurality of first parts and the plurality of second parts,
A display device, wherein the plurality of first parts and the plurality of second parts are electrically connected to each other through contact holes of the one or more insulating layers. In the first paragraph,
The above power wiring includes high potential power wiring,
A display device, wherein the plurality of auxiliary power wires include a plurality of auxiliary high-potential power wires connected to the high-potential power wires. In Article 6,
The non-display area of the above substrate further includes a plurality of pads arranged on one side and the other side of the display area,
A display device, wherein the above high-potential power wiring is connected to a high-potential power pad arranged in a pad area on one side of the above display area. In the first paragraph,
The above power wiring includes low-potential power wiring,
A display device, wherein the plurality of auxiliary power wires include a plurality of auxiliary low-potential power wires connected to the low-potential power wires. In Article 8,
The non-display area of the above substrate further includes a plurality of pads arranged on one side and the other side of the display area,
A display device, wherein the above low-potential power wiring is connected to a low-potential power pad arranged in a pad area on the other side of the above display area. In the first paragraph,
A display device, wherein the plurality of auxiliary power wirings extend from both sides of the substrate to the ends of the substrate.

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