KR20240110758A - Storage device, and storage device including printed circuit board - Google Patents

Abstract

An electronic device according to an embodiment of the present disclosure includes: first to eighth memory devices; a memory controller configured to control first to eighth memory devices; a first signal line configured to electrically connect between the memory controller and the first branch point; a second signal line configured to electrically connect between the first branch point and the second branch point; a third signal line configured to electrically connect between the first branch point and the third branch point; a fourth signal line configured to electrically connect between the second branch point and the fourth branch point; a fifth signal line configured to electrically connect between the second branch point and the fifth branch point; a sixth signal line configured to electrically connect between the third branch point and the sixth branch point; It includes a seventh signal line configured to electrically connect between the third branch point and the seventh branch point, the first memory device and the second memory device are connected to the fourth branch point, and the third memory device and the fourth memory device are connected to the fourth branch point. It is connected to the fifth branch point, the fifth memory device and the sixth memory device are connected to the sixth branch point, the seventh memory device and the eighth memory device are connected to the seventh branch point, and the length of the second signal line is It is shorter than the length of the 4 signal line, and the length of the third signal line is shorter than the length of the sixth signal line.

Description

Electronic device, and electronic device including a printed circuit board {STORAGE DEVICE, AND STORAGE DEVICE INCLUDING PRINTED CIRCUIT BOARD}

This disclosure relates to semiconductor memories, and more particularly to electronic devices and electronic devices including printed circuit boards.

Semiconductor memories include volatile memory devices, such as SRAM and DRAM, where the stored data is lost when the power supply is cut off, and flash memory devices, such as PRAM, MRAM, RRAM, and FRAM, which retain the stored data even when the power supply is cut off. Divided into devices.

Electronic devices based on flash memory operate based on electrical signals. As an example, controllers and memory devices included in electronic devices communicate with each other through various signal lines. In order to improve the reliability of electronic devices, various techniques for maintaining signal reliability are being developed. However, as the operating speed of electronic devices increases and the degree of integration of electronic devices improves, it is difficult to maintain signal reliability using existing techniques.

An object of the present disclosure is to provide an electronic device with improved reliability, and an electronic device including a printed circuit board.

An electronic device according to an embodiment of the present disclosure includes: first to eighth memory devices; a memory controller configured to control the first to eighth memory devices; a first signal line configured to electrically connect between the memory controller and a first branch point; a second signal line configured to electrically connect between the first branch point and the second branch point; a third signal line configured to electrically connect between the first branch point and the third branch point; a fourth signal line configured to electrically connect between the second branch point and the fourth branch point; a fifth signal line configured to electrically connect between the second branch point and the fifth branch point; a sixth signal line configured to electrically connect between the third branch point and the sixth branch point; and a seventh signal line configured to electrically connect between the third branch point and the seventh branch point, wherein the first memory device and the second memory device are connected to the fourth branch point, and the third memory device and The fourth memory device is connected to the fifth branch point, the fifth memory device and the sixth memory device are connected to the sixth branch point, and the seventh memory device and the eighth memory device are connected to the seventh branch point. is connected to, the length of the second signal line is shorter than the length of the fourth signal line, and the length of the third signal line is shorter than the length of the sixth signal line.

An electronic device according to an embodiment of the present disclosure includes: first to fourth memory devices; a memory controller configured to control the first to fourth memory devices; a first signal line configured to electrically connect between the memory controller and a first branch point; a second signal line configured to electrically connect between the first branch point and the second branch point; a third signal line configured to electrically connect between the first branch point and the third branch point; a fourth signal line configured to electrically connect between the second branch point and the first memory device; a fifth signal line configured to electrically connect between the second branch point and the second memory device; a sixth signal line configured to electrically connect between the third branch point and the third memory device; a seventh signal line configured to electrically connect between the third branch point and the fourth memory device, wherein the length of the second signal line is shorter than the length of the fourth signal line, and the third signal line The length of is shorter than the length of the sixth signal line.

An electronic device according to an embodiment of the present disclosure includes: a printed circuit board including an upper surface and a lower surface; a memory controller mounted on the upper surface; first and second memory devices mounted on the upper surface; a third memory device mounted on the lower surface to face the first memory device; and a fourth memory device mounted on the lower surface to face the third memory device, wherein the printed circuit board has: a first branch spaced apart from the memory controller by a first distance and electrically connected to the memory controller. ; a second branch point spaced apart from the first branch point by a second distance and electrically connected to the first branch point, the first memory device, and the third memory device; and a third branch point spaced apart from the first branch point by the second distance and electrically connected to the first branch point, the second memory device, and the fourth memory device, and the second branch point and the first branch point. The distance between the memory devices is a third distance, the second distance is shorter than the third distance, and the distance between the second branch point and the second memory device is a fourth distance, and the fourth distance is shorter than the second distance. short.

According to embodiments of the present disclosure, the influence of reflected signals between memory devices can be attenuated by expanding a specific section of signal lines between a memory controller and memory devices. Accordingly, deterioration of signal reliability due to reflected signals can be prevented, and thus a printed circuit board, an electronic device, and an electronic device including a printed circuit board with improved reliability are provided.

1 is a block diagram showing an electronic device according to an embodiment of the present disclosure.
Figure 2 is a block diagram to explain signal flow between a memory controller and a memory device.
3A to 3C are block diagrams showing electronic devices according to an embodiment of the present disclosure.
Figure 4 is a block diagram showing an electronic device according to an embodiment of the present disclosure.
Figure 5 is a block diagram showing an electronic device according to an embodiment of the present disclosure.
Figure 6 is a block diagram showing an electronic device according to an embodiment of the present disclosure.
7A to 7C are block diagrams showing electronic devices according to embodiments of the present disclosure.
8A to 8C are block diagrams showing electronic devices according to an embodiment of the present disclosure.
Figure 9 is a block diagram showing an electronic device according to an embodiment of the present disclosure.
Figure 10 is a block diagram showing an electronic device according to an embodiment of the present disclosure.
Figure 11 is a block diagram showing an electronic device according to an embodiment of the present disclosure.
Figure 12 is a block diagram showing an electronic device according to an embodiment of the present disclosure.
13A and 13B are block diagrams showing an electronic device according to an embodiment of the present disclosure.
14A to 14C are block diagrams showing electronic devices according to an embodiment of the present disclosure.
15A to 15D are block diagrams showing electronic devices according to embodiments of the present disclosure.
FIG. 16 is a block diagram showing the channel of FIG. 14A in more detail.
17A to 17G are diagrams exemplarily showing a printed circuit board according to an embodiment of the present disclosure.
18A and 18B are timing diagrams for explaining the effect of removing a reflected signal according to an embodiment of the present disclosure.
FIG. 18C is a graph illustrating the effect of removing a reflected signal according to an embodiment of the present disclosure.
Figure 19 is a block diagram showing an SSD system to which an electronic device is applied according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described clearly and in detail so that a person skilled in the art can easily practice the present disclosure.

1 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Referring to FIG. 1 , the electronic device 100 may include a memory controller 110 and a plurality of memory devices 120 .

The memory controller 110 may control a plurality of memory devices 120 . For example, the memory controller 110 may control each of the memory devices 120 through a plurality of channels CH1 to CHn.

The plurality of memory devices 120 may operate based on signals received from the memory controller 110 through the plurality of channels CH1 to CHn. For example, each of the plurality of memory devices 120 stores data received through a plurality of channels (CH1 to CHn) under the control of the memory controller 110 or stores the stored data through a plurality of channels (CH1 It can be transmitted to the memory controller 110 through ~CHn).

In one embodiment, each of the plurality of memory devices 120 may be a NAND flash memory chip or a multi-chip package including a plurality of NAND flash memory chips, but the scope of the present disclosure is not limited thereto. Each of the plurality of memory devices 120 includes Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Phase-change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and FRAM ( It may be any one of various memory devices such as ferroelectric RAM).

In one embodiment, at least two or more memory devices may communicate with a memory controller through one channel (eg, the first channel CH1). That is, the electronic device 100 may have a multi-rank structure. For example, a signal to be transmitted to the first memory device connected to the first channel CH1 may be provided to other memory devices connected to the first channel CH1. At this time, reflected signals generated from other memory devices may flow into the first memory device. Alternatively, reflected signals generated at each branch point may flow into the first memory device. The incoming reflected signal may affect the signal received by the first memory device. In this case, the first memory device may not receive signals normally or may malfunction.

The electronic device 100 according to the present disclosure adjusts (for example, expands or reduces) the length of a channel in a specific section or the length of a signal line in a specific section between the memory controller 110 and the memory devices 120. , it is possible to reduce the influence of reflected signals between a plurality of memory devices connected to the same channel. The length of the signal line of the electronic device 100 according to the present disclosure is explained in more detail with reference to the drawings below.

The electronic device 100 according to the present disclosure may further include stubs between the memory controller 110 and the memory devices 120. For example, a stub may be a dummy signal line. One end of the stub may be connected to a branch point or a specific point, and the other end of the stub may be open without being connected to any other electrical path. Alternatively, one end of the stub may be electrically connected to a signal line (or one end of a signal line), and the other end of the stub may be open without being connected to another electrical path. By adding more stubs, the influence of reflected signals can be reduced. A description of the stub of the electronic device 100 according to the present disclosure is described in more detail with reference to the drawings below.

In one embodiment, each of the plurality of memory devices 120 may be a memory package including a plurality of memory chips (or dies). In one embodiment, each of the plurality of memory devices 120 includes a plurality of memory chips (or dies), so that the electronic device 100 with high capacity can be implemented. Hereinafter, for convenience of explanation, the term “memory device” is used, but the term “memory device” used in the present disclosure may refer to a memory package including a plurality of memory chips.

Figure 2 is a block diagram to explain signal flow between a memory controller and a memory device. Hereinafter, for convenience of explanation, one signal line among the first to fourth memory devices M1 to M4 connected to the first channel CH1 and a plurality of signal lines of the first channel CH1 is referenced. Embodiments of the present disclosure are described. However, the scope of the present disclosure is not limited thereto, and the first channel CH1 may further include a plurality of signal lines. Alternatively, the memory controller 11 may be further connected to other memory devices through the first channel CH1.

Referring to FIG. 2 , the memory controller 11 may be connected to the first to fourth memory devices M1 to M4 through signal lines S1 to S7 of the first channel CH1. In one embodiment, the signal lines S1 to S7 of the first channel CH1 are one for transmitting the data signal DQ or one of various control signals to at least one of the memory devices M1 to M4. It can point to the signal line of .

For example, one data signal DQ may be provided to each of the memory devices M1 to M4 through the signal lines S1 to S7. That is, each of the first to fourth memory devices M1 to M4 may be configured to receive the same signal from the memory controller 11 through the signal lines S1 to S7 of the first channel CH1. For this purpose, the signal lines (S1 to S7) may be divided into a plurality of sections (PR1 to PR3).

A plurality of sections (PR1 to PR3) can be divided based on branch points (B11, B21, B22). For example, the signal line S1 from the memory controller 11 to the first branch point B11 may be included in the first section PR1. The signal line S2 from the first branch point B11 to the second branch point B21 and the signal line S3 from the first branch point B11 to the third branch point B22 are included in the second section PR2. You can. Signal lines (S4, S5) from the second branch point (B21) to the first and second memory devices (M1, M2) and from the third branch point (B22) to the third and fourth memory devices (M3, M4) The signal lines S6 and S7 up to ) may be included in the third section PR3. That is, by branching the signal line through the branch points B11, B21, and B22, the memory controller 11 and each of the first to fourth memory devices M1 to M4 can be electrically connected to each other.

In one embodiment, the first section PR1 may include one signal line (ie, S1). The second section PR2 may include two signal lines S2 and S3. The third section PR3 may include four signal lines (S4, S5, S6, and S7). However, the scope of the present disclosure is not limited to this, and the number of signal lines in each section may change depending on the number of memory devices connected to one channel.

In one embodiment, the electronic device 10 may arrange the first branch point B11 close to the memory devices M1 to M4. Accordingly, the length from one end to the other end of the signal line S1 of the first section PR1 may be longer than the length from one end to the other end of the signal line S2 of the second section PR2.

In one embodiment, the memory controller 11 may use a separate control signal (eg, a chip select signal) to select a memory device to which a signal is to be transmitted. For example, when the memory controller 11 transmits an input signal to the first memory device (M1), the memory controller 11 activates the chip selection signal corresponding to the first memory device (M1). And the input signal can be transmitted through signal lines (S1 to S7). In one embodiment, the chip selection signal may be provided to the first to fourth memory devices M1 to M4 through different signal lines.

At this time, because the same input signal is provided to the other memory devices M2 to M4, a reflected wave or reflection signal may be generated in the other memory devices M2 to M4. For example, in order to transmit an input signal to the first memory device (M1), when the memory controller 11 transmits the input signal through the signal lines (S1 to S7), the input signal of the third memory device (M3) Reflected signals may occur at the terminal due to impedance mismatching.

In one embodiment, each of the memory devices M1 to M4 may include an on-die termination (ODT) resistor to achieve impedance matching. The ODT resistor can prevent reflected signals by achieving impedance matching between the signal line and the memory devices (M1 to M4). However, when the operating speed of the electronic device 100 is higher than a certain speed (i.e., when the electronic device 100 performs a high-speed operation), it may be difficult to attenuate the reflected signal through a general ODT resistance.

Alternatively, a reflected wave or reflection signal may be generated at each of the plurality of branch points B11, B21, and B22. For example, in order to transmit an input signal to the first memory device M1, when the memory controller 11 transmits the input signal through the signal lines S1 to S7, the impedance at the third branch point B22 Reflected signals may occur due to impedance mismatching. Signal distortion occurs due to the reflected signal, and because of this, the first memory device M1 may not be able to accurately determine the input signal.

For example, the reflected signal generated in the third memory device M3 may flow into the first memory device M1 through the signal lines S6, S3, S2, and S4. Alternatively, the reflected signal generated at the third branch point B22 may flow into the first memory device M1 through the signal lines S3, S2, and S4. That is, the first memory device M1 may receive not only an input signal from the memory controller 11 but also a reflected signal from the third memory device M3 or a reflected signal from the third branch point B22. In this case, the first memory device M1 may not be able to properly determine the input signal. Signal distortion occurs due to the reflected signal, and because of this, the first memory device M1 may not be able to accurately determine the input signal.

3A to 3C are block diagrams showing electronic devices according to an embodiment of the present disclosure. Hereinafter, for convenience of explanation, descriptions that overlap with the previously described components will be omitted.

Referring to FIG. 3A , the electronic device 100 may include a memory controller 110 and first to fourth memory devices M1 to M4. The memory controller 110 may be connected to the first to fourth memory devices M1 to M4 through signal lines SL11, SL21, SL22, SL31, SL32, SL33, and SL34 of the first channel CH1, respectively. . Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch points BP11, BP21, and BP22. Since this is similar to what was previously described, detailed description thereof is omitted.

The electronic device 100 according to the present disclosure may adjust the channel length of a specific section or the length of a signal line of a specific section in order to remove the influence of reflected signals between memory devices or reflected signals from branch points. For example, differently from what is shown in FIG. 2A, according to the embodiment of FIG. 3A, the length (e.g., first length L1) of the signal lines SL11 of the first section PR1 and the second It may be equal to the length (eg, second length L2) of the signal lines SL21 and SL22 of the section PR2. That is, the length of the signal lines SL21 and 22 of the second section PR2 may be extended.

For example, the first length L1 indicates the length from one end to the other end of the signal line SL11 of the first section PR1. That is, the first length L1 may correspond to the distance from the memory controller 110 to the first branch point BP11. The second length L2 indicates the length from one end to the other end of each of the signal lines SL21 and SL22 of the second section PR2. That is, the second length L2 may correspond to the distance from the first branch point BP11 to the second branch point BP21 or the distance from the first branch point BP11 to the third branch point BP22.

In other words, the length of the signal lines SL11 in FIG. 3A may be shorter than the length of the signal lines S1 in FIG. 2A. Alternatively, the length of the signal lines SL21 and SL22 in FIG. 3A may be longer than the length of the signal lines S2 and S3 in FIG. 2A.

In one embodiment, compared to FIG. 2A, the first length L1 is reduced and the second length L2 is increased, resulting in a ratio of the first length L1 to the second length L2 of 1. :1. The length of each of the signal lines SL21 and SL22 of the second section PR2 is such that the reflected signal from the third or fourth memory device M3, M4 or the reflected signal from the third branch point BP22 is transmitted to the first or fourth section PR2. The length may be the same as the signal line SL11 of the first section PR1 so as not to affect the input signal to the second memory devices M1 and M2. Alternatively, the length of each of the signal lines SL21 and SL22 in the second section PR2 may be equal to the length of the signal line SL11 in the first section PR1 so that the reflected signal is attenuated below a certain level. At this time, the specific level is such that the reflected signal from the third or fourth memory devices M3, M4 or the third branch point BP22 does not affect the input signal to the first or second memory devices M1, M2. It may be an unknown signal level.

As described above, by making the first length L1 and the second length L2 the same, the reflected signal generated at the branch point can be attenuated below a specific level. That is, as the reflected signal is attenuated below a certain level, its influence on the input signal provided to the activated memory device may be reduced.

Referring to FIG. 3B, unlike shown in FIG. 3A, the length of the signal lines SL11 of the first section PR1 (for example, the first length L1) is longer than that of the signal of the second section PR2. The length of each of the lines SL21 and SL22 (eg, the second length L2) may be long.

In other words, the length of the signal lines SL11 in FIG. 3B may be shorter than the length of the signal lines SL11 in FIG. 3A. Alternatively, the length of each of the signal lines SL21 and SL22 in FIG. 3B may be longer than the length of the signal lines SL21 and SL22 in FIG. 3A.

In one embodiment, compared to FIG. 2A, the first length L1 is reduced and the second length L2 is increased, resulting in a ratio of the first length L1 to the second length L2 of 3. It could be /7. Accordingly, the signal lines of the second section PR2 are connected so that the reflected signals occurring at the branch points B21 and B22 in the second section PR2 do not affect the input signals to the memory devices M1 to M4. The length of (SL21, SL22) can be extended.

Referring to FIG. 3C, unlike shown in FIG. 3A, the length of the signal lines SL11 of the first section PR1 (for example, the first length L1) is longer than that of the signal of the second section PR2. The length of the lines SL21 and SL22 (eg, the second length L2) may be short.

In other words, the length of the signal lines SL11 in FIG. 3C may be longer than the length of the signal lines SL11 in FIG. 3A. Alternatively, the length of the signal lines SL21 and SL22 in FIG. 3B may be shorter than the length of the signal lines SL21 and SL22 in FIG. 3A.

In one embodiment, compared to FIG. 2A, the first length L1 is reduced and the second length L2 is increased, resulting in a ratio of the first length L1 to the second length L2 of 7. It could be /3. Accordingly, the signal lines of the second section PR2 are connected so that the reflected signals occurring at the branch points B21 and B22 in the second section PR2 do not affect the input signals to the memory devices M1 to M4. The length of (SL21, SL22) can be extended.

As described above, compared to FIG. 2A, the first length L1 is reduced and the second length L2 is increased, resulting in a ratio of the first length L1 and the second length L2. It may be a set ratio. For example, the ratio of the first length (L1) to the second length (L2) may be about 3/7 to 7/3. Alternatively, the second length (L2) may be about 0.43 to 2.33 times the first length (L1). Accordingly, the influence of the reflected signal can be reduced.

Figure 4 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Hereinafter, for convenience of explanation, descriptions that overlap with the previously described components will be omitted. Unlike shown in FIGS. 3A to 3C , in FIG. 4 , the length of the third section PR3 may be longer than the length of the second section PR2.

Referring to FIG. 4 , the electronic device 200 may include a memory controller 210 and first to fourth memory devices M1 to M4. The memory controller 210 may be connected to the first to fourth memory devices M1 to M4 through signal lines SL11, SL21, SL22, SL31, SL32, SL33, and SL34 of the first channel CH1, respectively. . Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch points BP11, BP21, and BP22. Since this is similar to what was previously described, detailed description thereof is omitted.

For example, the first length L11 indicates the length from one end to the other end of the signal line SL11 of the first section PR1. That is, the first length L11 may correspond to the distance from the memory controller 210 to the first branch point BP11. The second length L12 indicates the length from one end to the other end of each of the signal lines SL21 and SL22 of the second section PR2. That is, the second length L12 may correspond to the distance from the first branch point BP11 to the second branch point BP21 or the distance from the first branch point BP11 to the third branch point BP22. The third length L13 indicates the length from one end to the other end of each of the signal lines SL31, SL32, SL33, and SL34 of the third section PR3. That is, the third length L13 is the distance from the second branch point BP21 to the first memory device M1, the distance from the second branch point BP21 to the second memory device M2, and the third branch point BP22. ) may correspond to the distance from the third memory device M3, or from the third branch point BP22 to the fourth memory device M4. The fourth length L14 may indicate the sum of the second length L12 and the third length L13.

The electronic device 100 according to the present disclosure may adjust the channel length of a specific section or the length of a signal line of a specific section in order to remove the influence of reflected signals between memory devices or reflected signals from branch points. In one embodiment, the second length L12 may be shorter than the third length L13. For example, the length of the signal lines SL21 and SL22 of the second section PR2 may be shorter than the length of the signal lines SL31, SL32, SL33, and SL34 of the third section PR3. In one embodiment, the first length L11 may be (eg, substantially) equal to the fourth length L14. That is, the length of the signal lines SL21 and 22 of the second section PR2 or the length of the signal lines SL31, SL32, SL33, and SL34 of the third section PR3 may be extended.

In one embodiment, the length of the signal lines SL21 and SL22 of the second section PR2 is set to offset reflected signals from the memory devices M1 to M4 or the branch points BP11, BP21, and BP22. It can be. For example, the length of each of the signal lines SL21 and SL22 of the second section PR2 is a reflected signal from the third or fourth memory device M3 and M4 or a reflected signal from the third branch point BP22. may be set to a level that does not affect the input signal to the first or second memory devices M1 and M2. For another example, the length of each of the signal lines SL21 and SL22 of the second section PR2 is a reflection signal from the first or second memory device M1 and M2 or a reflection from the second branch point BP21. The signal may be set so that it does not affect the input signal to the third or fourth memory devices M3 and M4. Alternatively, the length of each of the signal lines SL21 and SL22 of the second section PR2 may be set so that the reflected signal is attenuated below a specific level. At this time, the specific level is such that the reflected signal from the third or fourth memory devices M3, M4 or the third branch point BP22 does not affect the input signal to the first or second memory devices M1, M2. It may be an unknown signal level.

As described above, the first length L11 and the fourth length L14 are set to be equal (e.g., substantially), or the second length L12 is set to be shorter than the third length L13. Thus, the reflected signal generated at the branch point can be attenuated below a certain level. That is, as the reflected signal is attenuated below a certain level, its influence on the input signal provided to the activated memory device may be reduced.

Figure 5 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Unlike shown in FIG. 3A, according to the embodiment of FIG. 5, the length (eg, second length L2) of the first signal line SL21 of the second section PR2 and the second section PR2 ) of the second signal line SL22 (for example, the third length L3) may be different from each other.

In one embodiment, the length L2 of the first signal line SL21 of the second section PR2 is the length of the signal line SL11 of the first section PR1 (for example, the first length L1 ) may be the same as The length (eg, third length L3) of the second signal line SL22 of the second section PR2 may be shorter than the length L1 of the signal line SL11 of the first section PR1. . That is, the lengths of signal lines included in each section PR1, PR2, and PR3 may be the same or different.

In one embodiment, even though the signal lines SL21 and SL22 of the second section PR2 have different lengths, each of the signal lines SL21 and SL22 of the second section PR2 and the first section PR1 The signal line may have a predetermined ratio. For example, as described in FIGS. 3A to 3C, the ratio of the length of the signal line SL11 of the first section PR1 to the length of each of the signal lines SL21 and SL22 of the second section PR2 may be 3/7 to 7/3.

In FIG. 5, the length of the first signal line SL21 of the second section PR2 is shown to be longer than the length of the second signal line SL22 of the second section PR2, but the scope of the present disclosure is limited thereto. It doesn't work. The length of the first signal line SL21 of the second section PR2 may be shorter than the length of the second signal line SL22 of the second section PR2.

Figure 6 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Referring to FIG. 6, hereinafter, for convenience of explanation, descriptions that overlap with the previously described components will be omitted. Referring to FIG. 6 , the electronic device 300 may include a memory controller 310 and first to eighth memory devices M1 to M8. The memory controller 310 connects the first to eighth memory devices M1 to M8 through the signal lines SL11, SL21, SL22, SL31, SL32, SL33, SL34, and SL41 to SL48 of the first channel (CH). ) can be connected to. Similar to what was described above, the signal lines of the first channel (CH1) can be divided based on branch points (BP11, BP21, BP22, BP31, BP32, BP33, and BP34). Since this is similar to what was previously described, detailed description thereof is omitted. Unlike the electronic devices 100 and 200 described with reference to FIGS. 2 to 5, the electronic device 300 described with reference to FIG. 6 includes additional memory devices (e.g., fifth to eighth memory devices (e.g., fifth to eighth memory devices) It may include M5~M8)).

For example, the first length L21 indicates the length from one end to the other end of the signal line SL11 of the first section PR1. That is, the first length L21 may correspond to the distance from the memory controller 310 to the first branch point BP11. The second length L22 indicates the length from one end to the other end of each of the signal lines SL21 and SL22 of the second section PR2. That is, the second length L22 may correspond to the distance from the first branch point BP11 to the second branch point BP21 or the distance from the first branch point BP11 to the third branch point BP22. The third length L23 indicates the length from one end to the other end of each of the signal lines SL31, SL32, SL33, and SL34 of the third section PR3. That is, the third length L23 is the distance from the second branch point BP21 to the fourth branch point BP31, the distance from the second branch point BP21 to the fifth branch point BP32, and the distance from the third branch point BP22 to the third branch point BP22. It may correspond to the distance to the sixth branch point (BP33), or the distance from the third branch point (BP22) to the seventh branch point (BP34).

The fourth length L24 indicates the length from one end to the other end of the signal lines SL41 to SL48 of the fourth section PR4. That is, the fourth length L24 is the distance from the fourth branch point BP31 to the first memory device M1, the distance from the fourth branch point BP31 to the second memory device M2, and the fifth branch point BP31. ) to the third memory device (M3), the distance from the fifth branch point (BP32) to the fourth memory device (M4), the distance from the sixth branch point (BP33) to the fifth memory device (M5), The distance from the 6th branch point (BP33) to the sixth memory device (M6), the distance from the 7th branch point (BP34) to the 7th memory device (M7), or the distance from the 7th branch point (BP34) to the 8th memory device (M8) It can respond to distances up to . The fifth length L25 may be the sum of the second length L22, the third length L23, and the fourth length L25.

The electronic device 300 according to the present disclosure may adjust the channel length of a specific section or the length of a signal line of a specific section in order to remove the influence of reflected signals between memory devices or reflected signals from branch points. In one embodiment, the second length L22 may be shorter than the third length L23. For example, the length of the signal lines SL21 and SL22 of the second section PR2 may be shorter than the length of the signal lines SL31, SL32, SL33, and SL34 of the third section PR3. In one embodiment, the first length L21 may be (eg, substantially) equal to the fifth length L25. That is, the length of the signal lines SL21 and 22 of the second section PR2 or the length of the signal lines SL31, SL32, SL33, and SL34 of the third section PR3 may be extended.

In one embodiment, the length of the signal lines SL21 and SL22 of the second section PR2 is the same as that of the memory devices M1 to M8 or the branch points BP11, BP21, BP22, BP31, BP32, BP33, and BP34. It can be set to cancel reflected signals from For example, the length of each of the signal lines SL21 and SL22 of the second section PR2 is the reflected signal from the third to eighth memory devices M3 to M8, or branch points (e.g., The reflected signal from the fifth branch point BP32, etc.) may be set to a level where it does not affect the input signal to the first or second memory devices M1 and M2. For another example, the length of each of the signal lines SL21 and SL22 of the second section PR2 is the reflected signal from the first to sixth memory devices M1 to M6, or branch points (e.g. , the sixth branch point B33, etc.) may be set so that the reflected signal does not affect the input signal to the seventh or eighth memory devices M7 and M8. Likewise, to prevent reflected signals from other memory devices or branch points from affecting the input signals to the third to sixth memory devices M3 to M6, the signal lines SL21 and SL22 of the second section PR2 ) Each length can be set.

As described above, the first length L11 and the fifth length L25 are set to be equal (e.g., substantially), or the second length L22 is set to be shorter than the third length L23. Thus, the reflected signal generated at the branch point can be attenuated below a certain level. That is, as the reflected signal is attenuated below a certain level, its influence on the input signal provided to the activated memory device may be reduced.

7A to 7C are block diagrams showing electronic devices according to embodiments of the present disclosure. Hereinafter, for convenience of explanation, descriptions that overlap with the previously described components will be omitted. Referring to FIG. 7A , the electronic device 400 may include a memory controller 410 and first to fourth memory devices M1 to M4. The memory controller 410 may be connected to the first to fourth memory devices M1 to M4 through signal lines SL11, SL21, SL22, SL31, SL32, SL33, and SL34 of the first channel CH1, respectively. . Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch points BP11, BP21, and BP22. Since this is similar to what was previously described, detailed description thereof is omitted.

In one embodiment, the length of the signal lines (SL31, SL32, SL33, and SL34) of the third section is shorter than the length of the signal lines (SL11, SL21, and SL22) of the first and second sections (PR1 and PR2). You can. For example, the signal lines SL31, SL32, SL33, and SL34 of the third section may be micro signal lines.

The electronic device 400 may further include stubs ST1 and ST2. One end of each of the stubs ST1 and ST2 may be connected to a corresponding branch point, and the other end may be open without being connected to another electrical path. For example, one end of the first stub (ST1) may be connected to the second branch point (BP21), and the other end may be open without being connected to any other electrical path. One end of the second stub (ST2) may be connected to the third branch point (BP22), and the other end may be open without being connected to any other electrical path. For example, stubs can be dummy signal lines.

The length from one end to the other end of each of the stubs ST1 and ST2 may be the same as the length of the signal lines SL31 to SL34 of the third section PR3. The fourth length L4 indicates the distance or length from one end to the other end of the signal lines SL31 to SL34 of the third section PR3. That is, the fourth length L4 may correspond to the distance from the second branch point BP21 or the third branch point BP22 to the memory devices M1 to M4. The length of each of the stubs ST1 and ST2 may be equal to the fourth length L4.

As described above, the electronic device 400 may further include stubs ST1 and ST2 at the branch points BP21 and BP22 to the extent that the reflected signal does not affect the input signal to the memory device. Alternatively, the electronic device 400 may further include stubs ST1 and ST2 at the branch points BP21 and BP22 so that the reflected signal is attenuated below a certain level. Accordingly, the signal reflected from each end of the stubs ST1 and ST2 can compensate for signal distortion caused by the reflected signal. Accordingly, signal characteristics of electronic devices that perform high-speed operations can be improved.

The electronic device 400 according to an embodiment of the present disclosure can attenuate the influence of the reflected signal by adjusting the length of each of the stubs ST1 and ST2. The length of each of the stubs ST1 and ST2 may be determined based on the length of the signal lines SL31 to SL34 of the third section PR3 so that the influence of the reflected signal is removed or attenuated.

Referring to FIG. 7B, the length of each of the stubs ST1 and ST2 (e.g., the fifth length L5) is the length of the signal lines SL31 to SL34 of the third section PR3 (e.g. , may be different from the fourth length (L4)). The fifth length L5 indicates the distance or length from one end to the other end of each of the stubs ST1 and ST2.

In one embodiment, the length from one end to the other end of the stubs ST1 and ST2 may be shorter than the length from one end to the other end of the signal lines SL31 to SL34 of the third section PR3. That is, the fifth length L5 may be shorter than the fourth length L4. For example, the length of the stubs ST1 and ST2 may be at least 0.1 times the length of the signal lines SL31 to SL34 of the third section PR3. Alternatively, the length of the stubs ST1 and ST2 may be at least 1 mm.

Referring to FIG. 7C, the length of each of the stubs ST1 and ST2 (e.g., the fifth length L5) is the length of the signal lines SL31 to SL34 of the third section PR3 (e.g. , may be different from the fourth length (L4)).

In one embodiment, the length from one end to the other end of the stubs ST1 and ST2 may be longer than the length from one end to the other end of the signal lines SL31 to SL34 of the third section PR3. That is, the fifth length L5 may be longer than the fourth length L4. For example, the length of the stubs ST1 and ST2 may be up to 5 times the length of the signal lines SL31 to SL34 of the third section PR3.

As described above, the length of the stubs ST1 and ST2 can be adjusted such that the reflected signal does not affect the input signal to the memory device. Alternatively, the length of the stubs ST1 and ST2 may be adjusted based on the signal lines SL31 to SL34 of the third section PR3 so that the reflected signal is attenuated below a certain level. The length of the stubs ST1 and ST2 may be the same as or different from the length of the signal lines SL31 to SL34 of the third section PR3. The length of the stubs ST1 and ST2 may be k times the length of the signal lines SL31 to SL34 of the third section PR3. At this time, k may be 0.1 to 5. Alternatively, the length of the stubs ST1 and ST2 may be 1 mm or more and may be 5 times or less the length of the signal lines SL31 to SL34 of the third section PR3.

In one embodiment, as shown in FIGS. 7A to 7C, the length of the first stub (ST1) may be the same as the length of the second stub (ST2). However, the scope of the present disclosure is not limited thereto. The length of the first stub (ST1) and the length of the second stub (ST2) may be different from each other.

In one embodiment, as shown in FIGS. 7A to 7C, in the electronic device 400 including stubs, the length of the signal line SL11 of the first section PR1 and the signal of the second section PR2 The lengths of the lines SL21 and SL22 may be the same. However, the scope of the present disclosure is not limited thereto. As described above, the length of the signal line SL11 of the first section PR1 and the lengths of the signal lines SL21 and SL22 of the second section PR2 may be the same or different. The length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 may have a predetermined ratio. For example, the predetermined ratio may be 3/7 to 7/3.

8A to 8C are block diagrams showing electronic devices according to embodiments of the present disclosure. Hereinafter, for convenience of explanation, descriptions that overlap with the previously described components will be omitted. The electronic device 500 may be the same as or similar to the electronic device 300 of FIG. 6 . Referring to FIG. 8 , the electronic device 500 may include first to eighth memory devices M1 to M8. Referring to FIG. 6 together, the first to eighth memory devices M1 to M8 have signal lines SL11, SL21, SL22, SL31, SL32, SL33, SL34, SL41, SL42, SL43, SL44, SL45, and SL46. , SL47, and SL48), respectively, can be connected to the first to eighth memory devices M1 to M8.

For convenience of explanation in FIGS. 8A to 8C , the memory controller 310, the signal line SL11 of the first section PR1, the signal lines SL21 and SL22 of the second section PR2, and the third section The illustration and description of the signal lines (SL31, SL32, SL33, SL34) and branch points (BP11, BP21, BP22) of (PR3) may be omitted, but may be the same as or similar to those shown and described in FIG. 6. It must be understood. In one embodiment, the second length L22 of the second section PR2 of the electronic device 500 of FIGS. 8A to 8C may be shorter than the third length L23 of the third section PR3.

In one embodiment, the lengths of the signal lines (SL41, SL42, SL43, SL44, SL45, SL46, SL47, and SL48) of the fourth section are the same as those of the first, second, and third signal sections (PR1, PR2, and PR3). It may be shorter than the length of the signal lines (SL11, SL21, SL22, SL31, SL32, SL33, and SL34). For example, the signal lines (SL41 to SL48) of the fourth section may be micro signal lines.

The electronic device 500 may further include stubs ST11 to ST14. One end of each of the stubs (ST11 to ST14) is connected to a corresponding branch point, and the other end may be open without being connected to another electrical path. For example, one end of the first stub (ST11) may be connected to the fourth branch point (BP31), and the other end may be open without being connected to any other electrical path. One end of the second stub (ST12) may be connected to the fifth branch point (BP32), and the other end may be open without being connected to any other electrical path. Likewise, one end of the third stub (ST13) may be connected to the sixth branch point (BP33), and the other end may be open without being connected to any other electrical path. One end of the fourth stub (ST14) may be connected to the seventh branch point (BP34), and the other end may be open without being connected to any other electrical path. For example, stubs can be dummy signal lines.

The length from one end to the other end of each of the stubs (ST11 to ST14) may be the same as the length of the signal lines (SL41 to SL48) of the fourth section (PR4). The fourth length L24 indicates the distance or length from one end to the other end of the signal lines SL41 to SL48 of the fourth section PR4. That is, the fourth length L24 is the distance from the fourth branch point BP31, the fifth branch point BP32, the sixth branch point BP33, or the seventh branch point BP34 to the memory devices M1 to M8. We can respond. The length of each of the stubs (ST11 to ST14) may be the same as the fourth length (L24).

As described above, the electronic device 500 may further include stubs ST11 to ST14 at the branch points BP31, BP32, BP33, and BP34 to the extent that the reflected signal does not affect the input signal to the memory device. You can. Alternatively, the electronic device 500 may further include stubs ST11 to ST14 at the branch points BP31, BP32, BP33, and BP34 so that the reflected signal is attenuated below a certain level. Accordingly, the signal reflected from each end of the stubs (ST11 to ST14) can compensate for signal distortion caused by the reflected signal. Accordingly, signal characteristics of electronic devices that perform high-speed operations can be improved.

The electronic device 500 according to an embodiment of the present disclosure can attenuate the influence of the reflected signal by adjusting the length of each of the stubs ST11 to ST14. The length of each of the stubs ST11 to ST14 may be determined based on the length of the signal lines SL41 to SL48 of the fourth section PR4 so that the influence of the reflected signal is removed or attenuated.

Referring to FIG. 8B, the length of each of the stubs ST11 to ST14 (e.g., the sixth length L26) is the length of the signal lines SL41 to SL48 of the fourth section PR4 (e.g., , may be different from the fourth length (L24)). The sixth length L6 indicates the distance or length from one end to the other end of each of the stubs ST11 to ST14.

In one embodiment, the length from one end to the other end of the stubs ST11 to ST14 may be shorter than the length from one end to the other end of the signal lines SL41 to SL48 of the fourth section PR4. That is, the sixth length L26 may be shorter than the fourth length L24. For example, the length of the stubs ST11 to ST14 may be at least 0.1 times the length of the signal lines SL41 to SL48 of the fourth section PR4. Alternatively, the length of the stubs (ST11 to ST14) may be at least 1 mm.

Referring to FIG. 8C, the length of each of the stubs ST11 to ST14 (e.g., the sixth length L26) is the length of the signal lines SL41 to SL48 of the fourth section PR4 (e.g. , may be different from the fourth length (L24)).

In one embodiment, the length from one end to the other end of the stubs ST11 to ST14 may be longer than the length from one end to the other end of the signal lines SL41 to SL48 of the fourth section PR4. That is, the sixth length L26 may be longer than the fourth length L24. For example, the length of the stubs ST11 to ST14 may be up to 5 times the length of the signal lines SL31 to SL34 of the fourth section PR4.

As described above, the length of the stubs ST11 to ST14 can be adjusted so that the reflected signal does not affect the input signal to the memory device. Alternatively, the length of the stubs ST11 to ST14 may be adjusted based on the signal lines SL41 to SL48 of the fourth section PR4 so that the reflected signal is attenuated below a certain level. The length of the stubs ST11 to ST14 may be the same as or different from the length of the signal lines SL41 to SL48 of the fourth section PR4. The length of the stubs ST11 to ST14 may be k times the length of the signal lines SL41 to SL48 of the fourth section PR4. At this time, k may be 0.1 to 5. Alternatively, the length of the stubs (ST11 to ST14) may be 1 mm or more and may be 5 times or less than the length of the signal lines (SL41 to SL48) of the fourth section (PR4).

In one embodiment, as shown in FIGS. 8A to 8C, the length of the first stub (ST11) may be the same as the length of the second stub (ST12). However, the scope of the present disclosure is not limited thereto. The length of the first stub (ST11) and the length of the second stub (ST12) may be different from each other. Likewise, the lengths of the stubs (ST11 to ST14) may all be the same, the lengths of at least some of the stubs (ST11 to ST14) may be the same, or the lengths of all of the stubs (ST11 to ST14) may be different. .

Figure 9 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Referring to FIG. 9 , the electronic device 400 may include a memory controller 410 and first to fourth memory devices M1 to M4. The memory controller 410 may be connected to the first to fourth memory devices M1 to M4 through signal lines SL11, SL21, SL22, SL31, SL32, SL33, and SL34 of the first channel CH1, respectively. . Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch points BP11, BP21, and BP22. Since this is similar to what was previously described, detailed description thereof is omitted.

The electronic device 400 may further include stubs ST3 and ST4. For example, one end of the third stub (ST3) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path. One end of the fourth stub (ST4) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path.

The length from one end to the other end of the stubs ST3 and ST4 may be the same as the length of the signal lines SL21 and SL22 of the second section PR2. That is, the length of each of the stubs ST3 and ST4 may correspond to the length of the signal lines SL21 and SL22 of the second section PR2.

Unlike shown in FIG. 9 , the length of the stubs ST3 and ST4 may be different from the length of the signal lines SL21 and SL22 of the second section PR2. The length of the stubs ST3 and ST4 may be shorter than the length of the signal lines SL21 and SL22 of the second section PR2. Alternatively, the length of the stubs ST3 and ST4 may be longer than the length of the signal lines SL21 and SL22 of the second section PR2. For example, the length of the stubs ST3 and ST4 may be k times the length of the signal lines SL21 and SL22 of the second section PR2. At this time, k may be 0.1 to 5. Alternatively, the length of the stubs ST3 and ST4 may be 1 mm or more and may be 5 times or less the length of the signal lines SL21 and SL22 of the second section PR2.

In one embodiment, the length of the third stub (ST3) may be the same as the length of the fourth stub (ST4). However, the scope of the present disclosure is not limited thereto. The length of the third stub (ST3) and the length of the fourth stub (ST4) may be different from each other.

In one embodiment, in the electronic device 400 including stubs, the length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 are the same. can do. However, the scope of the present disclosure is not limited thereto. As shown in FIGS. 2, 3, and 5, the length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 are the same or different. can do. The ratio of the length of the signal line SL11 of the first section PR1 to the length of each of the signal lines SL21 and SL22 of the second section PR2 may be 3/7 to 7/3.

Figure 10 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Referring to FIG. 10 , the electronic device 400 may include a memory controller 410 and first to fourth memory devices M1 to M4. The memory controller 410 may be connected to the first to fourth memory devices M1 to M4 through signal lines SL11, SL21, SL22, SL31, SL32, SL33, and SL34 of the first channel CH1, respectively. . Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch points BP11, BP21, and BP22. Since this is similar to what was previously described, detailed description thereof is omitted.

Unlike shown in FIG. 7A, the electronic device 400 of FIG. 10 may further include a signal line SL0. The memory controller 410 may be connected to the first branch point BP11 through the signal line SL0 and the signal line SL11 of the first section PR1. One end of the signal line SL0 may be connected to the memory controller 410, and the other end may be connected to the first point P1. One end of the signal line SL11 of the first section PR1 may be connected to the first point P1, and the other end may be connected to the first branch point BP11. For example, the length of the signal line SL0 may be shorter than the length of the signal line SL11 of the first section PR1. The signal line SL0 may be a micro signal line.

The electronic device 400 may further include a stub ST5. For example, one end of the fifth stub (ST5) may be connected to the first point (P1), and the other end may be open without being connected to any other electrical path.

The length from one end to the other end of the stub ST5 may be the same as the length of the signal lines SL11 of the first section PR1. That is, the length of the stub ST5 may correspond to the length of the signal lines SL11 of the first section PR1.

Unlike shown in FIG. 10 , the length of the stub ST5 may be different from the length of the signal line SL11 of the first section PR1. The length of the stub ST5 may be shorter than the length of the signal line SL11 of the first section PR1. Alternatively, the length of the stub ST5 may be longer than the length of the signal line SL11 of the first section PR1. For example, the length of the stub ST5 may be k times the length of the signal line SL11 of the first section PR1. At this time, k may be 0.1 to 5. Alternatively, the length of the stub ST5 may be 1 mm or more and may be 5 times or less the length of the signal line SL11 of the first section PR1.

In one embodiment, in the electronic device 400 including a stub, the length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 are the same. can do. However, the scope of the present disclosure is not limited thereto. 2 to 5, the length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 may be the same or different. . The ratio of the length of the signal line SL11 of the first section PR1 to the length of each of the signal lines SL21 and SL22 of the second section PR2 may be 3/7 to 7/3.

7A to 7C, 9, and 10 have been described based on the electronic device of FIGS. 3A to 3C, but the scope of the present disclosure is not limited thereto. Embodiments in which the electronic device 100 of FIGS. 3A to 3C includes some or all of the stubs described with reference to FIGS. 7A to 7C, 9, and 10 should also be understood as falling within the scope of the present disclosure. Likewise, an embodiment in which the electronic device 200 of FIG. 4 includes all or part of the stubs illustrated in FIGS. 7A to 7C, 9, or 10 should also be understood as falling within the scope of the present disclosure. In this case, the length (e.g., second length L12) of the signal lines SL21 and SL22 of the second section PR2 is the same as that of the signal lines SL31, SL32, and SL33 of the third section PR3. It may be shorter than the length of SL34) (for example, the third length L13).

Figure 11 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Referring to FIG. 11 , the electronic device 500 may include a memory controller 510 and first to eighth memory devices M1 to M8. The memory controller 510 provides the first signal through the signal lines (SL11, SL21, SL22, SL31, SL32, SL33, SL34, SL41, SL42, SL43, SL44, SL45, SL46, SL47, and SL48) of the first channel (CH1). It may be connected to the eighth to eighth memory devices M1 to M8, respectively. Similar to what was described above, the signal lines of the first channel (CH1) are divided into first to fourth sections (PR1 to PR4) based on the branch points (BP11, BP21, BP22, BP31, BP32, BP33, BP34). can be distinguished. Since this is similar to what was previously described, detailed description thereof is omitted.

The electronic device 500 may further include stubs ST21 to ST24. For example, one end of the fifth stub (ST21) may be connected to the second branch point (BP21), and the other end may be open without being connected to any other electrical path. One end of the sixth stub (ST22) may be connected to the second branch point (BP21), and the other end may be open without being connected to any other electrical path. Likewise, one end of the seventh stub (ST23) may be connected to the third branch point (BP22), and the other end may be open without being connected to any other electrical path. One end of the eighth stub (ST24) is connected to the third branch point (BP22), and the other end may be open without being connected to any other electrical path.

The length from one end to the other end of the stubs (ST21 to ST24) may be the same as the length of the signal lines (SL31, SL32, SL33, and SL34) of the third section (PR3). That is, the length of each of the stubs ST21 to ST24 may correspond to the length of the signal lines SL31, SL32, SL33, and SL34 of the third section PR3.

Unlike shown in FIG. 11 , the length of the stubs ST21 to ST24 may be different from the length of the signal lines SL31 to SL34 of the third section PR3. The length of the stubs ST21 to ST24 may be shorter than the length of the signal lines SL21 and SL22 of the second section PR2. Alternatively, the length of the stubs (ST21 to ST24) may be longer than the length of the signal lines (SL31 to SL34) of the third section (PR3). For example, the length of the stubs ST21 to ST24 may be k times the length of the signal lines SL31 to SL34 of the third section PR3. At this time, k may be 0.1 to 5. Alternatively, the length of the stubs ST3 and ST4 may be 1 mm or more and may be 5 times or less the length of the signal lines SL21 and SL22 of the second section PR2.

Unlike what is shown in FIG. 9 , the electronic device 500 may not include some stubs. In one embodiment, the electronic device 500 has one end connected to the second branch point BP21, the other end connected to the fifth stub ST21 not connected to another electrical path, and one end connected to the third branch point BP22. And the other end may include an eighth stub (ST24) that is not connected to any other electrical path.

In one embodiment, the length of the fifth stub (ST21) may be the same as the length of the sixth stub (ST22). However, the scope of the present disclosure is not limited thereto. The length of the fifth stub (ST21) and the length of the sixth stub (ST22) may be different from each other. Likewise, the lengths of all of the stubs (ST21 to ST24) may be the same, the lengths of at least some of the stubs (ST21 to ST24) may be the same, or the lengths of all of the stubs (ST21 to ST24) may be different. You can.

In one embodiment, in the electronic device 500 including stubs, the length of the signal lines SL21 and SL22 of the second section PR2 is equal to the length of the signal lines SL31, SL32, and SL33 of the third section PR3. , may be shorter than the length of SL34). For example, the second length L22 may be shorter than the third length L23.

Figure 12 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Referring to FIG. 12 , the electronic device 500 may include a memory controller 510 and first to eighth memory devices M1 to M8. The memory controller 510 provides the first signal through the signal lines (SL11, SL21, SL22, SL31, SL32, SL33, SL34, SL41, SL42, SL43, SL44, SL45, SL46, SL47, and SL48) of the first channel (CH1). It may be connected to the eighth to eighth memory devices M1 to M8, respectively. Similar to what was described above, the signal lines of the first channel (CH1) are divided into first to fourth sections (PR1 to PR4) based on the branch points (BP11, BP21, BP22, BP31, BP32, BP33, BP34). can be distinguished. Since this is similar to what was previously described, detailed description thereof is omitted.

The electronic device 500 may further include stubs ST31 and ST32. For example, one end of the seventh stub (ST31) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path. One end of the eighth stub (ST32) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path.

The length from one end to the other end of the stubs ST31 and ST32 may be the same as the length of the signal lines SL21 and SL22 of the second section PR2. That is, the length of each of the stubs ST31 and ST32 may correspond to the length of the signal lines SL21 and SL22 of the second section PR2.

Unlike what is shown in FIG. 12 , the length of the stubs ST31 and ST32 may be different from the length of the signal lines SL21 and SL22 of the second section PR2. The length of the stubs ST31 and ST32 may be shorter than the length of the signal lines SL21 and SL22 of the second section PR2. Alternatively, the length of the stubs ST31 and ST32 may be longer than the length of the signal lines SL21 and SL22 of the second section PR2. For example, the length of the stubs ST31 and ST32 may be k times the length of the signal lines SL21 and SL22 of the second section PR2. At this time, k may be 0.1 to 5. Alternatively, the length of the stubs ST3 and ST4 may be 1 mm or more and may be 5 times or less the length of the signal lines SL21 and SL22 of the second section PR2.

In one embodiment, the length of the seventh stub (ST31) may be the same as the length of the eighth stub (ST32). However, the scope of the present disclosure is not limited thereto. The length of the seventh stub (ST31) and the length of the eighth stub (ST32) may be different from each other. Unlike what is shown in FIG. 9 , the electronic device 500 may not include some stubs. In one embodiment, the electronic device 500 may include a seventh stub (ST31) whose one end is connected to the first branch point (BP11) and the other end of which is not connected to any other electrical path.

In one embodiment, in the electronic device 500 including stubs, the length of the signal lines SL21 and SL22 of the second section PR2 is equal to the length of the signal lines SL31, SL32, and SL33 of the third section PR3. , may be shorter than the length of SL34). For example, the second length L22 may be shorter than the third length L23.

Referring to FIGS. 6, 8A to 8C, and 11 together, the electronic device 300 of FIG. 6 includes all or part of the stubs described in FIGS. 8A to 8C, 11, and 12. Examples should also be understood to fall within the scope of this disclosure.

13A and 13B are block diagrams showing an electronic device according to an embodiment of the present disclosure. Referring to FIGS. 13A and 13B , the electronic device 400 may include a memory controller 410 and first to fourth memory devices M1 to M4. The memory controller 410 is connected to the first to fourth memory devices M1 to M4 through signal lines SL0, SL11, SL21, SL22, SL31, SL32, SL33, and SL34 of the first channel CH1. You can. Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch points BP11, BP21, and BP22. Since this is similar to what was previously described, detailed description thereof is omitted.

The electronic device 400 of FIG. 13A may further include stubs ST1 to ST5. For example, one end of the first stub (ST1) may be connected to the second branch point (BP21), and the other end may be open without being connected to any other electrical path. One end of the second stub (ST2) may be connected to the third branch point (BP22), and the other end may be open without being connected to any other electrical path. One end of the third stub (ST3) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path. One end of the fourth stub (ST4) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path. One end of the fifth stub (ST5) is connected between the signal line (SL0) and the signal line (SL11) of the first section (PR1) (for example, the first point (P1)), and the other end is connected to another electrical path. It can be opened without being activated.

The length of each of the stubs (ST1 to ST5) may be the same as or different from the length of the corresponding signal lines. The length of each of the stubs (ST1 to ST5) may be shorter or longer than the length of the corresponding signal lines. For example, the length of each of the stubs ST1 to ST5 may be k times the length of the corresponding signal lines. At this time, k may be 0.1 to 5. Alternatively, the length of each of the stubs (ST1 to ST5) may be 1 mm or more and 5 times or less than the length of the corresponding signal lines. The signal line corresponding to each of the stubs (ST1 to ST5) may indicate signal lines connected to a point or branch point connected to one end of each of the stubs (ST1 to ST5). For example, the signal line corresponding to the first stub ST1 may be the signal lines SL31 and SL32 connected to the second branch point BP21 connected to the first stub ST1.

The electronic device of FIG. 13A may include first to fifth stubs ST1 to ST5. However, the scope of the present disclosure is not limited thereto, and unlike shown in FIG. 13A, the electronic device 400 may include at least one of the first to fifth stubs ST1 to ST5. For example, the electronic device 400 may further include only the first and fourth stubs ST1 and ST4.

The electronic device 400 of FIG. 13B may further include stubs ST1 to ST5. Unlike FIG. 13A, the stubs ST1 to ST5 in FIG. 13B may be connected other than branch points or points between signal lines. For example, each of the stubs ST1 to ST5 may be connected between one end and the other end of the corresponding signal lines. That is, each of the stubs ST1 to ST5 may be connected to the middle of the corresponding signal lines.

For example, one end of the first stub (ST1) is connected between one end and the other end of the signal line (SL31) rather than the second branch point (BP21), and the other end of the first stub (ST1) is not connected to another electrical path. It can be opened without. One end of the second stub (ST2) is connected between one end and the other end of the signal line (SL34) rather than the third branch point (BP22), and the other end of the second stub (ST2) may be open without being connected to any other electrical path. . One end of the third stub (ST3) is connected between one end and the other end of the signal line (SL21) rather than the first branch point (BP11), and the other end of the third stub (ST3) may be open without being connected to any other electrical path. . One end of the fourth stub (ST4) is connected between one end and the other end of the signal line (SL22) rather than the first branch point (BP11), and the other end of the fourth stub (ST4) may be open without being connected to any other electrical path. One end of the fifth stub (ST5) is connected between one end and the other end of the signal line (SL11) rather than the first point (P1), and the other end of the fifth stub (ST5) may be open without being connected to any other electrical path.

The length of each of the stubs (ST1 to ST5) may be the same as or different from the length of the corresponding signal lines. The length of each of the stubs (ST1 to ST5) may be shorter or longer than the length of the corresponding signal lines. For example, the length of each of the stubs ST1 to ST5 may be k times the length of the corresponding signal lines. At this time, k may be 0.1 to 5. Alternatively, the length of each of the stubs (ST1 to ST5) may be 1 mm or more and 5 times or less than the length of the corresponding signal lines. The signal line corresponding to each of the stubs (ST1 to ST5) may indicate signal lines connected to a point or branch point connected to one end of each of the stubs (ST1 to ST5). For example, the signal line corresponding to the first stub ST1 may be the signal lines SL31 and SL32 connected to the second branch point BP21 connected to the first stub ST1.

The electronic device of FIG. 13B may include first to fifth stubs ST1 to ST5. However, the scope of the present disclosure is not limited thereto, and unlike shown in FIG. 13B, the electronic device 400 may include at least one of the first to fifth stubs ST1 to ST5. For example, the electronic device 400 may further include only the first and fourth stubs ST1 and ST4.

In the electronic device 400 of FIGS. 13A and 13B, the length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 may be the same. . However, the scope of the present disclosure is not limited thereto. 2 to 5, the length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 may be the same or different. . The ratio of the length of the signal line SL11 of the first section PR1 to the length of the signal lines SL21 and SL22 of the second section PR2 may be 3/7 to 7/3.

As described above, the electronic device 400 adds stubs such as dummy lines to branch points or points and adjusts the length of the stub, the number of stubs, and the direction of the stub to remove or remove the influence of the reflected signal. It can be attenuated.

FIGS. 13A and 13B are explained based on the electronic device 100 of FIGS. 3A to 3C and the electronic device 300 of FIGS. 7A to 7C, but the scope of the present disclosure is not limited thereto. An embodiment in which the electronic device 200 of FIG. 4 includes some or all of the same or similar stubs as those described with reference to FIGS. 13A and 13B, or the electronic device 300 of FIG. 6 with FIGS. 13A and 13B. Embodiments including some or all of the same or similar stubs as described should be understood to fall within the scope of the present disclosure.

14A to 14C are block diagrams showing electronic devices according to an embodiment of the present disclosure. Referring to FIG. 14A , the electronic device 600 may include a memory controller 610 and first and second memory devices M1 and M2. The memory controller 610 may be connected to the first and second memory devices M1 and M2 through signal lines SL11, SL21, and SL22 of the first channel CH1, respectively.

The signal lines of the first channel (CH1) may be divided into first and second sections (PR1 and PR2) based on the branch point (BP11). For example, the signal line SL11 from the memory controller 610 to the first branch point BP11 may be included in the first section PR1. Signal lines SL21 and SL22 from the first branch point BP11 to the first and second memory devices M1 and M2 may be included in the second section PR2. That is, by branching the signal line through the branch point BP11, the memory controller 610 and each of the first and second memory devices M1 and M2 can be electrically connected to each other.

In one embodiment, the first section PR1 may include one signal line (ie, SL11). The second section PR2 may include two signal lines SL21 and SL22. However, the scope of the present disclosure is not limited to this, and the number of signal lines in each section may change depending on the number of memory devices connected to one channel.

The electronic device 600 according to the present disclosure may adjust the channel length of a specific section or the length of a signal line of a specific section in order to remove the influence of reflected signals between memory devices or reflected signals from branch points. For example, according to the embodiment of FIG. 14A, the length (eg, first length L1) of the signal lines SL11 of the first section PR1 and the signal lines of the second section PR2 The lengths of (SL21 and SL22) (eg, the second length (L2)) may be the same.

For example, the first length L1 indicates the length from one end to the other end of the signal line SL11 of the first section PR1. That is, the first length L1 may correspond to the distance from the memory controller 110 to the first branch point BP11. The second length L2 indicates the length from one end to the other end of the signal lines SL21 and SL22 of the second section PR2. That is, the second length L2 may correspond to the distance from the first branch point BP11 to the first memory device M1 or the distance from the first branch point BP11 to the second memory device M2.

As described above, the ratio of the length of the signal line SL11 of the first section PR1 to the length of the signal lines SL21 and SL22 of the second section PR2 may be 1:1. Accordingly, the reflected signal from the second memory device M2 may be attenuated to the extent that it does not affect the input signal to the first memory device M1.

Referring to FIG. 14B, unlike shown in FIG. 14A, the length of the signal lines SL11 of the first section PR1 (for example, the first length L1) is longer than that of the signal of the second section PR2. The length of the lines SL21 and SL22 (eg, the second length L2) may be long.

In other words, the length of the signal lines SL11 in FIG. 14B may be shorter than the length of the signal lines SL11 in FIG. 14A. Alternatively, the length of the signal lines SL21 and SL22 in FIG. 14B may be longer than the length of the signal lines SL21 and SL22 in FIG. 14A.

In one embodiment, the ratio of the first length (L1) to the second length (L2) may be 3/7. That is, the length L2 of the signal lines SL21 and SL22 of the second section PR2 may be l times that of the signal line SL11 of the first section PR1. However, l may be greater than 1 and less than or equal to 2.33.

Referring to FIG. 14C, unlike shown in FIG. 14A, the length of the signal lines SL11 of the first section PR1 (for example, the first length L1) is longer than that of the signal of the second section PR2. The length of the lines SL21 and SL22 (eg, the second length L2) may be short.

In other words, the length of the signal line SL11 in FIG. 14C may be longer than the length of the signal line SL11 in FIG. 14A. Alternatively, the length of the signal lines SL21 and SL22 in FIG. 14C may be shorter than the length of the signal lines SL21 and SL22 in FIG. 14A.

In one embodiment, the ratio of the first length L1 and the second length L2 may be 7:3. That is, the length L2 of the signal lines SL21 and Sl22 of the second section PR2 may be m times the length L1 of the signal line SL11 of the first section PR1. However, m may be 0.42 or more and 1 or less.

As shown in FIGS. 14A to 14C, the length of the first signal line SL21 of the second section PR2 and the length of the second signal line SL22 of the second section PR2 may be the same. However, the scope of the present disclosure is not limited thereto. Although not shown, the length of the first signal line SL21 in the second section PR2 may be different from the length of the second signal line SL22 in the second section PR2.

As described above, the first length L1 and the second length L2 may have a predetermined ratio. For example, the ratio of the first length (L1) to the second length (L2) may be about 3/7 to 7/3. Alternatively, the second length (L2) may be k times the first length (L1). However, k may be 0.42 or more and 2.33 or less. Accordingly, the influence of reflected signals can be reduced.

15A to 15D are block diagrams showing electronic devices according to embodiments of the present disclosure. Hereinafter, for convenience of explanation, descriptions that overlap with the previously described components will be omitted. Referring to FIG. 15A , the electronic device 700 may include a memory controller 710 and first and second memory devices M1 and M2. The memory controller 710 may be connected to the first and second memory devices M1 and M2 through signal lines SL0, SL11, SL21, SL22, SL31, and SL32 of the first channel CH1, respectively. One end of the signal line SL0 may be connected to the memory controller 710, and the other end may be connected to the first point P1. The signal lines of the first channel (CH1) may be divided into first to third sections (PR1 to PR3) based on the branch point (BP11) and points (P1 to P3).

For example, the signal line SL11 from the first point P1 to the first branch point BP11 may be included in the first section PR1. The signal line SL21 from the first branch point BP11 to the second point P2 and the signal line SL22 from the first branch point BP11 to the third point P3 are included in the second section PR2. You can. The signal line SL31 from the second point P2 to the first memory device M1 and the signal line SL32 from the third point P3 to the second memory device M2 are connected to the third section PR3. may be included in

For example, the signal line SL0 may be shorter than the signal line SL11 of the first section PR1. Each of the signal lines SL31 and SL32 of the third section PR3 may be shorter than the signal line SL11 of the second section PR2. The signal lines SL0, SL31, and SL32 may be micro signal lines.

In one embodiment, the electronic device 700 may further include stubs ST1 and ST2. One end of each of the stubs ST1 and ST2 may be connected to a corresponding point, and the other end may be open without being connected to another electrical path. For example, one end of the first stub (ST1) may be connected to the second point (P2), and the other end may be open without being connected to any other electrical path. One end of the second stub (ST2) may be connected to the third point (P3), and the other end may be open without being connected to any other electrical path.

In one embodiment, the length from one end to the other end of the stubs ST1 and ST2 may be the same as the length of the signal lines SL31 and SL32 of the third section PR3. That is, the length of each of the stubs ST1 and ST2 may correspond to the length of the signal lines SL31 and SL32 of the third section PR3. The length of each of the stubs ST1 and ST2 may be the fourth length L4. The fourth length L4 indicates the distance or length from one end to the other end of the signal lines SL31 and SL32 of the third section PR3. That is, the fourth length L4 indicates the distance from the second or third point P2 and P3 to the memory devices M1 and M2.

In one embodiment, the length of the stubs ST1 and ST2 may be different from the length of the signal lines SL31 and SL32 of the third section PR3. For example, the length of the stubs ST1 and ST2 may be shorter than the length of the signal lines SL31 and SL32 of the third section PR3. Alternatively, the length of the stubs ST1 and ST2 may be longer than the length of the signal lines SL31 and SL32 of the third section PR3. The length of the stubs ST1 and ST2 may be k times the fourth length L4. At this time, k may be 0.1 to 5. Alternatively, the length of the stubs ST1 and ST2 may be 1 mm or more and 5 times or less the fourth length L4.

In one embodiment, as shown in FIG. 15A, the length of the first stub (ST1) may be the same as the length of the second stub (ST2). However, the scope of the present disclosure is not limited thereto. The length of the first stub (ST1) and the length of the second stub (ST2) may be different from each other.

As described above, the electronic device 700 may further include stubs ST1 and ST2 at points P2 and P3. Accordingly, the signal reflected from the ends of each of the stubs ST1 and ST2 can compensate for signal distortion caused by the reflected signal. Accordingly, signal characteristics of electronic devices that perform high-speed operations can be improved.

Referring to FIG. 15B , the electronic device 700 may include a memory controller 710 and first and second memory devices M1 and M2. The memory controller 710 may be connected to the first and second memory devices M1 and M2 through signal lines SL0, SL11, SL21, SL22, SL31, and SL32 of the first channel CH1, respectively. Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch point BP11 and the points P1 to P3. Since this is similar to what was previously described, detailed description thereof is omitted.

The electronic device 700 may further include stubs ST3 and ST4. For example, one end of the third stub (ST3) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path. One end of the fourth stub (ST4) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path.

The length from one end to the other end of the stubs ST3 and ST4 may be the same as the length of the signal lines SL21 and SL22 of the second section PR2. That is, the length of each of the stubs ST3 and ST4 may correspond to the length of the signal lines SL21 and SL22 of the second section PR2.

Unlike shown in FIG. 15B, the length of the stubs ST3 and ST4 may be different from the length of the signal lines SL21 and SL22 of the second section PR2. The length of the stubs ST3 and ST4 may be shorter than the length of the signal lines SL21 and SL22 of the second section PR2. Alternatively, the length of the stubs ST3 and ST4 may be longer than the length of the signal lines SL21 and SL22 of the second section PR2. For example, the length of the stubs ST3 and ST4 may be k times the length of the signal lines SL21 and SL22 of the second section PR2. At this time, k may be 0.1 to 5. Alternatively, the length of the stubs ST3 and ST4 may be 1 mm or more and may be 5 times or less the length of the signal lines SL21 and SL22 of the second section PR2.

In one embodiment, the length of the third stub (ST3) may be the same as the length of the fourth stub (ST4). However, the scope of the present disclosure is not limited thereto. The length of the third stub (ST3) and the length of the fourth stub (ST4) may be different from each other.

Referring to FIG. 15C , the electronic device 700 may include a memory controller 710 and first and second memory devices M1 and M2. The memory controller 710 may be connected to the first and second memory devices M1 and M2 through signal lines SL0, SL11, SL21, SL22, SL31, and SL32 of the first channel CH1, respectively. Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch point BP11 and the points P1 to P3. Since this is similar to what was previously described, detailed description thereof is omitted.

The electronic device 700 may further include a stub ST5. For example, one end of the fifth stub (ST3) may be connected to the first point (P1), and the other end may be open without being connected to any other electrical path.

In one embodiment, the length from one end to the other end of the stub ST5 may be the same as the length of the signal line SL11 of the first section PR1. That is, the length of the stub ST5 may correspond to the length of the signal line SL11 of the first section PR1.

Unlike shown in FIG. 15C, the length of the stub ST5 may be different from the length of the signal line SL11 of the first section PR1. The length of the stub ST5 may be shorter than the length of the signal line SL11 of the first section PR1. Alternatively, the length of the stub ST5 may be longer than the length of the signal line SL11 of the first section PR1. For example, the length of the stub ST5 may be k times the length of the signal line SL11 of the first section PR1. At this time, k may be 0.1 to 5. Alternatively, the length of the stub ST5 may be 1 mm or more and may be 5 times or less the length of the signal line SL11 of the first section PR1.

Referring to FIG. 15D , the electronic device 700 may include a memory controller 710 and first and second memory devices M1 and M2. The memory controller 710 may be connected to the first and second memory devices M1 and M2 through signal lines SL0, SL11, SL21, SL22, SL31, and SL32 of the first channel CH1, respectively. Similar to what was described above, the signal lines of the first channel CH1 may be divided into first to third sections PR1 to PR3 based on the branch point BP11 and the points P1 to P3. Since this is similar to what was previously described, detailed description thereof is omitted.

The electronic device 700 may further include stubs ST1 to ST5. For example, one end of the first stub (ST1) may be connected to the second point (P2), and the other end may be open without being connected to any other electrical path. One end of the second stub (ST2) may be connected to the third point (P3), and the other end may be open without being connected to any other electrical path. One end of the third stub (ST3) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path. One end of the fourth stub (ST4) may be connected to the first branch point (BP11), and the other end may be open without being connected to any other electrical path. One end of the fifth stub (ST5) may be connected to the first point (P1), and the other end may be open without being connected to any other electrical path.

The length of each of the stubs (ST1 to ST5) may be the same as or different from the length of the corresponding signal lines. The length of each of the stubs (ST1 to ST5) may be shorter or longer than the length of the corresponding signal lines. For example, the length of each of the stubs ST1 to ST5 may be k times the length of the corresponding signal lines. At this time, k may be 0.1 to 5. Alternatively, the length of each of the stubs (ST1 to ST5) may be 1 mm or more and 5 times or less than the length of the corresponding signal lines.

The signal line corresponding to each of the stubs (ST1 to ST5) may indicate signal lines connected to a point or branch point connected to one end of each of the stubs (ST1 to ST5). For example, the signal line corresponding to the first stub (ST1) may be the signal lines (SL31) connected to the second point (P2) connected to the first stub (ST1).

In one embodiment, unlike shown in FIG. 15D , the stubs ST1 to ST5 may be connected other than branch points or points between signal lines. For example, each of the stubs ST1 to ST5 may be connected between one end and the other end of the corresponding signal lines. That is, each of the stubs ST1 to ST5 may be connected to the middle of the corresponding signal lines.

For example, one end of the first stub (ST1) is connected between one end and the other end of the signal line (SL31) rather than the second point (P2), and the other end of the first stub (ST1) is not connected to any other electrical path. It can be opened without. One end of the second stub (ST2) is connected between one end and the other end of the signal line (SL32) rather than the third point (P3), and the other end of the second stub (ST2) may be open without being connected to any other electrical path. . One end of the third stub (ST3) is connected between one end and the other end of the signal line (SL21) rather than the first branch point (BP11), and the other end of the third stub (ST3) may be open without being connected to any other electrical path. . One end of the fourth stub (ST4) is connected between one end and the other end of the signal line (SL22) rather than the first branch point (BP11), and the other end of the fourth stub (ST4) may be open without being connected to any other electrical path. One end of the fifth stub (ST5) is connected between one end and the other end of the signal line (SL11) rather than the first point (P1), and the other end of the fifth stub (ST5) may be open without being connected to any other electrical path.

The electronic device of FIG. 15D may include first to fifth stubs ST1 to ST5. However, the scope of the present disclosure is not limited thereto, and, unlike shown in FIG. 15D, the electronic device 700 may include at least one of the first to fifth stubs ST1 to ST5. For example, the electronic device 400 may further include only the first and fourth stubs ST1 and ST4.

15A to 15D, in the electronic device 700 including stubs, the length of the signal line SL11 in the first section PR1 and the signal lines SL21 in the second section PR2 The length of SL22) may be the same. However, the scope of the present disclosure is not limited thereto. 3A to 5, the length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 may be the same or different. . The length of the signal line SL11 of the first section PR1 and the length of the signal lines SL21 and SL22 of the second section PR2 may have a predetermined ratio. For example, the predetermined ratio may be 3/7 to 7/3.

FIG. 16 is a block diagram showing the channel of FIG. 14A in more detail. Referring to FIG. 14A , the electronic device 600 may include a memory controller 610 and first and second memory devices M1 and M2. For convenience of explanation and brevity of drawings, detailed descriptions or reference numbers for components that are the same as or similar to the components described above are omitted.

In one embodiment, the signal line SL11 of the first section PR1 may include a first sub-signal line SL11a and a second sub-signal line SL11b. The signal line SL21 of the second section PR2 may include a third sub-signal line SL21a and a fourth sub-signal line SL21b.

Signals corresponding to bidirectional signals may be transmitted through the first sub-signal line SL11a and the third sub-signal line SL21a. Signals corresponding to bidirectional signals may include a data signal (DQ) and a data strobe signal (DQS). For example, the memory controller 610 may transmit the data signal DQ corresponding to write data to the first memory device M1 through the first sub-signal line SL11a and the third sub-signal line SL21a. there is. The first memory device M1 may transmit the data signal DQ corresponding to read data to the memory controller 610 through the third sub-signal line SL21a and the first sub-signal line SL11a.

Control signals (CTRL) corresponding to unidirectional signals may be transmitted through the second sub-signal line (SL11b) and the fourth sub-signal line (SL21b). The control signals CTRL may include a command latch enable signal (CLE), an address latch enable signal (ALE), a read enable signal (RE), or a write enable signal (WE). For example, the memory controller 610 may transmit the write enable signal WE to the first memory device M1 through the second sub-signal line SL11b and the fourth sub-signal line SL21b.

As described above, each of the signal lines included in the first channel (CH1) of the electronic device described with reference to FIGS. 1 to 15D has a sub-signal line transmitting a bidirectional signal and a sub-signal line transmitting a unidirectional signal. It can be included.

Although the above-described embodiments have been described based on a write operation of an electronic device (i.e., an operation of transmitting a signal from a memory controller to one of a plurality of memory devices), the scope of the present disclosure is not limited thereto. For example, during a read operation of an electronic device, one memory device among a plurality of memory devices may transmit an input signal (eg, read data) to a memory controller. In this case, the signal length of a specific section may be extended so that reflected signals from other memory devices among the plurality of memory devices are attenuated or do not flow into the memory controller or the first memory device.

17A to 17G are diagrams exemplarily showing a printed circuit board according to an embodiment of the present disclosure. FIG. 17A is a plan view showing the top surface of the printed circuit board (PCB_1) according to an embodiment of the present disclosure, and FIG. 17B is a cross-sectional view taken along line A-A' of the printed circuit board (PCB_1) of FIG. 17A.

An electronic device may include a printed circuit board (PCB), a memory controller, and a plurality of memory devices. Since the memory controller and the plurality of memory devices have been described above, detailed description thereof will be omitted. According to the embodiments of the present disclosure described with reference to FIGS. 1 to 16, in order to attenuate the influence of reflected signals, signal lines included in a printed circuit board (PCB) may have a certain ratio or stubs may be added. there is. With reference to the drawings below, signal lines formed in the metal layer are described in detail.

In order to easily explain the technical idea of the present disclosure, a signal line (SL) electrically connected to some of the plurality of sockets (SCK11 to SCK4n) is shown. However, the scope of the present disclosure is not limited thereto, and other sockets may also be electrically connected to other signal lines. In one embodiment, the signal line may be included in the metal layer ML of the printed circuit board PCB_1. The metal layer (ML) may be implemented as a multi-layer including multiple layers. Exemplarily, with reference to FIGS. 17A and 17B , a printed circuit board applicable to the electronic device 100 of FIG. 3A is described.

Referring to FIGS. 17A and 17B , the printed circuit board (PCB_1) may include a controller socket (SCK_CT) and a plurality of sockets (SCK11 to SCK4n). The controller socket (SCK_CT) of FIGS. 17A and 17B may be located on one side of the printed circuit board (PCB_1). For example, the controller socket (SCK_CT) may be placed on one side of the printed circuit board (PCB_1), and a plurality of sockets (SCK11 to SCK4n) may be placed on the remaining area. The controller socket (SCK_CT) may be an area, configuration, or device on which a memory controller is mounted. The plurality of sockets (SCK11 to SCK4n) may be an area, configuration, or device in which a plurality of memory devices are mounted. Although not clearly shown in the drawing, additional sockets may be formed on the lower surface of the printed circuit board (PCB_1). A plurality of memory devices may be mounted on additional sockets formed on the lower surface of the printed circuit board (PCB_1).

Each of the memory controller and the plurality of memory devices is mounted on a corresponding socket and can communicate with each other through a signal line (SL) included in a printed circuit board (PCB). A printed circuit board (PCB) may include signal lines (SL). The signal line SL may be a signal transmission path between the memory controller and memory devices. That is, the signal line SL may be configured to electrically connect a plurality of sockets SCK11 to SCK4n and the controller socket SCK_CT. Exemplarily, the signal line SL may be formed on a metal layer or wiring layer of the first printed circuit board PCB_1.

The controller socket (SCK_CT) may be electrically connected to the first branch point (BP11). The first branch point BP11 may be spaced apart from the controller socket SCK_CT by a predetermined distance. The first branch point BP11 may be electrically connected to the second and third branch points BP21 and BP22, respectively.

The second branch point BP21 may be electrically connected to the sockets SCK11 and SCK51, respectively, and the third branch point BP22 may be electrically connected to the sockets SCK21 and SCK61, respectively. At this time, as shown in FIG. 17B, the length of the first section PR1 may be the same as the length of the second section PR2. Alternatively, the ratio of the length of the first section PR1 to the length of the second section PR2 may be 3/7 to 7/3.

For example, the sockets (SCK11, SCK21, SCK51, and SCK61) may be electrically connected to the controller socket (SCK_CT) through the same channel (i.e., one signal line). At this time, the sockets SCK11 and SCK51 may be arranged to face each other based on the printed circuit board (PCB), and the sockets SCK21 and SCK61 may be arranged to face each other based on the printed circuit board (PCB). You can. In other words, the sockets SCK11 and SCK21 may be placed on the upper surface (PCB_TOP) of the printed circuit board, and the sockets SCK51 and SCK61 may be placed on the lower surface (PCB_BOTTOM) of the printed circuit board.

At this time, the sockets (SCK11, SCK21) located on the top surface (PCB_TOP) may be sockets that are not adjacent to each other. For example, other sockets (e.g., SCK12 to SCK1n) may exist between sockets (SCK11, SCK21) connected to the same channel (i.e., one signal line), and other sockets (e.g., SCK12~SCK1n) can be electrically connected to the controller socket (SCK_CT) through a separate signal line. Sockets (SCK51, SCK61) located on the bottom surface (PCB_BOTTOM) may be sockets that are not adjacent to each other. That is, other sockets (for example, SCK52 to SCK5n) may exist between the sockets (SCK51 and SCK61) connected by one signal line, and other sockets (for example, SCK52 to SCK5n) may exist. It can be electrically connected to the controller socket (SCK_CT) through a separate signal line.

In one embodiment, in a conventional electronic device, sockets adjacent to each other are electrically connected to a controller socket through one signal line. In this case, because branch points are created in the surrounding areas of adjacent sockets, the length of the first section becomes relatively short. On the other hand, according to an embodiment of the present disclosure, sockets (e.g., SCK11, SCK21) that are not adjacent to each other are connected to the controller socket (SCK_CT) through one signal line, so that, as in the embodiment of the present disclosure, The length of section 2 (PR2) can be relatively long. Accordingly, the influence of reflected signals between memory devices mounted in each socket can be reduced.

The printed circuit board (PCB) shown in FIGS. 17A and 17B is illustrative, and the scope of the present disclosure is not limited thereto. For example, in a printed circuit board (PCB), the positions of each of the branch points BP11, BP21, and BP22 may be changed in various ways without departing from the technical spirit of the present disclosure.

For example, the first branch point BP11 is located in the area of the socket SCK11, the area of the socket SCK21, or another area, and the length of the second section PR2 and the length of the first section PR1 are The signal lines of the first and second sections PR1 and PR2 may be formed to be identical. Alternatively, the signal lines of the first and second sections PR1 and PR2 may be formed so that the length of the first section PR1 and the length of the second section PR2 have a predetermined ratio.

In one embodiment, the total length of signal lines connected from the controller socket (SCK_CT) to each of the plurality of sockets may vary from about 50 mm to 400 mm. For example, the length of the signal line connecting the controller socket (SCK_CT) and the socket (SCK11) may be 50 mm, and the length of the signal line connecting the controller socket (SCK_CT) and the socket (SCK2n) may be 400 mm.

In one embodiment, the length of the signal lines in the third section PR3 may be longer than the length of the signal lines in the second section PR2. That is, the length of the signal lines in the second section PR2 may be shorter than the length of the signal lines in the third section PR3. For example, when the printed circuit board (PCB) shown in FIGS. 17A and 17B implements the electronic device 200 of FIG. 4, the length of the signal lines in the second section PR2 is the length of the third section PR3. It may be shorter than the length of the signal lines.

Hereinafter, for convenience of explanation, it is assumed that the length of the signal lines of the third section PR3 is relatively smaller than the length of the signal lines of the first and second sections PR1 and PR2. That is, it is assumed that the length of the third section PR3 is negligibly small compared to the lengths of the signal lines of the first and second sections PR1 and PR2.

For example, assume that the length of the signal line connecting the controller socket (SCK_CT) to the socket (SCK11) is 50 mm. The length of the signal line SL11 of the first section PR1 may be the same as the length of each of the signal lines SL21 and SL22 of the second section PR2. That is, the length of the signal line SL11 of the first section PR1 may be 25 mm, and the length of the signal lines SL21 and SL22 of the second section PR2 may be 25 mm.

Alternatively, the length of the signal line SL11 of the first section PR1 and the length of each of the signal lines SL21 and SL22 of the second section PR2 may have a constant ratio. The ratio of the length of the signal line SL11 of the first section PR1 to the length of each of the signal lines SL21 and SL22 of the second section may be 3/7 to 7/3. For example, if the length of the signal line SL11 of the first section PR1 is 15 mm, the length of each of the signal lines SL21 and SL22 of the second section PR2 may be 35 mm. If the length of the signal line SL11 of the first section PR1 is 35 mm, the length of each of the signal lines SL21 and SL22 of the second section PR2 may be 15 mm.

For example, assume that the length of the signal line connecting the controller socket (SCK_CT) to the socket (SCK2n) is 400mm. The length of the signal line SL11 of the first section PR1 may be the same as the length of each of the signal lines SL21 and SL22 of the second section PR2. That is, the length of the signal line SL11 in the first section PR1 may be 100 mm, and the length of the signal lines SL21 and SL22 in the second section PR2 may be 100 mm.

For example, if the length of the signal line SL11 of the first section PR1 is 60 mm, the length of each of the signal lines SL21 and SL22 of the second section PR2 may be 140 mm. If the length of the signal line SL11 of the first section PR1 is 140 mm, the length of each of the signal lines SL21 and SL22 of the second section PR2 may be 60 mm.

FIG. 17C is a plan view showing the top surface of the printed circuit board (PCB_2) according to an embodiment of the present disclosure, and FIG. 17D is a B-B' cross-sectional view of the printed circuit board (PCB_2) of FIG. 17C. The electronic device may include a printed circuit board (PCB_2), a memory controller, and first to fourth memory devices M1 to M4. Since the memory controller and the first to fourth memory devices M1 to M4 have been described above, detailed description thereof will be omitted. For the sake of concise explanation, descriptions of the components described above are omitted.

Referring to FIGS. 17C and 17D, the printed circuit board (PCB_2) may include a controller socket (SCK_CT) and a plurality of sockets (SCK1 to SCK4). The controller socket (SCK_CT) may be an area, configuration, or device on which a memory controller is mounted. The first to fourth sockets SCK1 to SCK4 may be areas, configurations, or devices on which the first to fourth memory devices M1 to M4 are mounted. Although not clearly shown in the drawing, additional sockets SCK2 and SCK4 may be formed on the lower surface of the printed circuit board (PCB). The second and fourth memory devices M2 and M4 may be mounted in additional sockets formed on the lower surface of the printed circuit board PCB_2.

For example, the controller socket SCK_CT and the first and third sockets SCK1 and SCK3 may be formed on the top surface (PCB_TOP) of the printed circuit board PCB_2, and the second and fourth sockets (SCK2, SCK4) may be formed on the bottom surface (PCB_BOTTOM) of the printed circuit board (PCB_2). In one embodiment, the second socket SCK2 may be arranged to face the first socket SCK1 with respect to the printed circuit board PCB_2, and the fourth socket SCK4 may be arranged with respect to the printed circuit board PCB_2. It can be arranged to face the third socket (SCK3).

The controller socket (SCK_CT) may be located in an area on one side of the printed circuit board (PCB_2). For example, the controller socket SCK_CT may be placed on one side of the printed circuit board PCB_2, and the first and third sockets SCK1 and SCK3 may be placed on the remaining area. The first socket SCK1 may be disposed at a position spaced apart from the controller socket SCK_CT by a predetermined distance in the first direction D1. The second socket SCK2 may be disposed at a position spaced apart from the first socket SCK1 by a predetermined distance in the second direction D2 perpendicular to the first direction D1.

For example, the signal line SL may branch at a plurality of branch points BP11, BP21, and BP22 from the controller socket SCK_CT, similar to what was described above, and thus, a plurality of sockets ( It can be configured to electrically connect between SCK1~SCK4) and the controller socket (SCK_CT). For example, the signal line SL11 from the controller socket SCK_CT to the branch point BP11 may be included in the first section PR1. The signal lines SL21 and SL22 from the branch point BP11 to each of the branch points BP21 and BP22 may be included in the second section PR2. Signal lines SL31 to SL34 from each of the branch points BP21 and BP22 to each of the first to fourth sockets SCK1 to SCK4 may be included in the third section PR3.

In one embodiment, the branch points BP11, BP21, and BP22 may be located in an area related to the controller socket SCK_CT and the first to fourth sockets SCK1 to SCK4. For example, the branch point BP11 may be located between the controller socket SCK_CT and the first and third sockets SCK1 and SCK3. The branch point BP21 may be located between the first and second sockets SCK1 and SCK2, and may be connected to the first and second sockets SCK1 and SCK2 through a via contact. The branch point BP22 may be located between the third and fourth sockets SCK3 and SCK4 and may be connected to the third and fourth sockets SCK3 and SCK4 through a via contact.

Alternatively, the branch point BP11 may be formed at a location spaced apart from the controller socket SCK_CT along the third direction D3 by the first length L1. For example, the third direction D3 may indicate a direction between the first direction D1 and the second direction D2. The angle between the first direction D1 and the third direction D3 may be an acute angle. The branch point BP22 may be formed at a location spaced apart from the branch point BP11 in the third direction D3 by the second length L2. The branch point BP21 may be formed at a location spaced apart from the branch point BP11 in the fourth direction D4 by the second length L2. For example, the fourth direction D4 may indicate a direction between the first direction D1 and the opposite direction of the second direction D2. The angle between the first direction D1 and the fourth direction D4 may be an acute angle. At this time, the first length (L1) and the second length (L2) may be the same. However, the scope of the present disclosure is not limited thereto, and the ratio of the first length L1 to the second length L2 may be 3/7 to 7/3. An optimal ratio of the first length L1 and the second length L2 may be determined to cancel out noise in the reflected signal.

The branch points BP21 and BP22 may be formed at positions spaced apart from the sockets SCK1 to SCK4 by a predetermined distance along the vertical direction. By way of example, the vertical direction may refer to a direction perpendicular to the upper or lower surface of the printed circuit board (PCB_2). In other words, the vertical direction may be a direction that passes through the top or bottom surface of the printed circuit board (PCB). As described above, the embodiments of the present disclosure described with reference to FIGS. 1 to 16 can be implemented by forming branch points in the printed circuit board (PCB_2).

FIG. 17E is a plan view showing the top surface of the printed circuit board (PCB_3) according to an embodiment of the present disclosure, and FIGS. 17F and 17G are cross-sectional views taken along line C-C' of the printed circuit board (PCB_3) of FIG. 17E. The electronic device may include a printed circuit board (PCB_3), a memory controller, and first to fourth memory devices (M1 to M4). Referring to FIGS. 17E to 17G , the printed circuit board (PCB_3) may include a controller socket (SCK_CT) and first to fourth sockets (SCK1 to SCK4). For the sake of concise explanation, descriptions of the components described above are omitted.

The controller socket (SCK_CT) may be located in an area on one side of the printed circuit board (PCB_3). For example, the controller socket SCK_CT may be placed on one side of the printed circuit board PCB_3, and the first and third sockets SCK1 and SCK3 may be placed on the remaining area. Unlike FIG. 17C, the controller socket SCK_CT and the first and third sockets SCK1 and SCK3 in FIG. 17E may be arranged along the first direction. The first socket (SCK1) may be disposed at a position spaced apart from the controller socket (SCK_CT) by a predetermined distance in the first direction. The third socket SCK3 may be disposed at a position spaced apart from the first socket SCK1 by a predetermined distance in the first direction.

In one embodiment, the branch points BP11, BP21, and BP22 may be located in an area related to the controller socket SCK_CT and the first to fourth sockets SCK1 to SCK4. For example, the branch point BP11 may be located between the controller socket SCK_CT and the first socket SCK1. The branch point BP21 may be located between the first and second sockets SCK1 and SCK2, and may be connected to the first and second sockets SCK1 and SCK2 through a via contact. The branch point BP22 may be located between the third and fourth sockets SCK3 and SCK4 and may be connected to the third and fourth sockets SCK3 and SCK4 through a via contact.

Alternatively, the branch point BP11 may be formed at a location spaced apart from the controller socket SCK_CT in the first direction D1 by the first length L1. The branch point BP22 may be formed at a location spaced apart from the branch point BP11 in the first direction D1 by the second length L2. The branch point BP21 may be formed at a location spaced apart from the branch point BP11 in the first direction by the sixth length L6. For example, the sixth length L6 may be shorter than the second length L2. The first length L1 may be equal to the second length L2. However, the scope of the present disclosure is not limited thereto, and the ratio of the first length L1 to the second length L2 may be 3/7 to 7/3.

In one embodiment, the signal line SL21 connecting the branch point BP11 and the branch point BP21 may not be connected in a straight line or in the shortest distance. The signal line SL21 may be formed in a zigzag pattern, as shown in FIG. 17E. For example, in order to provide a longer electrical connection path between the branch point BP11 and the branch point BP21, it may include parts extending in the first direction D1 and parts extending in the second direction D2. You can. The ends of the parts extending in the first direction D1 and the ends of the parts extending in the second direction D2 may be connected to each other. Accordingly, the length of the signal line SL21 connecting the branch points BP11 and BP21 may be equal to the second length L2. That is, the signal line SL21 may have a second length L2 that is longer than the sixth length L6, which is the straight line distance between the branch points BP11 and BP21 along the first direction.

The branch points BP21 and BP22 may be formed at positions spaced apart from the sockets SCK1 to SCK4 by a predetermined distance along the vertical direction. By way of example, the vertical direction may refer to a direction perpendicular to the upper or lower surface of the printed circuit board (PCB_3). In other words, the vertical direction may be a direction penetrating the upper or lower surface of the printed circuit board (PCB_3). As described above, the embodiments of the present disclosure described with reference to FIGS. 1 to 16 can be implemented by forming branch points in the printed circuit board (PCB_3).

Referring to FIG. 17g, the printed circuit board (PCB_3) may further include stubs (ST1 and ST2). In one embodiment, one end of the first stub (ST1) may be connected to the branch point (BP21), and the other end of the first stub (ST1) may be open without being connected to another electrical path. The first stub ST1 may be formed along the horizontal direction from the branch point BP21. One end of the second stub (ST2) may be connected to the branch point (BP22), and the other end of the second stub (ST2) may be open without being connected to any other electrical path. The second stub ST2 may be formed along the horizontal direction from the branch point BP22.

For example, the horizontal direction may be parallel to the top or bottom surface of the printed circuit board (PCB_3). For example, the horizontal direction may refer to the horizontal axis direction, the vertical axis direction, or a combination of the horizontal and vertical axes of the plane formed by the upper surface of the printed circuit board (PCB_3). However, the scope of the present disclosure is not limited thereto, and the directions of the first and second stubs ST1 and ST2 may vary.

Although not shown, the stub may be further connected to the branch point BP11 or a point between the controller socket SCK_CT and the branch point BP11. As described above, the embodiments of the present disclosure described with reference to FIGS. 1 to 16 can be implemented by adding a stub to the printed circuit board (PCB_3).

17A to 17G are described based on the electronic device of FIG. 3A, but the scope of the present disclosure is not limited thereto. An embodiment in which the electronic device 200 of FIG. 4 is implemented on a printed circuit board identical or similar to that described with reference to FIGS. 17A to 17G should also be understood as falling within the scope of the present disclosure. In this case, the length of each of the signal lines in the second section PR2 may be shorter than the length of the signal lines in the third section PR3. Likewise, embodiments in which the electronic devices of FIGS. 6, 8A to 8C, 11, or 12 are implemented on a printed circuit board identical or similar to those described with reference to FIGS. 17A to 17G are also within the scope of the present disclosure. must be understood as belonging. In this case, the length of the signal lines in the second section PR2 may be shorter than the length of the signal lines in the third section PR3.

18A to 18B are timing diagrams for explaining the effect of removing a reflected signal according to an embodiment of the present disclosure. In the timing diagrams of FIGS. 18A and 18B, the two horizontal axes indicate time, and the vertical axis indicates signal size. Referring to FIGS. 18A and 18B, FIG. 18A is a signal waveform in the electronic device of FIG. 2, and FIG. 18B is a signal waveform in the electronic device explained through FIGS. 3A to 17G.

As shown in FIG. 18A, in the case of the electronic device of FIG. 2, the signal margin may be the first time (T1) due to the reflected signal. The input signal is distorted due to the reflected signal, and as a result, the change in signal size may not be sufficient. In this case, signals input to the memory device may not be read normally.

On the other hand, the margin of the signal in the electronic device according to FIGS. 3A to 17G of the present disclosure may be a second time (T2) longer than the first time (T1). That is, as the first section PR1 and the second section PR2 have a predetermined ratio or stubs are added, the influence of reflected signals from other memory devices or branch points may be attenuated, resulting in The signal margin may increase or the signal size change may be sufficient. That is, the reliability of the input signal in the memory device can be improved.

FIG. 18C is a graph illustrating the effect of removing a reflected signal according to an embodiment of the present disclosure. The horizontal axis of the graph of FIG. 18C represents the length (e.g., first length L1) of the signal line SL11 of the first section PR1 and the signal lines SL21 and SL22 of the second section PR2, respectively. It indicates the ratio of the length (for example, the second length (L2)), and the vertical axis indicates the margin of the signal.

In one embodiment, when the ratio of the first length (L1) to the second length (L2) (e.g., L1/L2) is 3/7, the margin of the signal is the second value (v2), and the first length (L1) If the ratio of (L1) to the second length (L2) is 1, the margin of the signal is the first value (v1), and if the ratio of the first length (L1) to the second length (L2) is 7/3 , the margin of the signal may be the third value (v3). The first value (v1) may be greater than the second value (v2), and the second value (v2) may be greater than the third value (v3). That is, when the first length (L1) and the second length (L2) are the same, the signal margin may be the largest.

In the electronic devices of FIGS. 2 and 3A, the signal margin according to the total length including the first length L1 and the second length L2 may be as shown in Table 1. Referring to Table 1, the first margin (Margin 1) indicates the signal margin of the electronic device of FIG. 2, and the second margin (Margin 2) indicates the signal margin of the electronic device of FIG. 3A.

It is assumed that the length of the signal lines in the third section PR3 is negligibly small compared to the lengths of the signal lines in the first and second sections PR1 and PR2. The total length of signal lines connecting each of the memory devices from the memory controller is called the total length (TL). For example, the total length TL means the length of the signal line in the first section PR1 and the length of each signal line in the second section PL2.

For example, when the total length (TL) is 73 mm, the length of the signal line (S1) of the first section (PR1) of the electronic device of FIG. 2 is 70 mm, and the signal lines (S2) of the second section (PR2) are 70 mm. , S3) each length may be 3 mm. The length (e.g., first length L1) of the signal line SL11 of the first section PR1 of the electronic device of FIG. 3A is 36.5 mm, and the signal lines SL21 of the second section PR2 are 36.5 mm. 22) Each length may be 36.5mm.

T.L. 73mm 93mm 113mm 133mm Margin 1 174ps 179ps 223ps 218ps Margin 2 311ps 600ps 270ps 279ps

When the total length (TL) is 73 mm, the signal margin of the electronic device of FIG. 2 may be 174 ps, and the signal margin of the electronic device of FIG. 3A may be 311 ps. When the total length (TL) is 93 mm, the signal margin of the electronic device of FIG. 2 may be 179 ps, and the signal margin of the electronic device of FIG. 3A may be 600 ps. When the total length (TL) is 113 mm, the signal margin of the electronic device of FIG. 2 may be 223 ps, and the signal margin of the electronic device of FIG. 3A may be 270 ps. When the total length (TL) is 133 mm, the signal margin of the electronic device of FIG. 2 may be 218 ps, and the signal margin of the electronic device of FIG. 3A may be 279 ps. The above-described numerical values are illustrative to clearly describe embodiments of the present disclosure, and the scope of the present disclosure is not limited thereto. As described above, the electronic device according to an embodiment of the present disclosure can increase the signal margin by adjusting the length of the signal line in the first section PR1 and the length of each signal line in the second section PR2. there is.

Figure 19 is a block diagram showing an SSD system to which an electronic device is applied according to an embodiment of the present disclosure. Referring to FIG. 19, the SSD system 1000 includes a host 1100 and an SSD 1400.

The SSD 1400 exchanges a signal (SIG) with the host 1100 through the signal connector 1201 and receives power (PWR) through the power connector 1202. The SSD 1400 includes an SSD memory controller 1410, a plurality of flash memories 1221 to 122n, an auxiliary power supply 1230, and a buffer memory 1240.

The SSD memory controller 1410 may control a plurality of flash memories 1221 to 122n in response to a signal SIG received from the host 1100. The plurality of flash memories 1221 to 122n may operate under the control of the SSD memory controller 1410. The auxiliary power device 1230 is connected to the host 1100 through the power connector 1002. The auxiliary power device 1230 can receive power (PWR) from the host 1100 and charge it. The auxiliary power device 1230 may provide power to the SSD 1400 when power supply from the host 1100 is not smooth.

In one embodiment, SSD 1400 may have the topology described with reference to FIGS. 1 to 18C. For example, various components included in the SSD 1400 may be mounted on a printed circuit board and electrically connected to each other through various signal lines included in the printed circuit board. At this time, as described above, the signal lines between the SSD memory controller 1410 and the plurality of memory devices 1221 to 122n have a predetermined ratio or by adding stubs, The influence of reflected signals can be attenuated.

The above-described contents are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also embodiments that are simply designed or can be easily changed. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of the present invention as well as the claims described below.

100: electronic device
110: memory controller
120: plural memory devices

Claims (10)

first to eighth memory devices;
a memory controller configured to control the first to eighth memory devices;
a first signal line configured to electrically connect between the memory controller and a first branch point;
a second signal line configured to electrically connect between the first branch point and the second branch point;
a third signal line configured to electrically connect between the first branch point and the third branch point;
a fourth signal line configured to electrically connect between the second branch point and the fourth branch point;
a fifth signal line configured to electrically connect between the second branch point and the fifth branch point;
a sixth signal line configured to electrically connect between the third branch point and the sixth branch point;
It includes a seventh signal line configured to electrically connect between the third branch point and the seventh branch point,
The first memory device and the second memory device are connected to the fourth branch point, the third memory device and the fourth memory device are connected to the fifth branch point, and the fifth memory device and the sixth memory A device is connected to the sixth branch point, the seventh memory device and the eighth memory device are connected to the seventh branch point,
The length of the second signal line is shorter than the length of the fourth signal line,
The length of the third signal line is shorter than the length of the sixth signal line.
According to claim 1,
The length of the second signal line is shorter than the length of the fifth signal line,
An electronic device in which the length of the third signal line is shorter than the length of the seventh signal line.
According to claim 1,
an eighth signal line configured to electrically connect the first memory device and the fourth branch point;
a ninth signal line configured to electrically connect the second memory device and the fourth branch point;
a tenth signal line configured to electrically connect the third memory device and the fifth branch point;
an eleventh signal line configured to electrically connect the fourth memory device and the fifth branch point;
a twelfth signal line configured to electrically connect the fifth memory device and the sixth branch point;
a thirteenth signal line configured to electrically connect the sixth memory device and the sixth branch point;
a fourteenth signal line configured to electrically connect the seventh memory device and the seventh branch point;
The electronic device further includes a fifteenth signal line configured to electrically connect the seventh memory device and the eighth branch point.
According to claim 3,
The electronic device wherein the length of the first signal line is equal to the sum of the lengths of the second signal line, the fourth signal line, and the eighth signal line.
According to claim 3,
The electronic device further includes a stub, one end of which is electrically connected to at least one of the first to fifteenth signal lines, and the other end of which is open and not connected to any other electrical path.
According to claim 5,
The stub includes first to fourth stubs,
One end of the first stub is electrically connected to the fourth branch point, and the other end is open without being connected to any other electrical path,
One end of the second stub is electrically connected to the fifth branch point, and the other end is open without being connected to any other electrical path,
One end of the third stub is electrically connected to the sixth branch point, and the other end is open without being connected to any other electrical path,
The fourth stub is an electronic device in which one end is electrically connected to the seventh branch point and the other end is open without being connected to any other electrical path.
According to claim 5,
The stub includes a fifth stub and a sixth stub,
One end of the fifth stub is electrically connected to the second branch point, and the other end is open without being connected to any other electrical path,
An electronic device in which one end of the sixth stub is electrically connected to the third branch point and the other end is open without being connected to any other electrical path.
According to claim 5,
The stub includes a seventh stub,
An electronic device in which one end of the seventh stub is electrically connected to the first branch point and the other end is open without being connected to any other electrical path.
first to fourth memory devices;
a memory controller configured to control the first to fourth memory devices;
a first signal line configured to electrically connect between the memory controller and a first branch point;
a second signal line configured to electrically connect between the first branch point and the second branch point;
a third signal line configured to electrically connect between the first branch point and the third branch point;
a fourth signal line configured to electrically connect between the second branch point and the first memory device;
a fifth signal line configured to electrically connect between the second branch point and the second memory device;
a sixth signal line configured to electrically connect between the third branch point and the third memory device;
A seventh signal line configured to electrically connect between the third branch point and the fourth memory device,
The length of the second signal line is shorter than the length of the fourth signal line,
The length of the third signal line is shorter than the length of the sixth signal line.
A printed circuit board including a top side and a bottom side;
a memory controller mounted on the upper surface;
first and second memory devices mounted on the upper surface;
a third memory device mounted on the lower surface to face the first memory device; and
A fourth memory device mounted on the lower surface to face the second memory device,
The printed circuit board:
a first branch point spaced apart from the memory controller by a first distance and electrically connected to the memory controller;
a second branch point spaced apart from the first branch point by a second distance and electrically connected to the first branch point, the first memory device, and the third memory device; and
A third branch point is spaced apart from the first branch point by the second distance and is electrically connected to the first branch point, the second memory device, and the fourth memory device,
The distance between the second branch point and the first memory device is a third distance, and the second distance is shorter than the third distance,
The distance between the third branch point and the second memory device is a fourth distance, and the fourth distance is shorter than the second distance.