KR20240105739A - Data driving circuit, image driving method and sensing method - Google Patents

Abstract

Embodiments of the present disclosure relate to a data driving circuit, a display device, an image driving method, and a sensing method. More specifically, the data driving circuit is a common operational amplifier circuit where the function of the operational amplifier circuit is changed by a reset signal. , It is possible to have a compact circuit structure by being composed of a common sensing circuit part electrically connected to the common operational amplifier circuit part, and a common driving circuit part electrically connected to the common operational amplifier circuit part.

Description

Data driving circuit, display device, image driving method, and sensing method {DATA DRIVING CIRCUIT, IMAGE DRIVING METHOD AND SENSING METHOD}

Embodiments of the present disclosure relate to a data driving circuit, a display device, an image driving method, and a sensing method.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, various display devices such as liquid crystal displays and organic light emitting display devices have been used.

A display device includes a display panel having multiple data lines, multiple gate lines, and multiple subpixels, a data driving circuit that outputs data signals through multiple data lines, and a gate driver that outputs scan signals through multiple gate lines. It may include circuits, etc.

The data driving circuit may include an image driving circuit for supplying a data voltage to a sub-pixel for displaying an image and a sensing circuit for sensing characteristic values of the sub-pixel.

As described above, in the data driving circuit, the image driving circuit part and the sensing circuit part are configured and arranged separately, so there are limitations in reducing the size of the data driving circuit.

Embodiments of the present disclosure can provide a data driving circuit with a compact circuit structure, a display device, an image driving method, and a sensing method.

Embodiments of the present disclosure can provide a display device capable of low power consumption by constructing a compact circuit structure, an image driving method, and a sensing method thereof.

Embodiments of the present disclosure include a display panel on which a plurality of subpixels are arranged, a data driving circuit that supplies a data voltage to the plurality of subpixels, and the data driving circuit includes an operational amplifier where the function of the operational amplifier circuit is reset. It is electrically connected through a common operational amplifier circuit changed by a signal, an output terminal of the operational amplifier included in the common operational amplifier circuit, and an output line, a common sensing circuit for sensing voltage, a non-inverting terminal of the operational amplifier, and the first A display device that is electrically connected through an input line and includes a common driving circuit for supplying voltage can be provided.

In embodiments of the present disclosure, the reference voltage supplied to the reference voltage line is supplied to the first node, which is the gate node of the driving transistor, and the image driving data voltage supplied to the common line is supplied to the second node of the driving transistor. A data driving circuit comprising a step, a second step in which the first node and the second node are floated, and a third step in which the light emitting element driven by the driving transistor emits light, and supplies a reference voltage and a data voltage for image driving, A common operational amplifier circuit where the function of the operational amplifier circuit including the operational amplifier is changed by a reset signal, and is electrically connected to the output terminal of the operational amplifier included in the common operational amplifier circuit through an output line, and is electrically connected to the common operational amplifier circuit for sensing voltage. It is electrically connected to the sensing circuit part and the non-inverting terminal of the operational amplifier through a first input line, and includes a common driving circuit part for supplying a voltage. In the first step, the common driving circuit part provides a non-inverting data voltage for image driving. A method of driving an image of a display device can be provided in which the data voltage for image driving is supplied to a common line through a second input line electrically connected to the inverting terminal of an operational amplifier.

Embodiments of the present disclosure include an initialization step in which the reference voltage supplied to the reference voltage line is supplied to the first node, which is the gate node of the driving transistor, and the sensing driving data voltage supplied to the common line is supplied to the second node of the driving transistor. , a tracking step in which the second node is floating and the voltage of the second node is raised, a sensing step in which the analog-to-digital converter and the common line are electrically connected, and the analog-to-digital converter senses the voltage of the common line, and the reference The data driving circuit that supplies voltage and data voltage for sensing driving includes a common operational amplifier circuit section in which the function of the operational amplifier circuit including an operational amplifier is changed by a reset signal, an output terminal of the operational amplifier included in the common operational amplifier circuit section, and It is electrically connected through an output line, includes a common sensing circuit for sensing the voltage, is electrically connected through a non-inverting terminal of the operational amplifier and a first input line, and includes a common driving circuit for supplying the voltage, and includes an initialization step. In the common driving circuit unit, the data voltage for sensing driving is supplied to the non-inverting terminal, and the data voltage for sensing driving is supplied to the common line through a second input line electrically connected to the inverting terminal of the operational amplifier included in the common operational amplifier circuit part. In the sensing step, the common sensing circuit unit may provide a sensing method for a display device that senses the voltage of a common line.

Embodiments of the present disclosure include a common operational amplifier circuit in which the function of an operational amplifier circuit including an operational amplifier is changed by a reset signal, and the output terminal of the operational amplifier included in the common operational amplifier circuit is electrically connected through an output line, Provides a data driving circuit including a common sensing circuit for sensing voltage, a common driving circuit for supplying voltage, and is electrically connected to the non-inverting terminal of the operational amplifier included in the common operational amplifier circuit through a first input line. can do.

According to embodiments of the present disclosure, the reference voltage supplied to the reference voltage line is supplied to the first node, which is the gate node of the driving transistor, and the data voltage for sensing driving supplied to the common line is supplied to the second node of the driving transistor. a voltage initialization step, a voltage tracking step in which the voltage of the output terminal of the operational amplifier that receives current through the common line changes, and the analog-to-digital converter and the common line are electrically connected, and the analog-to-digital converter adjusts the voltage of the common line. The data driving circuit, which includes a voltage sensing step and supplies a reference voltage and a data voltage for sensing driving, includes a common operational amplifier circuit section in which the function of the operational amplifier circuit including an operational amplifier is changed by a reset signal, and a common operational amplifier. It is electrically connected through the output terminal of the operational amplifier included in the circuit part and the output line, and is electrically connected through the common sensing circuit part for sensing the voltage, and the non-inverting terminal of the operational amplifier and the first input line, and supplies voltage. In the voltage initialization step, the common driving circuit supplies the sensing driving data voltage to the non-inverting terminal, and the sensing driving data voltage is supplied to the inverting terminal of the operational amplifier included in the common operational amplifier circuit. It is supplied to the common line through an electrically connected second input line, and in the voltage sensing step, the common sensing circuit unit can provide a sensing method for a display device that senses the voltage of the common line.

According to embodiments of the present disclosure, it is possible to provide a data driving circuit with a compact circuit structure, a display device, an image driving method, and a sensing method.

According to embodiments of the present disclosure, a display device capable of low power consumption by configuring a circuit structure compactly, an image driving method thereof, and a sensing method can be provided.

1 is a configuration diagram of a display device according to embodiments of the present disclosure.
2 is an equivalent circuit of a subpixel of a display device according to embodiments of the present disclosure.
3 is a circuit diagram of a source driver integrated circuit and a subpixel according to embodiments of the present disclosure.
4 is an equivalent circuit of a subpixel of a display device according to embodiments of the present disclosure.
5 is a circuit diagram of a source driver integrated circuit and a subpixel according to embodiments of the present disclosure.
Figure 6 is a flowchart of an image driving method of a display device according to embodiments of the present disclosure.
7 is a circuit diagram related to an image driving method of a display device according to embodiments of the present disclosure.
Figure 8 is a flowchart of a voltage-based sensing method of a display device according to embodiments of the present disclosure.
FIG. 9 is a timing diagram of a voltage-based sensing method of a display device according to embodiments of the present disclosure.
10 to 12 are circuit diagrams related to a voltage-based sensing method of a display device according to embodiments of the present disclosure.
Figure 13 is a flowchart of a current-based sensing method of a display device according to embodiments of the present disclosure.
FIG. 14 is a timing diagram of a current-based sensing method of a display device according to embodiments of the present disclosure.
15 to 17 are circuit diagrams related to a current-based sensing method of a display device according to embodiments of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to illustrative drawings. In adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, in describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the explanation of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

Meanwhile, when a numerical value or corresponding information (e.g., level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g., process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a system configuration diagram of a display device 100 according to embodiments of the present disclosure.

Referring to FIG. 1 , a display device 100 according to embodiments of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110 .

The display panel 110 includes signal lines such as a plurality of data lines DL and a plurality of gate lines GL, and may include a plurality of subpixels SP. The display panel 110 may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed. In the display panel 110, a plurality of subpixels (SP) for displaying an image are disposed in the display area (DA), and the driving circuits 120, 130, and 140 are electrically connected to the non-display area (NDA). The driving circuits 120, 130, and 140 may be connected or mounted, and a pad portion to which an integrated circuit or printed circuit, etc., may be connected may be disposed.

The driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and may further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

The data driving circuit 120 is a circuit for driving a plurality of data lines DL and can supply data signals to the plurality of data lines DL. The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL and can supply gate signals to the plurality of gate lines GL.

The gate driving circuit 130 may output a gate signal of a turn-on level voltage or a gate signal of a turn-off level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive a plurality of gate lines GL by sequentially supplying a gate signal with a turn-on level voltage to the plurality of gate lines GL.

The controller 140 may supply a data control signal (DCS) to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 may supply a gate control signal (GCS) to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

The controller 140 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to fit the data signal format used in the data driving circuit 120, and produces converted image data (Data). can be supplied to the data driving circuit 120, and data driving can be controlled at an appropriate time according to the scan.

The controller 140 controls the data driving circuit 120 and the gate driving circuit 130, including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable signal (DE), and a clock signal ( A timing signal such as CLK) is input, various control signals (DCS, GCS) are generated and output to the data driving circuit 120 and the gate driving circuit 130.

The controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 receives image data Data from the controller 140 and supplies a data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 is also called a source driving circuit. This data driving circuit 120 may include one or more source driver integrated circuits (SDIC). Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. In some cases, each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC).

For example, each source driver integrated circuit (SDIC) is connected to the display panel 110 using Tape Automated Bonding (TAB), Chip On Glass (COG), or Chip On Panel ( It may be connected to the bonding pad of the display panel 110 using a COP (Chip On Panel) method, or may be implemented using a Chip On Film (COF) method and connected to the display panel 110.

The gate driving circuit 130 is connected to the display panel 110 using a tape automated bonding (TAB) method, or is connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method. Pad) or may be connected to the display panel 110 according to the chip-on-film (COF) method. Alternatively, the gate driving circuit 130 may be of the GIP (Gate In Panel) type and may be formed in the non-display area NDA of the display panel 110.

When a specific gate line (GL) is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data (Data) received from the controller 140 into an analog data voltage to generate a plurality of data lines. It can be supplied as (DL).

The data driving circuit 120 may be connected to one side (eg, the upper or lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., upper and lower sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. It may be possible.

The gate driving circuit 130 may be connected to one side (eg, left or right) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 130 may be connected to both sides (e.g., left and right) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. It may be possible.

The controller 140 may be a timing controller 140 (Timing Controller) used in typical display technology, or a control device that further performs other control functions including the timing controller 140 (Timing Controller). It may be a control device different from the controller 140, or it may be a circuit within the control device. The controller 140 may be implemented with various circuits or electronic components such as an Integrated Circuit (IC), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), or Processor.

The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board, a flexible printed circuit, etc. The controller 140 may transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, a Serial Peripheral Interface (SPI), etc. The controller 140 may include a storage location such as one or more registers.

The display device 100 according to the present embodiments may be a self-luminous display such as an Organic Light Emitting Diode (OLED) display, a Quantum Dot display, or a Micro Light Emitting Diode (Micro LED) display.

FIG. 2 is an equivalent circuit of a subpixel (SP) of the display device 100 according to embodiments of the present disclosure.

Referring to FIG. 2, each of the plurality of subpixels (SP) disposed on the display panel 110 of the display device 100 according to embodiments of the present disclosure includes a light emitting element (ED), a driving transistor (DRT), and a scan function. It may include a transistor (SCT), a sensing transistor (SENT), and a storage capacitor (Cst). In this way, when the subpixel (SP) includes three transistors (DRT, SCT, SENT) and one capacitor (Cst), the subpixel (SP) is said to have a 3T (Transistor) 1C (Capacitor) structure. .

The light emitting device (ED) may include a pixel electrode (PE), a common electrode (CE), and a light emitting layer (EL) located between the pixel electrode (PE) and the common electrode (CE). Here, the pixel electrode PE may be disposed in each subpixel SP, and the common electrode CE may be commonly disposed in multiple subpixels SP. For example, the pixel electrode (PE) may be an anode electrode, and the common electrode (CE) may be a cathode electrode. For another example, the pixel electrode (PE) may be a cathode electrode, and the common electrode (CE) may be an anode electrode. For example, the light emitting device (ED) may be an organic light emitting diode (OLED), a micro light emitting diode (micro LED), or a quantum dot light emitting device (ED).

The driving transistor DRT is a transistor for driving the light emitting device ED and may include a first node N1, a second node N2, and a third node N3.

The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT and may be electrically connected to the source node or drain node of the scan transistor SCT. The second node (N2) of the driving transistor (DRT) may be a source node or a drain node of the driving transistor (DRT), is electrically connected to the source node or drain node of the sensing transistor (SENT), and is connected to the light emitting element (ED). It can also be electrically connected to the pixel electrode (PE) of . The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL that supplies the driving voltage EVDD.

The scan transistor (SCT) is controlled by the scan signal (SCAN) and may be connected between the first node (N1) of the driving transistor (DRT) and the data line (DL). The scan transistor (SCT) is turned on or off according to the scan signal (SCAN) supplied from the scan signal line (SCL), a type of gate line (GL), and is connected to the data line (DL) and the driving transistor ( The connection between the first nodes (N1) of the DRT) can be controlled.

The scan transistor (SCT) is turned on by the scan signal (SCAN) having a turn-on level voltage, and transmits the data voltage (Vdata) supplied from the data line (DL) to the first node ( It can be passed on to N1).

The turn-on level voltage of the scan signal (SCAN) that can turn on the scan transistor (SCT) may be a high level voltage or a low level voltage. The turn-off level voltage of the scan signal SCAN that can turn off the scan transistor SCT may be a low level voltage or a high level voltage. For example, when the scan transistor (SCT) is an n-type transistor, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. For another example, when the scan transistor (SCT) is a p-type transistor, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The sensing transistor SENT is controlled by the sense signal SENSE and may be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. The sensing transistor (SENT) is turned on or turned off according to the sense signal (SENSE) supplied from the sense signal line (SENL), which is another type of gate line (GL), and is driven with the reference voltage line (RVL). The connection between the second nodes (N2) of the transistor (DRT) can be controlled.

The sensing transistor (SENT) is turned on by the sense signal (SENSE) having a turn-on level voltage, and connects the reference voltage (Vref) supplied from the reference voltage line (RVL) to the second node of the driving transistor (DRT). You can forward it to (N2).

The turn-on level voltage of the sense signal (SENSE) that can turn on the sensing transistor (SENT) may be a high level voltage or a low level voltage. The turn-off level voltage of the sense signal (SENSE) that can turn off the sensing transistor (SENT) may be a low level voltage or a high level voltage. For example, when the sensing transistor SENT is an n-type transistor, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. For another example, when the sensing transistor SENT is a p-type transistor, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

Meanwhile, the display device 100 includes a line capacitor (Crvl) formed between the reference voltage line (RVL) and the ground (GND), and a sampling switch that controls the connection between the reference voltage line (RVL) and the analog-to-digital converter (ADC). It may further include a power switch (SPRE) that controls the connection between (SAM), the reference voltage line (RVL), and the reference voltage supply node (Nref). The reference voltage (Vref) output from the power supply device is supplied to the reference voltage supply node (Nref) and may be applied to the reference voltage line (RVL) through the power switch (SPRE).

In addition, the sensing transistor (SENT) is turned on by the sense signal (SENSE) having a turn-on level voltage, so that the voltage (V2) of the second node (N2) of the driving transistor (DRT) is connected to the reference voltage line ( RVL). Accordingly, the line capacitor Crvl formed between the reference voltage line RVL and the ground GND may be charged.

The function of the sensing transistor (SENT) to transfer the voltage (V2) of the second node (N2) of the driving transistor (DRT) to the reference voltage line (RVL) can be used when driving to sense the characteristic value of the subpixel (SP). You can. In this case, the voltage transmitted to the reference voltage line RVL may be a voltage for calculating the characteristic value of the subpixel SP or a voltage reflecting the characteristic value of the subpixel SP.

In the present disclosure, the characteristic values of the subpixel (SP) may be the characteristic values of the driving transistor (DRT) or the light emitting element (ED). Characteristic values of the driving transistor (DRT) may include threshold voltage and mobility of the driving transistor (DRT). The characteristic value of the light emitting device (ED) may include the threshold voltage of the light emitting device (ED).

Each of the driving transistor (DRT), scan transistor (SCT), and sensing transistor (SENT) may be an n-type transistor or a p-type transistor. In this disclosure, for convenience of explanation, the driving transistor (DRT), scan transistor (SCT), and sensing transistor (SENT) are each n-type as an example.

The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor (Cst) is charged with a charge corresponding to the voltage difference between both ends, and serves to maintain the voltage difference between both ends for a set frame time. Accordingly, the corresponding subpixel SP may emit light during a set frame time.

The storage capacitor (Cst) is not a parasitic capacitor (e.g. Cgs, Cgd), which is an internal capacitor that exists between the gate node and the source node (or drain node) of the driving transistor (DRT). ) may be an external capacitor intentionally designed outside of the capacitor.

The scan signal line (SCL) and the sense signal line (SENL) may be different gate lines (GL). In this case, the scan signal (SCAN) and the sense signal (SENSE) may be separate gate signals, and the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) Off timing can be independent. That is, the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) may be the same or different.

Alternatively, the scan signal line (SCL) and the sense signal line (SENL) may be the same gate line (GL). That is, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) within one subpixel (SP) may be connected to one gate line (GL). In this case, the scan signal (SCAN) and the sense signal (SENSE) may be the same gate signal, and the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) may be the same.

Meanwhile, the reference voltage line RVL may be disposed in each subpixel SP column. Alternatively, the reference voltage line RVL may be disposed in each column of two or more subpixels SP. When the reference voltage line RVL is disposed in each column of two or more subpixels SP, the plurality of subpixels SP may receive the reference voltage Vref from one reference voltage line RVL.

3 is a circuit diagram of a source driver integrated circuit (SDIC) and a subpixel (SP) according to embodiments of the present disclosure.

A plurality of subpixels SP may be disposed on the display panel 110. Each of the plurality of subpixels (SP) may include a light emitting element (ED), a driving transistor (DRT), a scan transistor (SCT), a sensing transistor (SENT), a storage capacitor (Cst), etc. The subpixel SP shown in FIG. 3 may be the same as the subpixel SP shown in FIG. 2 . Description of the same features as the subpixel SP shown in FIG. 2 may be omitted.

The data driving circuit 120 may include multiple source driver integrated circuits (SDICs). A multiple source driver integrated circuit (SDIC) may include multiple driving channels (DCH) and multiple sensing channels (SCH).

Each of the multiple data lines DL disposed on the display panel 110 may be connected one-to-one to multiple driving channels DCH. Each of the plurality of reference voltage lines (RVL) disposed on the display panel 110 may be connected to a plurality of sensing channels (SCH) on a one-to-one basis.

Referring to FIG. 3, any one subpixel (SP) among the plurality of subpixels (SP) can be confirmed, and any one source driver integrated circuit (SDIC) among the plurality of source driver integrated circuits (SDICs) can be confirmed. there is. One subpixel (SP) may be electrically connected to one source driver integrated circuit (SDIC). That is, the data line DL may be electrically connected to the driving channel DCH. The reference voltage line (RVL) may be electrically connected to the sensing channel (SCH).

The source driver integrated circuit (SDIC) may include a plurality of image driving circuit units (DB) and a plurality of sensing circuit units (SB). Multiple image driving circuit units (DB) may be connected one-to-one with multiple driving channels (DCH). Multiple sensing circuit units (SB) may be connected one-to-one with multiple sensing channels (SCH).

The image driving circuit unit (DB) may include a shift register unit (SR), a latch unit (Latch), a digital-to-analog converter (DAC), and an output buffer (BUF).

The shift register unit (SR) may sequentially output latch pulses to a plurality of latches included in the latch unit (Latch).

The latch unit (Latch) can sequentially store input data in response to latch pulses.

The digital-to-analog converter (DAC) can convert input data output from the latch into an analog voltage.

The output buffer (BUF) may be a buffer circuit including an operational amplifier (AMP_D). That is, the output buffer BUF may be an operational amplifier circuit that functions as a unit gain buffer with a gain of 1.

The operational amplifier (AMP_D) may include a non-inverting terminal (+), an inverting terminal (-), and an output terminal (Vout_D). The non-inverting terminal (+) of the operational amplifier (AMP_D) may be electrically connected to the digital-to-analog converter (DAC). The inverting terminal (-) of the operational amplifier (AMP_D) may be electrically connected to the output terminal (Vout_D). The output terminal (Vout_D) of the operational amplifier (AMP_D) may be electrically connected to the driving channel (DCH).

The sensing circuit unit (SB) may include a current integrator (CI), sample and hold (S/H), scaler, and analog-to-digital converter (ADC).

The current integrator (CI) may include an operational amplifier (AMP_CI), a feedback capacitor (Cfb), and a reset switch (SRST).

A reference voltage (Vref) may be supplied to the non-inverting terminal (+) of the operational amplifier (AMP_CI). The inverting terminal (-) of the operational amplifier (AMP_CI) may be electrically connected to the sensing channel (SCH). The output terminal (Vout_CI) of the operational amplifier (AMP_CI) may be electrically connected to the sample and hold (S/H).

A feedback capacitor (Cfb) and a reset switch (SRST) may be electrically connected between the inverting terminal (-) of the operational amplifier (AMP_CI) and the output terminal (Vout_CI) of the operational amplifier (AMP_CI).

The reset switch (SRST) can control the connection between circuits by the reset signal (RST).

A reset signal (RST) for connecting the circuit to the reset switch (SRST) may be applied, and a reference voltage (Vref) may be applied to the non-inverting terminal (+). In this case, the voltage charged in the feedback capacitor (Cfb) can be initialized.

Sample and hold (S/H) can sample and hold the sensing voltage output from the current integrator (CI). Although not shown in FIG. 3, sample and hold (S/H) may include a sampling switch (SAM). The sampling switch (SAM) can control the connection between the reference voltage line (RVL) and the analog-to-digital converter (ADC).

The scaler can adjust the size of the sampling value, which is the sensing voltage sampled from the sample and hold (S/H) circuit, within the operating range of the analog-to-digital converter (ADC).

The analog-to-digital converter (ADC) can convert the size-adjusted sampling value from the scaler into a digital format.

As described above, the image driving circuit unit (DB) and the sensing circuit unit (SB) may each be arranged in separate configurations in the source driver integrated circuit (SDIC). As the image driving circuit (DB) and the sensing circuit (SB) are each disposed inside the source driver integrated circuit (SDIC), there are limitations in reducing the size of the data driving circuit 120.

Accordingly, embodiments of the present disclosure can provide a data driving circuit 120, a display device 100, an image driving method, and a sensing method having a compact circuit structure. This will be explained in detail below.

FIG. 4 is an equivalent circuit of a subpixel (SP) of the display device 100 according to embodiments of the present disclosure.

Referring to FIG. 4, each of the plurality of subpixels (SP) disposed on the display panel 110 of the display device 100 according to embodiments of the present disclosure includes a light emitting element (ED), a driving transistor (DRT), and a scan function. It may include a transistor (SCT), a sensing transistor (SENT), and a storage capacitor (Cst).

The light emitting device (ED) may include a pixel electrode (PE), a common electrode (CE), and a light emitting layer (EL) located between the pixel electrode (PE) and the common electrode (CE). Here, the pixel electrode PE may be disposed in each subpixel SP, and the common electrode CE may be commonly disposed in multiple subpixels SP. For example, the pixel electrode (PE) may be an anode electrode, and the common electrode (CE) may be a cathode electrode. For another example, the pixel electrode (PE) may be a cathode electrode, and the common electrode (CE) may be an anode electrode. For example, the light emitting device (ED) may be an organic light emitting diode (OLED), a micro light emitting diode (micro LED), or a quantum dot light emitting device (ED).

The driving transistor DRT is a transistor for driving the light emitting device ED and may include a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT and may be electrically connected to the source node or drain node of the scan transistor SCT. The second node (N2) of the driving transistor (DRT) may be a source node or a drain node of the driving transistor (DRT), is electrically connected to the source node or drain node of the sensing transistor (SENT), and is connected to the light emitting element (ED). It can also be electrically connected to the pixel electrode (PE) of . The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL that supplies the driving voltage EVDD.

The scan transistor SCT is controlled by the scan signal SCAN and may be connected between the first node N1 of the driving transistor DRT and the reference voltage line RVL. The scan transistor (SCT) is turned on or off according to the scan signal (SCAN) supplied from the scan signal line (SCL), a type of gate line (GL), and is connected to the reference voltage line (RVL) and the driving transistor. The connection between the first nodes (N1) of (DRT) can be controlled.

The scan transistor (SCT) is turned on by the scan signal (SCAN) having a turn-on level voltage, and connects the reference voltage (Vref) supplied from the reference voltage line (RVL) to the first node of the driving transistor (DRT). You can forward it to (N1).

The turn-on level voltage of the scan signal (SCAN) that can turn on the scan transistor (SCT) may be a high level voltage or a low level voltage. The turn-off level voltage of the scan signal SCAN that can turn off the scan transistor SCT may be a low level voltage or a high level voltage. For example, when the scan transistor (SCT) is an n-type transistor, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. For another example, when the scan transistor (SCT) is a p-type transistor, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The sensing transistor (SENT) is controlled by the sense signal (SENSE) and may be connected between the second node (N2) of the driving transistor (DRT) and the common line (CL). The sensing transistor (SENT) is turned on or off depending on the sense signal (SENSE) supplied from the sense signal line (SENL), which is another type of gate line (GL), and is connected to the common line (CL) and the driving transistor. The connection between the second node (N2) of (DRT) can be controlled.

The sensing transistor (SENT) is turned on by the sense signal (SENSE) having a turn-on level voltage, and applies the voltage (Vcl) supplied from the common line (CL) to the second node (N2) of the driving transistor (DRT). ) can be passed on. The voltage (Vcl) supplied from the common line (CL) may be a data voltage (Vref-Vdata) for image driving or a data voltage (Vref-Vsen) for sensing driving.

The turn-on level voltage of the sense signal (SENSE) that can turn on the sensing transistor (SENT) may be a high level voltage or a low level voltage. The turn-off level voltage of the sense signal (SENSE) that can turn off the sensing transistor (SENT) may be a low level voltage or a high level voltage. For example, when the sensing transistor SENT is an n-type transistor, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. For another example, when the sensing transistor SENT is a p-type transistor, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The line capacitor (Ccl) may be electrically connected between the common line (CL) and the ground (GND).

In addition, the sensing transistor SENT is turned on by the sense signal SENSE having a turn-on level voltage, and the voltage V2 of the second node N2 of the driving transistor DRT is connected to the common line CL. ) can be delivered. Accordingly, the line capacitor Ccl formed between the common line CL and the ground GND may be charged.

The function of the sensing transistor (SENT) to transfer the voltage (V2) of the second node (N2) of the driving transistor (DRT) to the common line (CL) can be used when driving to sense the characteristic value of the subpixel (SP). there is. In this case, the voltage transmitted to the common line CL may be a voltage for calculating the characteristic value of the subpixel SP or a voltage reflecting the characteristic value of the subpixel SP.

In the present disclosure, the characteristic values of the subpixel (SP) may be the characteristic values of the driving transistor (DRT) or the light emitting element (ED). Characteristic values of the driving transistor (DRT) may include threshold voltage and mobility of the driving transistor (DRT). The characteristic value of the light emitting device (ED) may include the threshold voltage of the light emitting device (ED).

Each of the driving transistor (DRT), scan transistor (SCT), and sensing transistor (SENT) may be an n-type transistor or a p-type transistor. In this disclosure, for convenience of explanation, the driving transistor (DRT), scan transistor (SCT), and sensing transistor (SENT) are each n-type as an example.

The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor (Cst) is charged with a charge corresponding to the voltage difference between both ends, and serves to maintain the voltage difference between both ends for a set frame time. Accordingly, the corresponding subpixel SP may emit light during a set frame time.

The storage capacitor (Cst) is not a parasitic capacitor (e.g. Cgs, Cgd), which is an internal capacitor that exists between the gate node and the source node (or drain node) of the driving transistor (DRT). ) may be an external capacitor intentionally designed outside of the capacitor.

The scan signal line (SCL) and the sense signal line (SENL) may be different gate lines (GL). In this case, the scan signal (SCAN) and the sense signal (SENSE) may be separate gate signals, and the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) Off timing can be independent. That is, the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) may be the same or different.

Alternatively, the scan signal line (SCL) and the sense signal line (SENL) may be the same gate line (GL). That is, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) within one subpixel (SP) may be connected to one gate line (GL). In this case, the scan signal (SCAN) and the sense signal (SENSE) may be the same gate signal, and the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) may be the same.

The common circuit (CB) may be placed in a source driver integrated circuit (SDIC).

The common circuit portion (CB) may be electrically connected to the common line (CL).

The common circuit unit (CB) can supply voltage to the common line (CL). For example, during an image driving period for driving a frame image, a voltage for expressing the frame image may be supplied. As another example, during a sensing drive period for sensing the characteristic value of the subpixel SP, a voltage for sensing the characteristic value of the subpixel SP may be supplied. The common circuit unit (CB) may include circuits such as a shift register unit (SR), a latch unit (Latch), and a digital-to-analog converter (DAC) to supply voltage.

The common circuit unit (CB) can sense the voltage of the common line (CL). For example, the above-mentioned voltage sensing may be performed during a sensing drive period for sensing the characteristic value of the subpixel SP. The common circuit unit (CB) may include circuits such as sample and hold (S/H), scaler, and analog-to-digital converter (ADC) to sense the voltage of the common line (CL).

Below, the circuit configuration of the common circuit unit (CB) will be described in detail.

5 is a circuit diagram of a source driver integrated circuit (SDIC) and a subpixel (SP) according to embodiments of the present disclosure.

A plurality of subpixels SP may be disposed on the display panel 110. Each of the plurality of subpixels (SP) may include a light emitting element (ED), a driving transistor (DRT), a scan transistor (SCT), a sensing transistor (SENT), a storage capacitor (Cst), etc. The plurality of subpixels SP shown in FIG. 5 may be the same as the subpixels SP shown in FIG. 4 .

The data driving circuit 120 may include multiple source driver integrated circuits (SDICs). Multiple source driver integrated circuits (SDICs) may include multiple common channels (CCH) and multiple reference voltage channels (VCH).

Each of the plurality of reference voltage lines (RVL) disposed on the display panel 110 may be connected to a plurality of reference voltage channels (VCH) in a one-to-one relationship. Each of the common lines CL disposed on the display panel 110 may be connected to a plurality of common channels CCH on a one-to-one basis.

The reference voltage line (RVL) may be electrically connected to the reference voltage channel (VCH). The reference voltage Vref may be supplied from the data driving circuit 120 to the reference voltage line RVL through the reference voltage channel VCH.

The common line (CL) may be electrically connected to the common channel (CCH). A line capacitor (Ccl) may be formed between the common line (CL) and the ground (GND). The voltage of the common line CL may be transmitted to the data driving circuit 120 through the common channel CCH.

Referring to FIG. 5, one source driver integrated circuit (SDIC) among a plurality of SDICs can be identified.

Each of the multiple source driver integrated circuits (SDICs) may include a common circuit (CB), a common channel (CCH), and a reference voltage channel (VCH). The common circuit unit (CB) may be electrically connected to the common channel (CCH). The reference voltage Vref may be output to the reference voltage line RVL through the reference voltage channel VCH.

The common circuit (CB) may include a common operational amplifier circuit (CAB), a common sensing circuit (CSB), and a common driving circuit (CDB).

The common operational amplifier circuit (CAB) may include an operational amplifier (AMP_C), a feedback capacitor (Cfb), and a reset switch (SRST).

The common operational amplifier circuit (CAB) can perform the function of a unit gain buffer with a gain of 1 under the control of the reset switch (SRST). Additionally, the common operational amplifier circuit (CAB) can perform the function of a current integrator under the control of the reset switch (SRST).

The non-inverting terminal (+) of the operational amplifier (AMP_C) may be electrically connected to the common driving circuit unit (CDB) through the first input line (IL1). The first connection switch CST1 may be electrically connected between the first input line IL1 and the common driving circuit unit CDB. The first connection switch (CST1) receives the first connection control signal (CCS1) and can control whether or not to supply voltage.

The inverting terminal (-) of the operational amplifier (AMP_C) may be electrically connected to the common channel (CCH) through the second input line (IL2). The second connection switch CST2 may be electrically connected between the second input line IL2 and the common channel CCH. The second connection switch (CST2) can receive the second connection control signal (CCS2) and control whether or not to supply voltage.

The non-inverting terminal (+) of the operational amplifier (AMP_C) may be electrically connected to the common channel (CCH) through the third input line (IL3). The third connection switch CST3 may be electrically connected between the third input line IL3 and the common channel CCH. The third connection switch (CST3) receives the third connection control signal (CCS3) and can control whether or not to supply voltage.

The output terminal (Vout_C) of the operational amplifier (AMP_C) may be electrically connected to the common sensing circuit section (CSB) through the output line (OL). That is, the output terminal (Vout_C) of the operational amplifier (AMP_C) may be electrically connected to the sample and hold (S/H).

A feedback capacitor Cfb may be electrically connected between the inverting terminal (-) of the operational amplifier (AMP_C) and the output terminal (Vout_C) of the operational amplifier (AMP_C). A reset switch (SRST) may be electrically connected between the inverting terminal (-) of the operational amplifier (AMP_C) and the output terminal (Vout_C) of the operational amplifier (AMP_C). That is, the feedback capacitor Cfb and the reset switch SRST may be connected in parallel between the inverting terminal (-) of the operational amplifier (AMP_C) and the output terminal (Vout_C) of the operational amplifier (AMP_C).

The reset switch (SRST) can control the connection between the inverting terminal (-) and the output terminal (Vout_C) by using the reset signal (RST).

The common sensing circuit unit (CSB) may perform a function of sensing the voltage of the common line (CL).

The common sensing circuit unit (CSB) may include a sample and hold (S/H), a scaler, and an analog-to-digital converter (ADC) to sense the voltage of the common line (CL).

Sample and hold (S/H) can receive the output of the common operational amplifier circuit (CAB) through the output line (OL). Sample and hold (S/H) can sample and hold the sensing voltage output from the common operational amplifier circuit (CAB).

Although not shown in FIG. 5, sample and hold (S/H) may include a sampling switch (SAM). As the sampling switch (SAM) is controlled, the voltage of the common line (CL) can be supplied to the analog-to-digital converter (ADC). In other words, a turn-on signal may be supplied to the sampling switch (SAM) at a specific point in time to sense the voltage of the common line (CL), and accordingly the voltage of the common line (CL) is converted to the analog-to-digital converter (ADC). can be supplied. Referring to Figures 12 and 16, an equivalent circuit in which a turn-on signal is supplied to the sampling switch (SAM) and the voltage of the common line (CL) can be supplied to the analog-to-digital converter (ADC) can be confirmed. When it is not a specific time to sense the voltage of the common line CL, a turn-off signal may be supplied to the sampling switch SAM.

The scaler can adjust the size of the sampling value, which is the sensing voltage sampled from sample and hold (S/H), within the operating range of the analog-to-digital converter (ADC). Since the analog-to-digital converter (ADC) may have a limited voltage range that can be sensed, a scaler can adjust the size of the sensing voltage and supply it to the analog-to-digital converter (ADC).

The analog-to-digital converter (ADC) can convert the size-adjusted sampling value from the scaler into a digital format. The analog-to-digital converter (ADC) can supply the sensing voltage converted to a digital value to the controller 140. Thereafter, the controller 140 may determine the characteristic value of the subpixel (SP) based on the sensing voltage converted to a digital value.

The common driving circuit unit (CDB) may perform the function of supplying voltage to the common line (CL).

The common driving circuit unit (CDB) may include a shift register unit (SR), a latch unit (Latch), and a digital-to-analog converter (DAC) to supply voltage to the common line CL.

The shift register unit (SR) may sequentially output latch pulses to a plurality of latches included in the latch unit (Latch).

The latch unit (Latch) can sequentially store input data in response to latch pulses.

The digital-to-analog converter (DAC) can convert input data output from the latch into an analog voltage. The voltage output from the digital-to-analog converter (DAC) may be transmitted to the non-inverting terminal (+) through the first input line (IL1).

The voltage output from the digital-to-analog converter (DAC) may be a data voltage for image driving (Vref-Vdata) or a data voltage for sensing driving (Vref-Vsen).

A first connection switch (CST1) may be electrically connected between the digital-to-analog converter (DAC) and the first input line (IL1). The first connection switch (CST1) may receive the first connection control signal (CCS1). Accordingly, the first connection switch (CST1) can control whether or not to supply the voltage output from the digital-to-analog converter (DAC).

As described above, each of the multiple source driver integrated circuits (SDICs) may include a common circuit section (CB), and image driving and sensing may be performed using the common circuit section (CB).

That is, embodiments of the present disclosure can provide a data driving circuit 120, a display device 100, an image driving method, and a sensing method having a compact circuit structure. Hereinafter, the image driving method of the display device 100 will be described in detail with reference to FIGS. 6 and 7 . Additionally, the sensing method of the display device 100 will be described in detail with reference to FIGS. 8 to 16 .

FIG. 6 is a flowchart of an image driving method of the display device 100 according to embodiments of the present disclosure. FIG. 7 is a circuit diagram related to an image driving method of the display device 100 according to embodiments of the present disclosure.

Referring to FIG. 6 , the image driving method of the display device 100 may include a voltage supply step (S610), a floating step (S620), and a light emission step (S630).

In the voltage supply step (S610), the reference voltage (Vref) supplied to the reference voltage line (RVL) is supplied to the first node (N1), which is the gate node of the driving transistor (DRT), and the image supplied to the common line (CL) This may be a stage in which the driving data voltage (Vref-Vdata) is supplied to the second node (N2) of the driving transistor (DRT).

The reference voltage (Vref) may be a voltage of a certain magnitude. The reference voltage Vref may be supplied to the reference voltage line RVL through the reference voltage channel VCH.

A scan signal (SCAN) for switching the scan transistor (SCT) to the turn-on state may be supplied to the gate node of the scan transistor (SCT).

That is, since the scan transistor (SCT) can be switched to the turn-on state, the reference voltage (Vref) can be supplied to the first node (N1), which is the gate node of the driving transistor (DRT).

The image driving data voltage (Vref-Vdata) may be a voltage that varies depending on the image pattern. The image driving data voltage (Vref-Vdata) can be output from the common driving circuit unit (CDB) and supplied to the non-inverting terminal (+). That is, the common driving circuit unit (CDB) can output the image driving data voltage (Vref-Vdata).

Referring to FIG. 7, the first connection switch (CST1) is supplied with the first connection control signal (CCS1) to form a voltage or current path, and the non-inverting terminal (+) of the operational amplifier (AMP_C) is the first input. It may be electrically connected to the common driving circuit unit (CDB) through the line IL1. The second connection switch (CST2) is supplied with a second connection control signal (CCS2) to form a voltage or current path, and the inverting terminal (-) of the operational amplifier (AMP_C) is common through the second input line (IL2). It can be electrically connected to the channel (CCH). The third connection switch CST3 may receive a third connection control signal CCS3 for blocking voltage or current, so that no current flows and no voltage is supplied to the third input line IL3.

Meanwhile, referring to FIG. 7, in the voltage supply step (S610), a reset signal (RST) may be applied to the reset switch (SRST), and accordingly, the inverting terminal (-) and the output terminal (Vout_C) may be electrically connected. You can. That is, the common operational amplifier circuit (CAB) may be an operational amplifier circuit that functions as a unit gain buffer with a gain of 1.

Referring to FIG. 7, since the common operational amplifier circuit (CAB) is composed of a circuit with a buffer circuit function, the image driving data voltage (Vref-Vdata) supplied to the non-inverting terminal (+) is connected to the inverting terminal (-). can be supplied. The image driving data voltage (Vref-Vdata) supplied to the inverting terminal (-) may be supplied to the common line (CL) through the common channel (CCH).

In the voltage supply step (S610), a sense signal (SENSE) for switching the sensing transistor (SENT) to the turn-on state may be supplied to the gate node of the sensing transistor (SENT).

That is, since the sensing transistor (SENT) can be switched to the turn-on state, the image driving data voltage (Vref-Vdata) can be supplied to the second node (N2).

In other words, the reference voltage (Vref) can be supplied to the first node (N1), which is the gate node of the driving transistor (DRT), and the data voltage (Vref-Vdata) for image driving can be supplied to the second node (N2). there is.

This may be the same as the voltage supplied to both ends of the storage capacitor (Cst). That is, a voltage (Vdata) corresponding to the potential difference between the image driving data voltage (Vref-Vdata) and the reference voltage (Vref) can be stored in the storage capacitor (Cst), and the voltage (Vdata) stored in the storage capacitor (Cst) You can express an image using .

The floating step (S620) may be a step in which the first node (N1) and the second node (N2) are floated.

In the floating step (S620), a scan signal (SCAN) for switching the scan transistor (SCT) to the turn-off state may be supplied to the gate node of the scan transistor (SCT), and the gate node of the sensing transistor (SENT) may be supplied. A sense signal (SENSE) may be supplied to switch the sensing transistor (SENT) to the turn-off state.

Accordingly, the first node N1 of the driving transistor DRT and the second node N2 of the driving transistor DRT may be in a floating state. As the first node (N1) and the second node (N2) are floating, the potential difference (Vdata) between the first node (N1) and the second node (N2) is maintained and the first node (N1), which is the driving transistor gate node, is maintained. The voltage of the second node N2, which is the source node, may increase simultaneously.

The light emission step (S630) may be a step in which a light emitting device driven by a driving transistor emits light.

When the voltage of the first node N1 and the second node N2 increases and reaches a voltage state capable of supplying current to the light emitting device ED, the light emitting step (S630) may proceed.

In the light emission step (S630), current is supplied to the light emitting device ED so that the light emitting device ED can emit light.

In the light emission step (S630), the luminance expressed by the subpixel SP according to the light emission of the light emitting device ED is the luminance corresponding to the voltage difference Vdata between the first node N1 and the second node N2. It can be.

FIG. 8 is a flowchart of a voltage-based sensing method of the display device 100 according to embodiments of the present disclosure. FIG. 9 is a timing diagram of a voltage-based sensing method of the display device 100 according to embodiments of the present disclosure. 10 to 12 are circuit diagrams related to a voltage-based sensing method of the display device 100 according to embodiments of the present disclosure.

Below, the sensing method of the display device 100 will be briefly described with reference to FIG. 8 and then the sensing method of the display device 100 will be described in detail with reference to FIGS. 9 to 12.

Referring to FIG. 8, the sensing method of the display device 100 may include an initialization step (S810), a tracking step (S820), and a sensing step (S830).

In the initialization step (S810), the reference voltage (Vref) supplied to the reference voltage line (RVL) is supplied to the first node (N1), which is the gate node of the driving transistor (DRT), and the sensing drive is supplied to the common line (CL). This may be a stage in which the data voltage (Vref-Vsen) is supplied to the second node (N2) of the driving transistor.

The tracking step (S820) may be a step in which the second node (N2) is floating and the voltage of the second node (N2) is increased. In the tracking step (S820), a turn-off signal may be supplied to the second connection switch (CST2) and the third connection switch (CST3). Accordingly, voltage may not be supplied to the common line CL. As voltage is not supplied to the common line CL, voltage may not be supplied to the second node N2. That is, the second node N2 may be in a floating state.

The sensing step (S830) may be a step in which the analog-to-digital converter (ADC) and the common line (CL) are electrically connected and the analog-to-digital converter (ADC) senses the voltage of the common line (CL). In the sensing step (S830), a turn-on signal may be supplied to the sampling switch (SAM), and accordingly, the voltage of the common line (CL) may be supplied to the analog-to-digital converter (ADC).

Referring to FIG. 9, the sensing driving period may include an initialization period (Tinit), a tracking period (Ttrack), and a sensing period (Tsen). The initialization period (Tinit) may correspond to the initialization step (S810), the tracking period (Ttrack) may correspond to the tracking step (S820), and the sensing period (Tsen) may correspond to the sensing step (S830).

Referring to FIG. 9, the initialization period (Tinit) may be a period for initializing the first node (N1) and the second node (N2) of the driving transistor (DRT). During the initialization period (Tinit), the scan transistor (SCT) and the sensing transistor (SENT) may be turned on.

During the initialization period (Tinit), the voltage (V1) of the first node (N1) of the driving transistor (DRT) may be initialized to the reference voltage (Vref), and the voltage of the second node (N2) of the driving transistor (DRT) (V2) can be initialized to the data voltage (Vref-Vsen) for sensing driving.

Referring to FIG. 9 , in order to supply data voltages Vref-Vsen for sensing driving during the initialization period Tinit, the first to third connection switches CST1 to CST3 may be controlled as follows.

Referring to FIG. 9, during the initialization period (Tinit), a turn-on signal may be supplied to the first connection switch (CST1). Referring to FIG. 10, a first connection control signal (CCS1) for forming a voltage or current path may be supplied to the first connection switch (CST1). Accordingly, the non-inverting terminal (+) of the operational amplifier (AMP_C) may be electrically connected to the common driving circuit unit (CDB) through the first input line (IL1).

Referring to FIG. 9, during the initialization period (Tinit), a turn-on signal may be supplied to the second connection switch (CST2). Referring to FIG. 10, a second connection control signal (CCS2) for forming a voltage or current path may be supplied to the second connection switch (CST2). Accordingly, the inverting terminal (-) of the operational amplifier (AMP_C) may be electrically connected to the common channel (CCH) through the second input line (IL2).

Referring to FIG. 9, during the initialization period (Tinit), a turn-off signal may be supplied to the third connection switch (CST3). Referring to FIG. 10, a third connection control signal (CCS3) for blocking voltage or current may be supplied to the third connection switch (CST3). Accordingly, current may not flow and voltage may not be supplied to the third input line IL3.

Referring to FIG. 10, the reference voltage Vref may be supplied to the reference voltage line RVL through the reference voltage channel VCH. The reference voltage (Vref) may be a voltage of a certain magnitude.

A scan signal (SCAN) for switching the scan transistor (SCT) to the turn-on state may be supplied to the gate node of the scan transistor (SCT).

That is, since the scan transistor (SCT) can be switched to the turn-on state, the reference voltage (Vref) can be supplied to the first node (N1), which is the gate node of the driving transistor (DRT).

The data voltage (Vref-Vsen) for sensing driving may be output from the common driving circuit (CDB) and supplied to the non-inverting terminal (+). That is, the common driving circuit unit (CDB) can supply the sensing driving data voltage (Vref-Vsen) to the non-inverting terminal (+).

Meanwhile, referring to FIG. 9, a turn-on signal may be supplied to the reset switch SRST during the initialization period Tinit. Referring to FIG. 10, during the initialization period (Tinit), a reset signal (RST), which is a turn-on signal, may be applied to the reset switch (SRST), and accordingly, the inverting terminal (-) and the output terminal (Vout_C) may be electrically connected to each other. It can be connected to . That is, the common operational amplifier circuit (CAB) may be an operational amplifier circuit that functions as a unit gain buffer with a gain of 1.

Referring to FIG. 10, since the common operational amplifier circuit (CAB) is composed of a circuit with a buffer circuit function, the sensing driving data voltage (Vref-Vsen) supplied to the non-inverting terminal (+) is connected to the inverting terminal (-). can be supplied. The sensing driving data voltage (Vref-Vsen) supplied to the inverting terminal (-) may be supplied to the common line (CL) through the common channel (CCH).

A sensing signal (SENSE) for switching the sensing transistor (SENT) to the turn-on state may be supplied to the gate node of the sensing transistor (SENT).

That is, since the sensing transistor (SENT) can be switched to the turn-on state, the sensing driving data voltage (Vref-Vsen) can be supplied to the second node (N2) of the driving transistor (DRT).

In other words, the reference voltage (Vref) can be supplied to the first node (N1), which is the gate node of the driving transistor (DRT), and the data voltage (Vref-Vsen) for sensing driving can be supplied to the second node (N2). there is. It may be a sensing data voltage (Vsen).

Referring to FIG. 9, the tracking period (Ttrack) is the driving transistor (DRT) until the voltage (V2) of the second node (N2) of the driving transistor (DRT) reflects the characteristic value or change in characteristic value of the driving transistor (DRT). ) may be a period of boosting the voltage (V2) of the second node (N2).

During the tracking period (Ttrack), the first node (N1) of the driving transistor (DRT) is in a constant voltage state with the reference voltage (Vref), but the voltage (V2) of the second node (N2) of the driving transistor (DRT) increases. If you do this, you may become saturated.

Referring to FIG. 9, in order to control the second node (N2) to a floating state during the tracking period (Ttrack), the first connection switch (CST1) to the third connection switch (CST3) can be controlled as follows. there is.

Referring to FIG. 9, a turn-on signal may be supplied to the first connection switch CST1 during the tracking period Ttrack. Referring to FIG. 11 , a first connection control signal (CCS1) for forming a voltage or current path may be supplied to the first connection switch (CST1). Accordingly, the non-inverting terminal (+) of the operational amplifier (AMP_C) may be electrically connected to the common driving circuit unit (CDB) through the first input line (IL1).

Referring to FIG. 9, a turn-off signal may be supplied to the second connection switch CST2 during the tracking period Ttrack. Referring to FIG. 11, a second connection control signal (CCS2) for forming a voltage or current path may be supplied to the second connection switch (CST2). Accordingly, the inverting terminal (-) of the operational amplifier (AMP_C) may be electrically connected to the common channel (CCH) through the second input line (IL2).

Referring to FIG. 9, a turn-off signal may be supplied to the third connection switch CST3 during the tracking period Ttrack. Referring to FIG. 11, a third connection control signal (CCS3) for blocking voltage or current may be supplied to the third connection switch (CST3). Accordingly, current may not flow and voltage may not be supplied to the third input line IL3.

Referring to FIG. 11 , during the tracking period Ttrack, as voltage is not supplied to the common line CL, the second node N2 of the driving transistor DRT may be floating. Embodiments in which voltage is not supplied to the common line CL may vary. For example, referring to FIG. 11, as a turn-off signal is supplied to the second connection switch (CST2) and the third connection switch (CST3), the second connection switch (CST2) and the third connection switch (CST3) becomes open and the second node N2 may be floating. As another example, voltage supply may be stopped through a digital-to-analog converter (DAC). As another example, as the turn-off signal is supplied to the first connection switch (CST1), the voltage supplied from the digital-to-analog converter (DAC) may not be supplied through the first input line (IL1). That is, there is no limit to the method for controlling the second node N2 to a floating state.

As the second node N2 becomes floating, the voltage V2 of the second node N2 of the driving transistor DRT increases. The voltage (V2) of the second node (N2) of the driving transistor (DRT) does not continue to rise, but increases, and then the amount of increase decreases, eventually reaching saturation.

Referring to FIG. 9, the sensing period Tsen may be a period for sensing the characteristic value of the driving transistor DRT.

During the sensing period (Tsen), an analog-to-digital converter (ADC) may sense the voltage of the common line (CL). Here, the voltage of the common line CL may correspond to the voltage V2 of the second node N2 of the driving transistor DRT, and may correspond to the charging voltage of the line capacitor Ccl formed in the common line CL. It can be.

Referring to FIG. 9 , in order to sense the characteristic value of the driving transistor DRT during the sensing period Tsen, the first to third connection switches CST1 to CST3 may be controlled as follows.

Referring to FIG. 9, a turn-off signal may be supplied to the first connection switch CST1 during the sensing period Tsen. Referring to FIG. 12, a first connection control signal (CCS1) for blocking voltage or current may be supplied to the first connection switch (CST1). Accordingly, the non-inverting terminal (+) of the operational amplifier (AMP_C) may not be electrically connected to the common driving circuit unit (CDB) through the first input line (IL1).

Referring to FIG. 9 , a turn-off signal may be supplied to the second connection switch CST2 during the sensing period Tsen. Referring to FIG. 12, a second connection control signal (CCS2) for forming a voltage or current path may be supplied to the second connection switch (CST2). Accordingly, current may not flow and voltage may not be supplied to the second input line IL2.

Referring to FIG. 9, a turn-on signal may be supplied to the third connection switch CST3 during the sensing period Tsen. Referring to FIG. 12, a third connection control signal (CCS3) for forming a voltage or current path may be supplied to the third connection switch (CST3). Accordingly, the inverting terminal (+) of the operational amplifier (AMP_C) may be electrically connected to the common channel (CCH) through the third input line (IL3).

Since the common channel (CCH) and the inverting terminal (+) of the operational amplifier (AMP_C) are electrically connected, the voltage or current of the common line (CL) can be supplied to the inverting terminal (+) of the operational amplifier (AMP_C). . A reset signal (RST) may be applied to the reset switch (SRST), and accordingly, the inverting terminal (-) and the output terminal (Vout_C) may be electrically connected. That is, the common operational amplifier circuit (CAB) may be an operational amplifier circuit that functions as a unit gain buffer with a gain of 1. Since the common operational amplifier circuit (CAB) is composed of a circuit with a buffer circuit function, the voltage supplied to the non-inverting terminal (+) can be supplied to the inverting terminal (-). The voltage supplied to the inverting terminal (-) may be supplied to the common sensing circuit section (CSB) through the output line (OL).

That is, during the sensing period (Tsen), an analog-to-digital converter (ADC) may sense the voltage of the common line (CL).

The tracking period (Ttrack) may last long enough for the second node (N2) to be saturated. In this case, the voltage (V2) of the second node (N2) is the difference between the sensing data voltage (Vsen) and the threshold voltage (Vth) (Vsen-Vth) or the difference between the sensing data voltage (Vsen) and the threshold voltage deviation (ΔVth) It may correspond to (Vsen-ΔVth). The voltage of the second node N2 may be converted into a sensing voltage, which is a digital value, by an analog-to-digital converter (ADC). Thereafter, the controller 140 may determine the threshold voltage (Vth) characteristic value of the driving transistor (DRT) based on the sensing voltage converted to a digital value.

Meanwhile, the tracking period (Ttrack) may be short enough to prevent the second node (N2) from being saturated. In this case, the mobility characteristic value of the driving transistor DRT can be determined based on the voltage V2 of the second node N2 and the duration of the tracking period Ttrack. The voltage of the second node N2 may be converted into a sensing voltage, which is a digital value, by an analog-to-digital converter (ADC). Thereafter, the controller 140 may determine the mobility characteristic value of the driving transistor (DRT) based on the sensing voltage converted to a digital value.

FIG. 13 is a flowchart of a current-based sensing method of the display device 100 according to embodiments of the present disclosure. FIG. 14 is a timing diagram of a current-based sensing method of the display device 100 according to embodiments of the present disclosure. 15 to 17 are circuit diagrams related to a current-based sensing method of the display device 100 according to embodiments of the present disclosure.

Below, the sensing method of the display device 100 will be briefly described with reference to FIG. 13 and then the sensing method of the display device 100 will be described in detail with reference to FIGS. 14 to 17.

Referring to FIG. 13, the sensing method of the display device 100 may include a voltage initialization step (S1310), a voltage tracking step (S1320), and a voltage sensing step (S1330).

The voltage initialization step (S1310) may be a step in which voltage is controlled to drive a current-based sensing method. In the initialization step (S1310), the reference voltage (Vref) supplied to the reference voltage line (RVL) is supplied to the first node (N1), which is the gate node of the driving transistor (DRT), and the sensing signal supplied to the common line (CL) This may be a stage in which the driving data voltage (Vref-Vsen) is supplied to the second node (N2) of the driving transistor. In the initialization step (S1310), both ends of the feedback capacitor Cfb are electrically connected, so that the feedback capacitor Cfb can be initialized.

The voltage tracking step (S1320) may be a step in which the voltage of the output terminal (Vout_C) changes as the driving current (Id) flows through the driving transistor (DRT). In the voltage tracking step (S1320), the common operational amplifier circuit (CAB) may be configured as a circuit that performs the function of a current integrator under the control of the reset switch (SRST). As the common operational amplifier circuit (CAB) performs the function of a current integrator, when the driving current (Id) is supplied to the common operational amplifier circuit (CAB), the voltage at the output terminal (Vout_C) decreases. Therefore, the voltage magnitude may change.

The voltage sensing step (S1330) may be a step in which a turn-on signal is supplied to the sampling switch (SAM) and the voltage of the output terminal (Vout_C) is sensed. The voltage of the output terminal (Vout_C) may be reduced during the voltage tracking step (S1320), and the voltage of the output terminal (Vout_C) may be reduced from the data voltage for sensing driving (Vref-Vsen) to the output terminal sensing voltage (Vo_sen). there is.

Referring to FIG. 14, the sensing driving period may include a voltage initialization period (Ti), a voltage tracking period (Tt), and a voltage sensing period (Ts), respectively. The voltage initialization period (Ti) corresponds to the voltage initialization step (S1310), the voltage tracking period (Tt) corresponds to the voltage tracking step (S1320), and the voltage sensing period (Ts) corresponds to the voltage sensing step (S1330). You can.

Referring to FIG. 14, the voltage initialization period Ti may be a period for initializing the first node N1 and the second node N2 of the driving transistor DRT. During the voltage initialization period (Ti), the scan transistor (SCT) and the sensing transistor (SENT) may be turned on.

During the voltage initialization period Ti, the voltage V1 of the first node N1 of the driving transistor DRT may be initialized to the reference voltage Vref, and the voltage V1 of the second node N2 of the driving transistor DRT may be initialized to the reference voltage Vref. The voltage V2 may be initialized to the data voltage (Vref-Vsen) for sensing driving.

Referring to FIG. 14, in order to supply data voltages (Vref-Vsen) for sensing driving during the voltage initialization period (Ti), the first connection switch (CST1) to the third connection switch (CST3) may be controlled as follows. .

Referring to FIG. 14, during the voltage initialization period Ti, a turn-on signal may be supplied to the first connection switch CST1. Referring to FIG. 15, a first connection control signal (CCS1) for forming a voltage or current path may be supplied to the first connection switch (CST1). Accordingly, the non-inverting terminal (+) of the operational amplifier (AMP_C) may be electrically connected to the common driving circuit unit (CDB) through the first input line (IL1).

Referring to FIG. 14, during the voltage initialization period Ti, a turn-on signal may be supplied to the second connection switch CST2. Referring to FIG. 15, a second connection control signal (CCS2) for forming a voltage or current path may be supplied to the second connection switch (CST2). Accordingly, the inverting terminal (-) of the operational amplifier (AMP_C) may be electrically connected to the common channel (CCH) through the second input line (IL2).

Referring to FIG. 14, during the voltage initialization period Ti, a turn-off signal may be supplied to the third connection switch CST3. Referring to FIG. 15, a third connection control signal (CCS3) for blocking voltage or current may be supplied to the third connection switch (CST3). Accordingly, current may not flow and voltage may not be supplied to the third input line IL3.

Referring to FIG. 15, the reference voltage Vref may be supplied to the reference voltage line RVL through the reference voltage channel VCH. The reference voltage (Vref) may be a voltage of a certain magnitude.

A scan signal (SCAN) for switching the scan transistor (SCT) to the turn-on state may be supplied to the gate node of the scan transistor (SCT).

That is, since the scan transistor (SCT) can be switched to the turn-on state, the reference voltage (Vref) can be supplied to the first node (N1), which is the gate node of the driving transistor (DRT).

The data voltage (Vref-Vsen) for sensing driving may be output from the common driving circuit (CDB) and supplied to the non-inverting terminal (+). That is, the common driving circuit unit (CDB) can supply the sensing driving data voltage (Vref-Vsen) to the non-inverting terminal (+).

Meanwhile, referring to FIG. 14, a turn-on signal may be supplied to the reset switch SRST during the voltage initialization period Ti. Referring to FIG. 15, during the voltage initialization period Ti, a reset signal RST may be applied to the reset switch SRST, and the inverting terminal (-) and the output terminal (Vout_C) may be electrically connected accordingly. . That is, the common operational amplifier circuit (CAB) may be an operational amplifier circuit that functions as a unit gain buffer with a gain of 1.

Referring to FIG. 15, since the common operational amplifier circuit (CAB) is composed of a circuit with a buffer circuit function, the sensing driving data voltage (Vref-Vsen) supplied to the non-inverting terminal (+) is connected to the inverting terminal (-). can be supplied. The sensing driving data voltage (Vref-Vsen) supplied to the inverting terminal (-) may be supplied to the common line (CL) through the common channel (CCH).

A sensing signal (SENSE) for switching the sensing transistor (SENT) to the turn-on state may be supplied to the gate node of the sensing transistor (SENT).

That is, since the sensing transistor (SENT) can be switched to the turn-on state, the sensing driving data voltage (Vref-Vsen) can be supplied to the second node (N2) of the driving transistor (DRT).

In other words, the reference voltage (Vref) can be supplied to the first node (N1), which is the gate node of the driving transistor (DRT), and the data voltage (Vref-Vsen) for sensing driving can be supplied to the second node (N2). there is. It may be a sensing data voltage (Vsen).

Referring to FIG. 15, during the voltage initialization period (Ti), a reset signal (RST), which is a turn-on signal, may be applied to the reset switch (SRST), and accordingly, the inverting terminal (-) and the output terminal (Vout_C) Can be electrically connected. That is, the voltage of the inverting terminal (-) and the output terminal (Vout_C) can be the same. The feedback capacitor (Cfb) is electrically connected between the inverting terminal (-) and the output terminal (Vout_C). As the inverting terminal (-) and the output terminal (Vout_C) are electrically connected, the voltage difference between both ends of the feedback capacitor (Cfb) can be 0. That is, the feedback capacitor Cfb can be initialized.

Referring to FIG. 14, the voltage tracking period (Tt) may be a period in which the voltage of the output terminal (Vout_C) changes as the driving current (Id) flows through the driving transistor (DRT).

Referring to FIG. 14, the control state of the first to third connection switches CST1 to CST3 may be maintained in the voltage initialization period Ti until the voltage tracking period Tt.

The first connection switch (CST1) to the third connection switch (CST3) may be controlled so that the common operational amplifier circuit (CAB) is configured as a current integrator. As the turn-on signal is supplied to the first connection switch (CST1), the digital-to-analog converter (DAC) may be electrically connected to the non-inverting terminal (+) of the operational amplifier (AMP_C). As the turn-on signal is supplied to the second connection switch (CST2), the common line (CL) and the inverting terminal (-) of the operational amplifier (AMP_C) may be electrically connected. As the turn-off signal is supplied to the second connection switch CST2, the common line CL and the non-inverting terminal (+) of the operational amplifier AMP_C may not be electrically connected.

Referring to FIG. 16, during the voltage tracking period (Tt), a reset signal (RST), which is a turn-off signal, may be applied to the reset switch (SRST), and accordingly, the inverting terminal (-) and the output terminal (Vout_C) It may be electrically disconnected. At this time, the common operational amplifier circuit (CAB) may be a circuit that performs the function of a current integrator.

The driving current (Id) flowing through the driving transistor (DRT) may be supplied to the common operational amplifier circuit (CAB) through the common line (CL). The driving current (Id) may be supplied to the inverting terminal (-) of the operational amplifier (AMP_C). The common operational amplifier circuit (CAB) can receive current through the inverting terminal (-) of the operational amplifier (AMP_C), and as current is supplied, the voltage at the output node (Vout_C) changes from a predetermined voltage to a voltage that increases over time. This may decrease and change.

Referring to FIG. 14, during the voltage tracking period (Tt), the voltage of the output terminal (Vout_C) may be reduced from the sensing driving data voltage (Vref-Vsen) to the output terminal sensing voltage (Vo_sen). The size of the output terminal sensing voltage (Vo_sen) may vary depending on the device characteristics of the driving transistor (DRT).

Referring to FIG. 14, the voltage sensing period (Ts) may be a period in which the voltage of the output terminal (Vout_C) is sensed.

During the voltage sensing period (Ts), an analog-to-digital converter (ADC) may sense the voltage of the common line (CL). Here, the voltage of the common line CL may correspond to the voltage V2 of the second node N2 of the driving transistor DRT, and may correspond to the charging voltage of the line capacitor Ccl formed in the common line CL. It can be.

During the voltage sensing period (Ts), a turn-on signal may be supplied to the sampling switch (SAM). As the turn-on signal is supplied to the sampling switch (SAM), the voltage of the output terminal (Vout_C) can be supplied to the analog-to-digital converter (ADC). When a turn-on signal is supplied to the sampling switch (SAM) and the voltage at the output terminal (Vout_C) is supplied to the analog-to-digital converter (ADC), it can be called “voltage sensing.”

The voltage of the output terminal (Vout_C) can be converted into a sensing voltage, which is a digital value, by an analog-to-digital converter (ADC). Thereafter, the controller 140 may determine the characteristic value of the driving transistor (DRT) based on the sensing voltage converted to a digital value.

The principle of the above-described current-based sensing method will be explained through FIGS. 13 to 17.

During the voltage initialization period Ti, the multiple subpixels SP are all initialized to the same voltage. The voltage V1 of the first node N1 of the driving transistor DRT may be initialized to the reference voltage Vref, and the voltage V2 of the second node N2 of the driving transistor DRT may be used for sensing driving. It can be initialized with the data voltage (Vref-Vsen).

If the characteristic values of all driving transistors (DRT) are the same, the same driving current (Id) flows through the driving transistors (DRT). However, the characteristic values of the driving transistor (DRT) included in each of the plurality of subpixels (SP) may vary depending on device manufacturing process errors, device driving time, etc. Therefore, even if multiple subpixels (SP) are initialized to the same voltage, the size of the driving current (Id) is different depending on the characteristics of the device. That is, since the driving current (Id) flowing for a predetermined time will be different, the voltage level of the output terminal (Vout_C) that changes during the voltage tracking period (Tt) will be different.

The characteristic value of the driving transistor (DRT) can be determined based on the voltage level of the output terminal (Vout_C) that changes compared to a predetermined time. This can be called a current-based sensing method.

According to the embodiments of the present disclosure described above, a data driving circuit, a display device, an image driving method, and a sensing method having a compact circuit structure can be provided.

According to embodiments of the present disclosure, a display device capable of low power consumption by configuring a circuit structure compactly, an image driving method thereof, and a sensing method can be provided.

The embodiments of the present disclosure described above are briefly described as follows.

According to embodiments of the present disclosure, a display panel 110 on which a plurality of subpixels SP is disposed; and a data driving circuit 120 that supplies a data voltage to the plurality of subpixels (SP), wherein the function of the operational amplifier circuit including an operational amplifier (AMP_C) is to signal a reset signal. Common operational amplifier circuitry (CAB) changed by (RST); a common sensing circuit unit (CSB) electrically connected to the output terminal (Vout_C) of the operational amplifier (AMP_C) included in the common operational amplifier circuit unit (CAB) through an output line (OL) and for sensing a voltage; and a display device 100 electrically connected to the non-inverting terminal (+) of the operational amplifier (AMP_C) through a first input line (IL1) and including a common driving circuit (CDB) for supplying a voltage. can do.

The common operational amplifier circuit unit (CAB) has an inverting terminal (-) electrically connected to the first input line (IL1) and a second input line (IL2) that is different from the first input line (IL1). an operational amplifier (AMP_C) including the non-inverting terminal (+) and the output terminal (Vout_C) electrically connected to the output line (OL); a feedback capacitor (Cfb) electrically connected between the second input line (IL2) and the output line (OL); and a reset switch (SRST) electrically connected between the second input line (IL2) and the output line (OL).

The reset switch (SRST) may be controlled by the reset signal (RST).

The common driving circuit unit (CDB) includes a shift register unit (SR) that sequentially outputs latch pulses to a plurality of latches included in the latch unit (Latch); The latch unit sequentially stores input data in response to the latch pulse; And it may include a digital-to-analog converter (DAC) that converts the input data output from the latch into an analog voltage.

The common sensing circuit unit (CSB) includes a sample and hold circuit (S/H) that samples and holds the sensing voltage output from the common operational amplifier circuit unit (CAB); A scaler that adjusts the size of the sampling value, which is the sampled sensing voltage, within the operating range of an analog-to-digital converter (ADC); And it may include the analog-to-digital converter (ADC) that converts the size-adjusted sampling value from the scaler into a digital format.

The data driving circuit 120 includes a common channel (CCH) electrically connected to a second input line (IL2) different from the first input line (IL1); and a reference voltage channel (VCH), which is a different channel from the common channel (CCH) and outputs a reference voltage (Vref).

The display panel 110 includes a plurality of common lines CL; Multiple reference voltage lines (RVL); and a plurality of sub-pixels (SP) electrically connected to the plurality of common lines (CL) and the plurality of reference voltage lines (RVL), wherein the plurality of sub-pixels (SP) are connected to a first common line ( CL) and a first subpixel (SP) electrically connected to a first reference voltage line (RVL), the first common line (CL) is electrically connected to the common channel (CCH), and the first The reference voltage line (RVL) may be electrically connected to the reference voltage channel (VCH).

Each of the plurality of subpixels (SP) includes a driving transistor (DRT) for driving a light emitting device; a scan transistor (SCT) electrically connected between the reference voltage line (RVL) and a first node (N1), which is a gate node of the driving transistor (DRT); a sensing transistor (SENT) electrically connected between the common line (CL) and a second node (N2) of the driving transistor (DRT); and a storage capacitor (Cst) electrically connected between the first node (N1) and the second node (N2).

According to embodiments of the present disclosure, the reference voltage Vref supplied to the reference voltage line RVL is supplied to the first node N1, which is the gate node of the driving transistor DRT, and is supplied to the common line CL. A first step (S610) in which the image driving data voltage (Vref-Vdata) is supplied to the second node (N2) of the driving transistor (DRT); A second step (S620) in which the first node (N1) and the second node (N2) are floated; and a third step (S630) in which the light emitting element driven by the driving transistor (DRT) emits light, and a data driving circuit that supplies the reference voltage (Vref) and the image driving data voltage (Vref-Vdata). 120 is a common operational amplifier circuit section (CAB) in which the function of the operational amplifier circuit including the operational amplifier (AMP_C) is changed by the reset signal (RST); a common sensing circuit unit (CSB) electrically connected to the output terminal (Vout_C) of the operational amplifier (AMP_C) included in the common operational amplifier circuit unit (CAB) through an output line (OL) and for sensing a voltage; and a common driving circuit unit (CDB) electrically connected to the non-inverting terminal (+) of the operational amplifier (AMP_C) through a first input line (IL1) and for supplying a voltage, wherein the first step (S610) ), the common driving circuit unit (CDB) supplies the image driving data voltage (Vref-Vdata) to the non-inverting terminal (+), and the image driving data voltage (Vref-Vdata) is supplied to the operational amplifier ( A method of driving an image of the display device 100 supplied to the common line CL through the second input line IL2 electrically connected to the inverting terminal (-) of AMP_C) can be provided.

According to embodiments of the present disclosure, the reference voltage Vref supplied to the reference voltage line RVL is supplied to the first node N1, which is the gate node of the driving transistor DRT, and is supplied to the common line CL. An initialization step (S810) in which the sensing driving data voltage (Vref-Vsen) is supplied to the second node (N2) of the driving transistor (DRT); A tracking step (S820) in which the second node (N2) is floating and the voltage (V2) of the second node (N2) is increased; And a sensing step (S830) in which an analog-to-digital converter and the common line (CL) are electrically connected, and the analog-to-digital converter senses the voltage of the common line (CL), wherein the reference voltage (Vref) and the The data driving circuit 120 that supplies the data voltage (Vref-Vsen) for sensing driving is a common operational amplifier circuit (CAB) in which the function of the operational amplifier circuit including the operational amplifier (AMP_C) is changed by the reset signal (RST). ); a common sensing circuit unit (CSB) electrically connected to the output terminal (Vout_C) of the operational amplifier (AMP_C) included in the common operational amplifier circuit unit (CAB) through an output line (OL) and for sensing a voltage; and a common driving circuit unit (CDB) electrically connected to the non-inverting terminal (+) of the operational amplifier (AMP_C) through a first input line (IL1) and for supplying a voltage, and in the initialization step (S810) In, the common driving circuit unit (CDB) supplies the sensing driving data voltage (Vref-Vsen) to the non-inverting terminal (+), and the sensing driving data voltage (Vref-Vsen) is supplied to the common operational amplifier circuit unit. It is supplied to the common line (CL) through a second input line (IL2) electrically connected to the inverting terminal (-) of the operational amplifier (AMP_C) included in (CAB), and in the sensing step (S830), the The common sensing circuit unit (CSB) can provide a sensing method for the display device 100 to sense the voltage of the common line (CL).

According to embodiments of the present disclosure, a common operational amplifier circuit unit (CAB) in which the function of an operational amplifier circuit including an operational amplifier (AMP_C) is changed by a reset signal (RST); a common sensing circuit unit (CSB) electrically connected to the output terminal (Vout_C) of the operational amplifier (AMP_C) included in the common operational amplifier circuit unit (CAB) through an output line (OL) and for sensing a voltage; and a common driving circuit (CDB) electrically connected to the non-inverting terminal (+) of the operational amplifier (AMP_C) included in the common operational amplifier circuit (CAB) through the first input line (IL1), and for supplying a voltage. ) can be provided.

The common operational amplifier circuit unit (CAB) has an inverting terminal (-) electrically connected to the first input line (IL1) and a second input line (IL2) that is different from the first input line (IL1). an operational amplifier (AMP_C) including the non-inverting terminal (+) and the output terminal (Vout_C) electrically connected to the output line (OL); a feedback capacitor (Cfb) electrically connected between the second input line (IL2) and the output line (OL); and a reset switch (SRST) electrically connected between the second input line (IL2) and the output line (OL).

The data driving circuit 120 includes a common channel (CCH) electrically connected to the second input line (IL2); It is a different channel from the common channel (CCH) and may include a reference voltage channel (VCH) through which a reference voltage (Vref) is output.

According to embodiments of the present disclosure, the reference voltage supplied to the reference voltage line is supplied to the first node, which is the gate node of the driving transistor, and the sensing driving data voltage supplied to the common line is supplied to the second node of the driving transistor. A supply voltage initialization step, a voltage tracking step in which the voltage of the output terminal of the operational amplifier that receives current through the common line changes, and an analog-to-digital converter and the common line are electrically connected, and the analog-to-digital converter is electrically connected to the common line. A data driving circuit comprising a voltage sensing step of sensing the voltage of a common line, and supplying the reference voltage and the data voltage for the sensing drive, wherein the function of the operational amplifier circuit including the operational amplifier is changed by a reset signal. A common operational amplifier circuit unit, electrically connected to the output terminal of the operational amplifier included in the common operational amplifier circuit unit through an output line, a common sensing circuit unit for sensing a voltage, and a non-inverting terminal and a first input of the operational amplifier It is electrically connected through a line and includes a common driving circuit for supplying a voltage, and in the voltage initialization step, the common driving circuit supplies the data voltage for the sensing drive to the non-inverting terminal, and The data voltage is supplied to the common line through a second input line electrically connected to the inverting terminal of the operational amplifier included in the common operational amplifier circuit unit, and in the voltage sensing step, the common sensing circuit unit determines the voltage of the common line. A sensing method of a display device that senses can be provided.

The above description is merely an illustrative explanation of the technical idea of the present disclosure, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in this disclosure are not intended to limit the technical idea of the present disclosure, but rather to explain them, and therefore the scope of the technical idea of the present disclosure is not limited by these embodiments.

100: display device
110: display panel
120: data driving circuit
130: Gate driving circuit
140: controller

Claims (14)

A display panel on which a plurality of subpixels are arranged; and
It includes a data driving circuit that supplies data voltage to the plurality of subpixels,
The data driving circuit is,
a common operational amplifier circuit unit in which the function of an operational amplifier circuit including an operational amplifier is changed by a reset signal;
a common sensing circuit unit electrically connected to an output terminal of the operational amplifier included in the common operational amplifier circuit unit through an output line, and configured to sense a voltage; and
A display device electrically connected to a non-inverting terminal of the operational amplifier through a first input line and including a common driving circuit for supplying a voltage.
According to paragraph 1,
The common operational amplifier circuit unit,
An operational amplifier including an inverting terminal electrically connected to the first input line, the non-inverting terminal electrically connected to a second input line different from the first input line, and the output terminal electrically connected to the output line. ;
a feedback capacitor electrically connected between the second input line and the output line; and
A display device including a reset switch electrically connected between the second input line and the output line.
According to paragraph 2,
A display device wherein the reset switch is controlled by the reset signal.
According to paragraph 1,
The common driving circuit unit,
a shift register unit sequentially outputting latch pulses to a plurality of latches included in the latch unit;
the latch unit sequentially storing input data in response to the latch pulse; and
A display device comprising a digital-to-analog converter that converts the input data output from the latch unit into an analog voltage.
According to paragraph 1,
The common sensing circuit unit,
Sample and hold for sampling and holding the sensing voltage output from the common operational amplifier circuit unit;
A scaler that adjusts the size of the sampling value, which is the sampled sensing voltage, within the operating range of the analog-to-digital converter; and
A display device comprising the analog-to-digital converter that converts the size-adjusted sampling value from the scaler into a digital format.
According to paragraph 1,
The data driving circuit is,
a common channel electrically connected to the first input line and another second input line; and
A display device including a reference voltage channel that is different from the common channel and outputs a reference voltage.
According to clause 6,
The display panel is,
Multiple common lines;
Multiple reference voltage lines; and
It includes the plurality of subpixels electrically connected to the plurality of common lines and the plurality of reference voltage lines,
The plurality of subpixels include a first subpixel electrically connected to a first common line and a first reference voltage line,
A first common line is electrically connected to the common channel,
The first reference voltage line is electrically connected to the reference voltage channel.
In clause 7,
Each of the plurality of subpixels,
A driving transistor for driving a light emitting device;
a scan transistor electrically connected between the reference voltage line and a first node that is the gate node of the driving transistor;
a sensing transistor electrically connected between the common line and a second node of the driving transistor; and
A display device including a storage capacitor electrically connected between the first node and the second node.
A first step in which the reference voltage supplied to the reference voltage line is supplied to the first node, which is the gate node of the driving transistor, and the image driving data voltage supplied to the common line is supplied to the second node of the driving transistor;
A second step in which the first node and the second node are floated; and
A third step in which the light emitting element driven by the driving transistor emits light,
The data driving circuit that supplies the reference voltage and the image driving data voltage,
A common operational amplifier circuit unit in which the function of an operational amplifier circuit including an operational amplifier is changed by a reset signal;
a common sensing circuit unit electrically connected to an output terminal of the operational amplifier included in the common operational amplifier circuit unit through an output line, and configured to sense a voltage; and
It is electrically connected to the non-inverting terminal of the operational amplifier through a first input line and includes a common driving circuit for supplying a voltage,
In the first step,
The common driving circuit unit supplies the image driving data voltage to the non-inverting terminal, and the image driving data voltage is supplied to the common line through a second input line electrically connected to the inverting terminal of the operational amplifier. How to drive video on a device.
An initialization step in which the reference voltage supplied to the reference voltage line is supplied to the first node, which is the gate node of the driving transistor, and the sensing driving data voltage supplied to the common line is supplied to the second node of the driving transistor;
A tracking step in which the second node floats and the voltage of the second node increases; and
An analog-to-digital converter and the common line are electrically connected, and a sensing step in which the analog-to-digital converter senses the voltage of the common line,
The data driving circuit that supplies the reference voltage and the data voltage for sensing driving,
a common operational amplifier circuit unit in which the function of an operational amplifier circuit including an operational amplifier is changed by a reset signal;
a common sensing circuit unit electrically connected to an output terminal of the operational amplifier included in the common operational amplifier circuit unit through an output line, and configured to sense a voltage; and
It is electrically connected to the non-inverting terminal of the operational amplifier through a first input line and includes a common driving circuit for supplying a voltage,
In the initialization step,
The common driving circuit unit supplies the sensing driving data voltage to the non-inverting terminal, and the sensing driving data voltage is supplied through a second input line electrically connected to the inverting terminal of the operational amplifier included in the common operational amplifier circuit part. It is supplied to the common line through,
In the sensing step,
A sensing method for a display device in which the common sensing circuit unit senses the voltage of the common line.
a common operational amplifier circuit unit in which the function of an operational amplifier circuit including an operational amplifier is changed by a reset signal;
a common sensing circuit unit electrically connected to an output terminal of the operational amplifier included in the common operational amplifier circuit unit through an output line, and configured to sense a voltage; and
A data driving circuit electrically connected to a non-inverting terminal of the operational amplifier included in the common operational amplifier circuit unit through a first input line, and including a common driving circuit unit for supplying a voltage.
According to clause 11,
The common operational amplifier circuit unit,
An operational amplifier including an inverting terminal electrically connected to the first input line, the non-inverting terminal electrically connected to a second input line different from the first input line, and the output terminal electrically connected to the output line. ;
a feedback capacitor electrically connected between the second input line and the output line; and
A data driving circuit including a reset switch electrically connected between the second input line and the output line.
According to clause 12,
a common channel electrically connected to the second input line;
A data driving circuit that is different from the common channel and includes a reference voltage channel through which a reference voltage is output.
A voltage initialization step in which the reference voltage supplied to the reference voltage line is supplied to a first node, which is the gate node of the driving transistor, and the sensing driving data voltage supplied to the common line is supplied to the second node of the driving transistor;
A voltage tracking step in which the voltage of the output terminal of the operational amplifier that receives current through the common line changes; and
An analog-to-digital converter and the common line are electrically connected, and the analog-to-digital converter includes a voltage sensing step of sensing the voltage of the common line,
The data driving circuit that supplies the reference voltage and the data voltage for sensing driving,
a common operational amplifier circuit unit in which the function of the operational amplifier circuit including the operational amplifier is changed by a reset signal;
a common sensing circuit unit electrically connected to an output terminal of the operational amplifier included in the common operational amplifier circuit unit through an output line, and configured to sense a voltage; and
It is electrically connected to the non-inverting terminal of the operational amplifier through a first input line and includes a common driving circuit for supplying a voltage,
In the voltage initialization step,
The common driving circuit unit supplies the sensing driving data voltage to the non-inverting terminal, and the sensing driving data voltage is supplied through a second input line electrically connected to the inverting terminal of the operational amplifier included in the common operational amplifier circuit part. It is supplied to the common line through,
In the voltage sensing step,
A sensing method for a display device in which the common sensing circuit unit senses the voltage of the common line.

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