KR20240102568A - Display panel and display device including the same - Google Patents

Abstract

A display panel and a display device including the same are disclosed. The pixel circuit includes a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node; a light emitting device including an anode electrode connected to a fifth node, and a cathode electrode to which a pixel base voltage is applied; a first switch element connected between the first node and the fourth node; a second switch element connected between the third node and the fourth node; a third switch element connected between the first node and the second node; and a fourth switch element connected between the third node and the fifth node.

Description

Display panel and display device including the same {DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a display panel and a display device including the same.

Organic light emitting display devices include organic light emitting diodes (hereinafter referred to as “OLEDs”) that emit light on their own, and have the advantages of fast response speed, high luminous efficiency, brightness, and viewing angle. Organic light emitting display devices not only have a fast response speed and excellent luminous efficiency, brightness, and viewing angle, but also have excellent contrast ratio and color gamut because they can express black gradations in complete black.

Organic light emitting display devices do not require a backlight unit and can be implemented on flexible materials such as plastic substrates, thin glass substrates, and metal substrates. Therefore, the flexible display can be implemented as an organic light emitting display device.

Pixels of an organic light emitting display device include a pixel circuit including a driving element for driving an OLED and a capacitor connected to the driving element.

There may be differences in the electrical characteristics of driving elements between pixels due to process deviations and element characteristic deviations resulting from the display panel manufacturing process. This difference may become larger as the driving time of the pixels passes. To compensate for differences in electrical characteristics of driving elements between pixels, an internal compensation circuit may be added to the pixel circuit. The internal compensation circuit may sample the threshold voltage of the driving element and compensate the gate voltage of the driving element by the threshold voltage of the driving element.

The driving element for driving the light emitting element can be implemented with an oxide TFT (Thin Film Transistor) containing an oxide semiconductor. Oxide TFT has the advantage of low leakage current due to low off-current, but has low current capacity due to low mobility. By connecting the back gate electrode of a driving device implemented as an oxide TFT to the source electrode, the driving device can be manufactured as a TFT with a double gate structure. In this case, it is advantageous for low grayscale expression by increasing the subthreshold slope characteristic, but it has the disadvantage of having a small on-current. Because of this, when sampling the threshold voltage of the driving element in the internal compensation circuit, the sampling margin becomes insufficient.

The present invention aims to solve the above-described needs and/or problems.

The present invention provides a display panel that can improve on-current characteristics and low gray level expression when sampling the threshold voltage of a driving element, and a display device including the same.

The problem of the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A pixel circuit according to an embodiment of the present invention includes a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node. Drive elements including; a light emitting device including an anode electrode connected to a fifth node, and a cathode electrode to which a pixel base voltage is applied; a first switch element connected between the first node and the fourth node; a second switch element connected between the third node and the fourth node; a third switch element connected between the first node and the second node; and a fourth switch element connected between the third node and the fifth node.

The pixel circuit includes a capacitor connected between the second node and the fifth node; a fifth switch element connected between the fifth node and a third constant voltage node to which an initialization voltage is applied; a sixth switch element connected between a data line to which a data voltage is applied and the third node; And it may further include a first constant voltage node to which a pixel driving voltage is applied, and a seventh switch element connected between the first node.

The first switch element may include a first electrode connected to the first node, a gate electrode connected to a first gate line to which a first gate signal is applied, and a second electrode connected to the fourth node. The second switch element may include a first electrode connected to the third node, a gate electrode connected to a second gate line to which a second gate signal is applied, and a second electrode connected to the fourth node. The third switch element may include a first electrode connected to the second node, a gate electrode connected to the first gate line, and a second electrode connected to the first node. The fourth switch element may include a first electrode connected to the third node, a gate electrode connected to the second gate line, and a second electrode connected to the fifth node. The fifth switch element may include a first electrode connected to the fifth node, a gate electrode connected to the first gate line, and a second electrode connected to the third constant voltage node. The sixth switch element may include a first electrode connected to the data line, a gate electrode connected to a third gate line to which a third gate signal is applied, and a second electrode connected to the third node. The seventh switch element may include a first electrode connected to the first constant voltage node, a gate electrode connected to a fourth gate line to which a fourth gate signal is applied, and a second electrode connected to the first node.

Each of the first to seventh switch elements and the driving element may be an n-channel transistor. Each of the first to seventh switch elements may be turned on in response to a gate high voltage and turned off in response to a gate low voltage. The voltage of the first gate signal may be the gate high voltage during the first and second periods, and may be the gate low voltage during the third and fourth periods. The voltage of the second gate signal may be the gate low voltage during the first period and the second period, and may be the gate high voltage during the third period and the fourth period. The voltage of the third gate signal may be the gate high voltage during the second period, and may be the gate low voltage during the first period, the third period, and the fourth period. The voltage of the fourth gate signal may be the gate low voltage during the second period and the third period, and may be the gate high voltage during the first period and the fourth period.

Each of the driving element, the first switch element, the third switch element, and the fifth switch element is an n-channel transistor, and the second switch element, the fourth switch element, the sixth switch element, and the first switch element are n-channel transistors. Each of the seven switch elements may be a p-channel transistor. Each of the first switch element, the third switch element, and the fifth switch element may be turned on in response to a gate high voltage and turned off in response to a gate low voltage. Each of the second switch element, the fourth switch element, the sixth switch element, and the seventh switch element may be turned on in response to the gate low voltage and turned off in response to the gate high voltage. The voltage of the first gate signal may be the gate high voltage during the first and second periods, and may be the gate low voltage during the third and fourth periods. The voltage of the second gate signal may be the gate high voltage during the first period and the second period, and may be the gate low voltage during the third period and the fourth period. The voltage of the third gate signal may be the gate low voltage during the second period, and may be the gate high voltage during the first period, the third period, and the fourth period. The voltage of the fourth gate signal may be the gate high voltage during the second period and the third period, and may be the gate low voltage during the first period and the fourth period.

A pixel circuit according to another embodiment of the present invention includes a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node. Drive elements including; a light emitting element including an anode electrode connected to a fourth node, and a cathode electrode to which a pixel base voltage is applied; a first switch element connected between the third node and a second gate electrode of the driving element; a second switch element connected between the first node and the second node; and a third switch element connected between the third node and the fourth node.

The pixel circuit includes a capacitor connected between the second node and the fourth node; a fourth switch element connected between the fourth node and a third constant voltage node to which an initialization voltage is applied; a fifth switch element connected between a data line to which a data voltage is applied and the third node; And it may further include a first constant voltage node to which a pixel driving voltage is applied, and a sixth switch element connected between the first node.

The first switch element may include a first electrode connected to the third node, a gate electrode connected to a second gate line to which a second gate signal is applied, and a second electrode connected to the second gate electrode of the driving element. there is. The second switch element may include a first electrode connected to the second node, a gate electrode connected to a first gate line to which a first gate signal is applied, and a second electrode connected to the first node. The third switch element may include a first electrode connected to the third node, a gate electrode connected to the second gate line, and a second electrode connected to the fourth node. The fourth switch element may include a first electrode connected to the fourth node, a gate electrode connected to the first gate line, and a second electrode connected to the third constant voltage node. The fifth switch element may include a first electrode connected to the data line, a gate electrode connected to a third gate line to which a third gate signal is applied, and a second electrode connected to the third node. The sixth switch element may include a first electrode connected to the first constant voltage node, a gate electrode connected to a fourth gate line to which a fourth gate signal is applied, and a second electrode connected to the first node.

Each of the first to sixth switch elements and the driving element may be an n-channel transistor. Each of the first to sixth switch elements may be turned on in response to a gate high voltage and turned off in response to a gate low voltage. The voltage of the first gate signal may be the gate high voltage during the first and second periods, and may be the gate low voltage during the third and fourth periods. The voltage of the second gate signal may be the gate low voltage during the first period and the second period, and may be the gate high voltage during the third period and the fourth period. The voltage of the third gate signal may be the gate high voltage during the second period, and may be the gate low voltage during the first period, the third period, and the fourth period. The voltage of the fourth gate signal may be the gate low voltage during the second period and the third period, and may be the gate high voltage during the first period and the fourth period.

Each of the driving element, the first switch element, the third switch element, the fifth switch element, and the sixth switch element is a p-channel transistor, and the driving element, the second switch element, and the fourth switch are each a p-channel transistor. Each element may be an n-channel transistor. Each of the first switch element, the third switch element, the fifth switch element, and the sixth switch element may be turned on in response to a gate low voltage and turned off in response to a gate high voltage. Each of the second switch element and the fourth switch element may be turned on in response to the gate high voltage and turned off in response to the gate low voltage. The voltage of the first gate signal may be the gate high voltage during the first and second periods, and may be the gate low voltage during the third and fourth periods. The voltage of the second gate signal may be the gate high voltage during the first period and the second period, and may be the gate low voltage during the third period and the fourth period. The voltage of the third gate signal may be the gate low voltage during the second period, and may be the gate high voltage during the first period, the third period, and the fourth period. The voltage of the fourth gate signal may be the gate high voltage during the second period and the third period, and may be the gate low voltage during the first period and the fourth period.

A display device according to an embodiment of the present invention includes the pixel circuit.

In the present invention, during the sampling and addressing period in the internal compensation stage of the pixel circuit, the first and second gate electrodes of the driving element are connected to operate as a double gate transistor, and the second gate electrode and the third node (source node) are connected. Block the connection. As a result, the present invention can increase the on-current and improve sampling capability during sampling and addressing periods.

The present invention can improve low grayscale expression by connecting the second gate electrode of the driving element to the third node (source node) during the light emission period in the internal compensation stage of the pixel circuit.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram showing a display device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 1.
Figure 3 is a diagram schematically showing the display device of a mobile terminal.
Figure 4 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention.
FIG. 5 is a waveform diagram showing gate signals and data voltages applied to the pixel circuit shown in FIG. 4.
FIGS. 6A to 6D are circuit diagrams showing the operation of the pixel circuit shown in FIG. 5 for each period.
FIG. 7 is a diagram showing the voltage vs. current characteristic curve of a driving element in the pixel circuit shown in FIG. 4 with improved sampling ability and low gray level expression.
FIGS. 8 and 9 are diagrams showing the cross-sectional structures of the driving element, first switch element, and second switch element of the pixel circuit shown in FIG. 4.
Figure 10 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention.
FIG. 11 is a waveform diagram showing gate signals and data voltages applied to the pixel circuit shown in FIG. 10.
FIGS. 12A to 12D are circuit diagrams showing the operation of the pixel circuit shown in FIG. 10 for each period.
FIGS. 13 to 16 are diagrams showing cross-sectional structures of a driving element, a first switch element, and a second switch element of the pixel circuit shown in FIG. 10 .
Figure 17 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention.
FIG. 18 is a waveform diagram showing gate signals and data voltages applied to the pixel circuit shown in FIG. 17.
FIGS. 19A to 19D are circuit diagrams showing the operation of the pixel circuit shown in FIG. 17 by period.
FIG. 20 is a diagram showing a voltage vs. current characteristic curve of a driving element that improves sampling ability and low gray level expression in the pixel circuit shown in FIG. 17.
FIGS. 21 and 22 are diagrams showing the cross-sectional structures of the driving element and the first switch element of the pixel circuit shown in FIG. 17.
Figure 23 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention.
FIG. 24 is a waveform diagram showing gate signals and data voltages applied to the pixel circuit shown in FIG. 24.
FIGS. 25A to 25D are circuit diagrams showing the operation of the pixel circuit shown in FIG. 23 for each period.
FIGS. 26 to 29 are diagrams showing the cross-sectional structures of the driving element and the first switch element of the pixel circuit shown in FIG. 23.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. The embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “provides,” “includes,” “has,” “consists of,” etc. mentioned in this specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

Position between two components, such as 'on', 'on top', 'on the bottom', 'next to', '~ connect, couple', crossing, intersecting, etc. When relationships and interconnections are described, one or more other components may be interposed between the components, unless reference is made to 'immediately' or 'directly'.

If a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., it may not be continuous on the time axis unless 'immediately' or 'directly' is used. .

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistor may be an Oxide TFT (Thin Film Transistor) containing an oxide semiconductor or a LTPS TFT containing Low Temperature Poly Silicon (LTPS).

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal can swing between Gate On Voltage and Gate Off Voltage. The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (Gate High Voltage), and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 1. Figure 3 is a diagram schematically showing the display device of a mobile terminal.

1 to 3, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and pixels. and a power supply unit 140 that generates power necessary to drive the display panel driving circuit.

The display panel 100 may be a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels 101 . Power lines are connected to constant voltage nodes of the pixel circuits to supply the pixels 101 with a constant voltage required to drive the pixels 101.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white subpixel. Each subpixel includes a pixel circuit for driving a light emitting device. Each pixel circuit is connected to data lines, gate lines, and power lines.

Pixels can be arranged as real color pixels and pentile pixels. Pentile pixels can implement higher resolution than real color pixels by driving two sub-pixels of different colors into one pixel (101) using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color expression in each pixel with the color of light emitted from adjacent pixels.

The pixel array includes a plurality of pixel lines (L1 to Ln). Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. Pixels placed in one pixel line share gate lines 103. Subpixels arranged in the column direction (Y) along the data line direction share the same data line 102. 1 horizontal period is the time divided by 1 frame period by the total number of pixel lines (L1 to Ln).

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device where an image is displayed on the screen and the actual object in the background is visible. The display panel 100 may be manufactured as a flexible display panel.

The cross-sectional structure of the display panel 100 may include a circuit layer (CIR), a light emitting element layer (EMIL), and an encapsulation layer (ENC) stacked on a substrate (SUBS) as shown in FIG. 2. there is.

The circuit layer (CIR) may include a TFT array including a pixel circuit connected to wires such as data lines, gate lines, and power lines, a demultiplexer array 112, and a gate driver 120. The circuit layer (CIR) includes a plurality of metal layers insulated with insulating layers interposed therebetween, and a semiconductor material layer.

The light emitting device layer (EMIL) may include a light emitting device driven by a pixel circuit. The light emitting device may include a light emitting device in a red subpixel, a light emitting device in a green subpixel, and a light emitting device in a blue subpixel. The light emitting device layer (EMIL) may further include a white subpixel light emitting device. The light emitting element layer (EMIL) in each subpixel may have a structure in which a light emitting element and a color filter are stacked. The light emitting elements EL of the light emitting element layer EMIL may be covered with multiple protective layers including an organic layer and an inorganic layer.

The encapsulation layer (ENC) covers the light emitting device layer (EMIL) to seal the circuit layer (CIR) and the light emitting device layer (EMIL). The encapsulation layer (ENC) may have a multi-insulating film structure in which organic and inorganic films are alternately stacked. The inorganic membrane blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When an organic film and an inorganic film are stacked in multiple layers, the movement path of moisture or oxygen is longer compared to a single layer, so the penetration of moisture and oxygen that affects the light emitting device layer (EMIL) can be effectively blocked.

A touch sensor layer (omitted from the drawing) may be formed on the encapsulation layer (ENC), and a polarizing plate or color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense touch input based on changes in capacitance before and after touch input. The touch sensor layer may include metal wiring patterns and insulating films that form the capacitance of the touch sensors. The insulating films can insulate the intersections of metal wiring patterns and flatten the surface of the touch sensor layer. The polarizer can improve visibility and contrast ratio by converting the polarization of external light reflected by the metal of the touch sensor layer and circuit layer. The polarizer may be implemented as a polarizer or circular polarizer in which a linear polarizer and a phase retardation film are bonded. A cover glass may be adhered onto the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer absorbs part of the wavelength of light reflected from the circuit layer and the touch sensor layer, taking the role of a polarizer and increasing the color purity of the image reproduced in the pixel array.

The power supply unit 140 uses a DC-DC converter to generate constant voltage (or direct current (DC) voltage) required to drive the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power unit 140 adjusts the level of the direct current input voltage applied from the host system 200 to the gamma reference voltage (VGMA) and the gate high voltage (VGH). Constant voltages such as gate low voltage (VGL), pixel driving voltage (VDDEL), pixel base voltage (VSSEL), and initialization voltage (Vini) can be generated. The gamma reference voltage (VGMA) is supplied to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined according to the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest gray level voltage and the lowest gray level voltage.

The gate high voltage (VGH) and the gate low voltage (VGL) are supplied to the level shifter 150 and the gate driver 120. Constant voltages such as the pixel driving voltage (VDDEL), the pixel base voltage (VSSEL), and the initialization voltage (Vini) are supplied to the pixels 101 through power lines commonly connected to the pixels 101.

The pixel driving voltage VDDEL may be output from the main power source of the host system 200 and supplied to the display panel 100. In this case, the power supply unit 140 does not need to output the pixel driving voltage (VDDEL).

The display panel driving circuit writes pixel data of the input image to the pixels of the display panel 100 under the control of a timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120. The display panel driving circuit may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of de-multiplexers (DEMUX). The demultiplexer may include a plurality of switch elements disposed on the display panel 100. If the demultiplexer is disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. Demultiplexer array 112 may be omitted.

The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. The data driver 110 and the touch sensor driver may be integrated into one drive IC (Integrated Circuit). In a mobile terminal or wearable terminal, the timing controller 130, power supply unit 140, level shifter 150, data driver 110, touch sensor driver, etc. are integrated into one drive IC (DIC) as shown in FIG. 3. It can be.

The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts pixel data of the input image into a gamma compensation voltage using a digital to analog converter (DAC) and outputs the data voltage. The gamma reference voltage (VGMA) is divided into a gamma compensation voltage for each gray level through a voltage dividing circuit of the data driver 110 and provided to the DAC. The DAC generates a data voltage with a gamma compensation voltage corresponding to the grayscale value of the pixel data. The data voltage output from the DAC may be output to the data line 102 through an output buffer in each of the channels of the data driver 110 or may be output to the data line 102 through the demultiplexer array 112.

The gate driver 120 may be formed in the circuit layer (CIR) on the display panel 100 along with the TFT array and wires of the pixel array. The gate driver 120 may be disposed in a non-display area (Bezel, BZ) outside the display area AA of the display panel 100, or at least a portion of the gate driver 120 may be disposed in the display area AA.

The gate driver 120 may include a plurality of shift registers for sequentially shifting pulses of gate signals. The gate driver 120 is disposed in the bezel area (BZ) on both sides of the display panel 100 with the display area of the display panel in between, and transmits the gate signal by double feeding on both sides of the gate lines 103. Pulses can be supplied. In another embodiment, the gate driver 120 may be disposed on one of the left and right bezels of the display panel 100 and supply a gate signal to the gate lines 103 using a single feeding method. The gate driver 120 sequentially outputs pulses of gate signals to gate lines under the control of the timing controller 130. The gate driver 120 can sequentially supply the signals to the gate lines 103 by shifting the pulse of the gate signal using a shift register.

The timing controller 130 receives digital video data of an input image from the host system 200 and a timing signal synchronized with this data. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H).

The timing controller 130 provides a data timing control signal for controlling the operation timing of the data driver 110 based on the timing signals (Vsync, Hsync, DE) received from the host system 200 and the operation of the demultiplexer array 112. A MUX control signal for controlling timing and a gate timing control signal for controlling the operation timing of the gate driver 120 are generated. The timing controller 130 controls the operation timing of the display panel driving circuit and synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 150. The level shifter 150 may receive a gate timing control signal, generate a start pulse and a shift clock, and provide them to the gate driver 120. The level shifter 150 may supply a MUX control signal to the demultiplexer array 112. The input signal of the level shifter 150 may be a digital signal voltage signal, and the output signal of the level shifter 150 may be an analog voltage signal swinging between the gate high voltage (VGH) and the gate low voltage (VGL).

The host system 200 may include a main board of any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host system can scale the image signal from the video source to match the resolution of the display panel 100 and transmit it to the timing controller 130 along with the timing signal.

In a mobile system, the host system 200 may be implemented as an Application Processor (AP). The host system 200 may transmit pixel data of the input image to the drive IC (DIC) shown in FIG. 3 through MIPI (Mobile Industry Processor Interface). As shown in FIG. 3, the host system 200 may be connected to a drive IC (DIC) through a flexible printed circuit (FPC), for example. The drive IC may be bonded onto the display panel 100 using a chip on glass (COG) process.

The pixel circuit of each subpixel may include an internal compensation circuit to sample the threshold voltage of the driving element and compensate for the data voltage by the threshold voltage.

Figure 4 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention.

Referring to FIG. 4, the pixel circuit includes a light emitting element (EL), a driving element (DT) that drives the light emitting element (EL), a plurality of switch elements (T1 to T7), and a capacitor (Cst). Each of the driving element (DT) and switch elements (T1 to T7) can be implemented as an n-channel oxide TFT.

The pixel circuit is connected to a data line (DL) to which the data voltage (Vdata) of pixel data is applied, and to gate lines (GL1 to GL4) to which gate signals (SCAN, SCAN2, EM1, and EM2) are applied.

The pixel circuit includes a first constant voltage node (PL1) to which the pixel driving voltage (VDDEL) is applied, a second constant voltage node (PL2) to which the pixel base voltage (VSSEL) is applied, and a third constant voltage node ( It is connected to power nodes to which constant voltage is applied, such as PL3). Power lines to which constant voltage nodes are connected on the display panel may be commonly connected to all pixels.

The basic voltage level of the pixel driving voltage (VDDEL) is higher than the maximum voltage of the data voltage (Vdata) and is set to a voltage at which the driving element (DT) can operate in the saturation region. The initialization voltage Vini may be set to a voltage lower than the pixel driving voltage VDDEL and higher than the pixel base voltage VSSEL. The gate high voltage (VGH) may be set to a voltage higher than the pixel driving voltage (VDDEL), and the gate low voltage (VGL) may be set to a voltage lower than the pixel base voltage (VSSEL). For example, the constant voltage applied to the pixel circuit is VDDEL=+8[V], Vini=+1.3[V], VSSEL=0[V], VGH=12.5[V], VGL=-5[V], etc. It may be set, but is not limited to this.

In this embodiment, the gate signals SCAN, SCAN2, EM1, and EM2 include pulses that swing between the gate high voltage (VGH) and the gate low voltage (VGL). The gate driver 120 has a first shift register that outputs the pulse of the first gate signal (SCAN1), a second shift register that outputs the pulse of the second gate signal (EM1), and a third gate signal (SCAN2). It may include a third shift register and a fourth shift register that outputs a fourth gate signal EM2.

The driving element (DT) generates current according to the gate-source voltage (Vgs) to drive the light emitting element (EL). The driving element DT includes a first electrode connected to the first node n1, a first gate electrode TG connected to the second node n2, a second electrode connected to the third node n3, and a fourth node. It includes a second gate electrode (BG) connected to (n4). The first node (n1) can be interpreted as a drain node, the second node (n2) can be interpreted as a gate node, and the third node (n3) can be interpreted as a source node. As shown in FIGS. 8 and 9 , the first gate electrode TG and the second gate electrode BG overlap with the semiconductor pattern ACT2 therebetween. The first gate electrode (TG) can be interpreted as a top gate electrode, and the second gate electrode (BG) can be interpreted as a bottom gate electrode.

The light emitting element (EL) can be implemented as OLED. The light emitting element EL includes an anode electrode, a cathode electrode, and an organic compound layer interposed between the electrodes. The anode electrode of the light emitting element EL is connected to the fifth node n5, and the cathode electrode is connected to the second constant voltage node PL2 to which the pixel base voltage VSSEL is applied. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer. , EIL), but is not limited thereto. When voltage is applied to the anode and cathode electrodes of the light emitting device (EL), holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML), forming excitons. At this time, visible light is emitted from the light emitting layer (EML). The light emitting device (EL) may be implemented as an OLED with a tandem structure in which a plurality of light emitting layers are stacked. OLED with a tandem structure can improve pixel brightness and lifespan.

The capacitor Cst is connected between the second node n2 and the fifth node n5.

The first switch element T1 is connected between the first node n1 and the fourth node n4. The first switch element T1 is turned on in response to the gate high voltage VGH of the first gate signal SCAN1 to connect the first node n1 to the fourth node n4. The first switch element T1 has a first electrode connected to the first node n1, a gate electrode connected to the first gate line GL1 to which the first gate signal SCAN1 is applied, and a fourth node n4. It includes a connected second electrode.

The second switch element T2 is connected between the third node n3 and the fourth node n4. The second switch element T2 is turned on in response to the gate high voltage VGH of the second gate signal EM1 to connect the third node n3 to the fourth node n4. The second switch element T2 has a first electrode connected to the third node n3, a gate electrode connected to the second gate line GL2 to which the second gate signal EM1 is applied, and a fourth node n4. It includes a connected second electrode.

The third switch element T3 is connected between the first node (n1) and the second node (n2). The third switch element T3 is turned on in response to the gate high voltage VGH of the first gate signal SCAN1 to connect the first node n1 to the second node n2. The third switch element T3 has a first electrode connected to the second node n2, a gate electrode connected to the first gate line GL1 to which the first gate signal SCAN1 is applied, and a first node n1. It includes a connected second electrode.

The fourth switch element T4 is connected between the third node (n3) and the fifth node (n5). The fourth switch element T4 is turned on in response to the gate high voltage VGH of the second gate signal EM1 to connect the third node n3 to the fifth node n5. The fourth switch element T4 includes a first electrode connected to the third node n3, a gate electrode connected to the second gate line GL2, and a second electrode connected to the fifth node n5.

The fifth switch element T5 is connected between the fifth node n5 and the third constant voltage node PL3. The fifth switch element T5 is turned on in response to the gate high voltage VGH of the first gate signal SCAN1 to connect the fifth node n5 to the third constant voltage node PL3 to which the initialization voltage Vini is applied. ). The fifth switch element T5 includes a first electrode connected to the fifth node n5, a gate electrode connected to the first gate line GL1, and a second electrode connected to the third constant voltage node PL3.

The sixth switch element T6 is connected between the data line DL and the third node n3. The sixth switch element (T6) is turned on in response to the gate high voltage (VGH) of the third gate signal (SCAN2) and connects the data line (DL) to which the data voltage (Vdata) is applied to the third node (n3). Connect. The sixth switch element T6 includes a first electrode connected to the data line DL, a gate electrode connected to the third gate line GL3 to which the third gate signal SCAN2 is applied, and a third node n3. Includes a second electrode.

The seventh switch element T7 is connected between the first constant voltage node PL1 and the first node n1. The seventh switch element T7 is turned on in response to the gate high voltage VGH of the fourth gate signal EM2 and connects the first constant voltage node PL1 to which the pixel driving voltage VDDEL is applied to the first node ( Connect to n1). The seventh switch element T7 includes a first electrode connected to the first constant voltage node PL1, a gate electrode connected to the fourth gate line GL4 to which the fourth gate signal EM2 is applied, and a first node n1. It includes a second electrode connected to.

The pixel circuit shown in FIG. 4 is in the order of the first period (INI), the second period (SAMP), the third period (PRG), and the fourth period (EMIS) as shown in FIGS. 5 to 6D. It can be driven.

Referring to FIG. 5, the first period (INI), the second period (SAMP), the third period (PRG), and the fourth period (EMIS) are the waveforms of the gate signals (SCAN1, SCAN2, EM1, EM2). It can be decided by . A floating time in which all gate signals SCAN1, SCAN2, EM1, and EM2 are at the gate low voltage VGL may be set between the second period SAMP and the third period PRG. Because the switch elements (T1 to T7) are off during the floating time, the main nodes (n1 to n5) are in the floating state.

The first gate signal SCAN1 includes pulses of the gate high voltage VGH generated during the first period INI and the second period SAMP. The voltage of the first gate signal SCAN1 is the gate low voltage VGL during the third period PRG and the fourth period EMIS. The first, third, and fifth switch elements T1, T3, and T5 are turned on in response to the gate high voltage VGH of the first gate signal SCAN1 to operate in the first period INI and the second period. It is on during (SAMP) and off during the third and fourth periods (PRG, EMIS).

The third gate signal SCAN2 includes a pulse of the gate high voltage VGH generated in synchronization with the data voltage Vdata during the second period SAMP. The voltage of the third gate signal SCAN2 is the gate low voltage VGL during the first, third, and fourth periods (INI, PRG, EMIS). The sixth switch element (T6) is turned on in response to the gate high voltage (VGH) of the second gate signal (SCAN2) and is in the on state for the second period (SAMP), and is turned on for the first, third and fourth periods ( INI, PRG, EMIS) is in the off state.

The second gate signal EM1 includes pulses of the gate low voltage VGL generated during the first and second periods INI and SAMP. The voltage of the second gate signal EM1 is the gate high voltage VGH during the third and fourth periods PRG and EMIS. The second and fourth switch elements T2 and T4 are turned on in response to the gate high voltage VGH of the second gate signal EM1 and are turned on during the third and fourth periods PRG and EMIS. , is off during the first and second periods (INI, SAMP).

The fourth gate signal EM2 includes pulses of the gate low voltage VGL generated during the second and third periods SAMP and PRG. The voltage of the fourth gate signal EM2 is the gate high voltage VGH during the first and fourth periods INI and EMIS. The seventh switch element (T7) is turned on in response to the gate high voltage (VGH) of the fourth gate signal (EM2) and is turned on during the first and fourth periods (INI, EMIS), and is turned on for the second and third periods (INI, EMIS). It is off during the period (SAMP, PRG).

FIGS. 6A to 6D are circuit diagrams showing step-by-step the operation of the pixel circuit shown in FIG. 4. FIG. 6A is a circuit diagram showing a current path flowing through a pixel circuit in a first period (INI). FIG. 6B is a circuit diagram showing a current path flowing through the pixel circuit in the second period (SAMP). FIG. 6C is a circuit diagram showing a current path flowing through a pixel circuit in the third period (PRG). FIG. 6D is a circuit diagram showing a current path flowing through a pixel circuit in the fourth period (EMIS).

Referring to FIGS. 4, 5, and 6A, the voltage of the first and fourth gate signals (SCAN1, EM2) during the first period (INI) is the gate high voltage (VGH), while the voltage of the second and third gate signals (SCAN1, EM2) is the gate high voltage (VGH). The voltage of the signals (SCAN2, EM1) is the gate low voltage (VGL). Accordingly, during the first period, the first, third, fifth, and seventh switch elements (T1, T3, T5, T7) are turned on, and the second, fourth, and sixth switch elements ( T2, T4, T6) are turned off. In the first period INI, the driving element DT is turned on, and the light emitting element EL is not driven.

During the first period (INI), the main nodes (n1 to n5) of the pixel circuit are initialized. At the end of the first period (INI), the voltage of the first, second, and fourth nodes (n1, n2, n4) is initialized to the pixel driving voltage (VDDEL), and the voltage of the fifth node (n5) is initialized. Initialized with voltage (Vini).

Referring to FIGS. 4, 5, and 6B, during the second period (SAMP), the data voltage (Vdata) of the pixel data is applied to the third node (n3) to write the pixel data to the subpixel, and at the same time, the driving element ( The threshold voltage (Vth) of DT) is sampled and stored in the capacitor (Cst).

During the second period (SAMP), the voltage of the first and third gate signals (SCAN1, SCAN2) is the gate high voltage (VGH), while the voltage of the second and fourth gate signals (EM1, EM2) is the gate high voltage (VGH). Low voltage (VGL). Accordingly, during the second period (SAMP), the first, third, fifth, and sixth switch elements (T1, T3, T5, T6, and T6) are turned on, and the second, fourth, and seventh switches are turned on. Elements T2, T4, and T7 are turned off. During the second period SAMP, the driving element DT is turned off when the gate-source voltage Vgs is lower than the threshold voltage, and the light emitting element EL is not driven.

At the end of the second period (SAMP), the voltage of the third node (n3) is the data voltage (Vdata), and the voltages of the first, second and fourth nodes (n1, n2, n4) are Vdata-Vth. . Here, 'Vth' is the threshold voltage of the driving element (DT). In the second period (SAMP), the voltage of the fifth node (n5) maintains the initialization voltage (Vini). Since the capacitor Cst stores the difference voltage between the voltage of the second node n2 and the voltage of the fifth node n5, when the second period SAMP ends, (Vdata+Vth)-Vini is stored.

Referring to FIGS. 4, 5, and 6C, the voltage of the third node (n3) is set to the initialization voltage (Vini) during the third period (PRG).

During the third period PRG, the voltage of the second gate signal EM1 is the gate high voltage VGH, while the voltages of the other gate signals SCAN1, SCAN2, and EM2 are the gate low voltage VGL. Accordingly, during the third period PRG, the second and fourth switch elements T2 and T4 are turned on, and the first, third, fifth, sixth and seventh switch elements T1, T3, T5, T6, T7) are turned off. At the end of the third period (PRG), the voltage of the second node (n2) is Vdata+Vth. Since the third node (n3) and the fifth node (n5) are connected during the third period (PRG), the voltages of the third and fifth nodes (n3, n5) are initialized at the end of the third period (PRG). It is voltage (Vini).

Referring to FIGS. 4, 5, and 6D, during the fourth period (EMIS), the driving device (DT) supplies current to the light emitting device (EL) according to the gate-source voltage (Vgs) to Run .

During the fourth period (EMIS), the voltage of the second and fourth gate signals (EM1, EM2) is the gate high voltage (VGH), while the voltage of the other gate signals (SCAN1, SCAN2) is the gate low voltage (VGL) )am. Accordingly, during the fourth period (EMIS), the second, fourth, and seventh switch elements (T2, T4, T7) are turned on, and the first, third, fifth, and sixth switch elements ( T1, T3, T5, T6) are turned off. During the fourth period (EMIS), the current (I) flowing to the light emitting element (EL) is am. Here, k is a constant value including the channel ratio and mobility of the driving element. By this current (I), the voltage of the third, fourth, and fifth nodes (n3, n4, n5) changes to the anode voltage (Voled) of the light emitting element (EL), and the voltage of the second node (n2) is Changes to Vdata+Vth+Voled-Vini. Accordingly, the voltage (Vgs) between the gate and source of the driving device (DT) during the fourth period (EMIS) is Vgs = Vdata + Vth - Vini.

As can be seen from FIGS. 4 to 6D, in the pixel circuit shown in FIG. 4, the first gate electrode (TG) and the second gate electrode (BG) of the driving element (DT) are connected to each other during the second period (SAMP). It is connected through the first and third switch elements (T1, T3). Additionally, the pixel circuit shown in FIG. 4 prevents the second gate electrode BG of the driving element DT from being connected to the third node n3 during the second period SAMP. It is possible to prevent a decrease in the on-current of the driving element DT. As a result, during the second period (SAMP), the driving element (DT) is driven by a double gate transistor, so that the on-current increases as can be seen from the curve of “Double gate TR” in FIG. 7. The threshold voltage (Vth) of the device (DT) can be sampled quickly and accurately.

In the pixel circuit shown in FIG. 4, the subthreshold slope of the driving element DT is lowered during the fourth period (EMIS), as can be seen from the curve of "Source contact TR" in FIG. 7, resulting in low gray level expression. It can be improved. Here, the slope below the threshold can be interpreted as an S-factor.

Accordingly, in the pixel circuit shown in FIG. 4, the threshold voltage sampling ability of the driving element DT is improved during the second period (SAMP), and the sub-threshold slope characteristic of the driving element DT is improved during the fourth period (SAMP). This improves the ability to express low gradations.

In FIG. 7, the curve of “Double gate TR” is the drain-to-source current (Ids) relative to the gate-to-source voltage (Vgs) of the driving device (DT) during the second period (SAMP). The curve of “Source contact TR” is the drain-to-source current (Ids) relative to the gate-to-source voltage (Vgs) of the driving element (DT) during the fourth period (EMIS). “Single gate TR” is the drain-source current (Ids) relative to the gate-source voltage (Vgs) of a three-electrode driving device without a second gate electrode.

FIGS. 8 and 9 are diagrams showing the cross-sectional structures of the driving element (DT), the first switch element (T1), and the second switch element (T2) of the pixel circuit shown in FIG. 4.

Referring to FIGS. 8 and 9 , the circuit layer (CIR) of the display panel 100 includes a pixel circuit. The circuit layer CIR includes first to eighth insulating layers BUF1 to ILD5 stacked on a substrate. The insulating layers (BUF1 to ILD5) may be formed of an inorganic insulating material.

The semiconductor patterns (ACT1, ACT2, ACT3) for forming the channels of the driving element (DT) and the first and second switch elements (T1, T2) are made of an oxide semiconductor, for example, IGZO (Indium Gallium Zinc Oxide). can be formed. In this case, the fifth and sixth insulating layers (BUF2, GI) in contact with the semiconductor patterns (ACT1, ACT2, ACT3) are preferably formed of an oxide, for example, silicon oxide (SiOx). The first to fourth insulating layers BUF1 to ILD3 and the seventh and eighth insulating layers ILD4 and ILD5 may be formed of silicon nitride (SiNx) or silicon oxide (SiOx).

The first switch element T1 includes a first semiconductor pattern ACT1 disposed on the fifth insulating layer BUF2, a gate electrode TG1 disposed on the sixth insulating layer GI, and an eighth insulating layer ( It includes first and second source/drain electrode patterns SD1 and SD2 disposed on ILD5). The gate electrode TG1 overlaps the first semiconductor pattern ACT1 with the sixth insulating layer GI interposed therebetween.

In the first switch element T1, the first source/drain electrode pattern SD1 is a first electrode connected to the first node n1 as shown in FIG. 4. The first source/drain electrode pattern SD1 is in contact with one side of the upper surface of the first semiconductor pattern ACT1 through a first contact hole penetrating the sixth to eighth insulating layers GI to ILD5. . As shown in FIG. 4 , the second source/drain electrode pattern SD2 is a second electrode connected to the fourth node n4 and the second gate electrode BG of the driving element DT. The second source/drain electrode pattern SD2 is in contact with the other upper surface of the first semiconductor pattern ACT1 through the second contact hole penetrating the sixth to eighth insulating layers GI to ILD5, and the fifth to eighth insulating layers GI to ILD5. It is contacted to one upper surface of the second gate electrode BG of the driving element DT through the third contact hole penetrating the eighth insulating layers ILD3 to ILD5.

The driving element DT includes a second semiconductor pattern ACT2 disposed on the fifth insulating layer BUF2, a first gate electrode TG2 disposed on the sixth insulating layer GI, and an eighth insulating layer ILD5. ) and third and fourth source/drain electrode patterns SD3 and SD4 disposed on the third insulating layer ILD2. The first gate electrode TG2 overlaps the second semiconductor pattern ACT2 with the sixth insulating layer GI interposed therebetween. The second gate electrode BG overlaps the second semiconductor pattern ACT2 with the fourth and fifth insulating layers ILD3 and BUF2 interposed therebetween.

In the driving element DT, the third source/drain electrode pattern SD3 is a first electrode connected to the first node n1 and the first electrode of the first switch element T1, as shown in FIG. 4. . The first electrode of the first switch element T1 is the first source/drain pattern SD1. The third source/drain electrode pattern SD3 is in contact with one side of the upper surface of the second semiconductor pattern ACT2 through the fourth contact hole penetrating the sixth to eighth insulating layers GI to ILD5. The fourth source/drain electrode pattern SD4 is a second electrode connected to the third node n3 and the first electrode of the second switch element T2, as shown in FIG. 4. 8 and 9, the first electrode of the second switch element T2 is the sixth source/drain electrode pattern SD6. The fourth source/drain electrode pattern SD4 is in contact with the other upper surface of the second semiconductor pattern ACT2 through the fifth contact hole penetrating the sixth to eighth insulating layers GI to ILD5.

The second switch element (T2) includes a third semiconductor pattern (ACT3) disposed on the fifth insulating layer (BUF2), a gate electrode (TG3) disposed on the sixth insulating layer (GI), and an eighth insulating layer ( It includes fifth and sixth source/drain electrode patterns SD5 and SD6 disposed on ILD5). The gate electrode TG3 overlaps the third semiconductor pattern ACT3 with the sixth insulating layer GI interposed therebetween.

In the second switch element T2, the fifth source/drain electrode pattern SD5 is connected to the fourth node n4 and the second gate electrode BG of the driving element DT, as shown in FIG. 4. This is the second electrode. The fifth source/drain electrode pattern SD5 is connected to the other upper surface of the second gate electrode BG of the driving element DT through the sixth contact hole penetrating the fourth to eighth insulating layers ILD3 to ILD5. It contacts one side of the upper surface of the third semiconductor pattern ACT3 through the seventh contact hole penetrating the sixth to eighth insulating layers GI to ILD5. The sixth source/drain electrode pattern SD6 is a first electrode connected to the third node n3 and the second electrode of the driving element DT, as shown in FIG. 4. The sixth source/drain electrode pattern SD6 is in contact with the other upper surface of the third semiconductor pattern ACT3 through the eighth contact hole penetrating the sixth to eighth insulating layers GI to ILD5.

In order to increase the reliability of the first and second switch elements T1 and T2, bottom metal patterns LS1 and LS2 are formed below the first and second switch elements T1 and T2, as shown in FIG. 9. ) can be placed. The first bottom metal pattern LS1 is disposed on the second insulating layer ILD1 below the first switch element T1 and overlaps the first semiconductor pattern ACT1. The second bottom metal pattern LS2 is disposed on the second insulating layer ILD1 below the second switch element T2 and overlaps the third semiconductor pattern ACT3. The bottom metal patterns (LS1, LS1) block the gas penetration path so that out gassing from the insulating layers (BUF1, ILD1) below does not affect the switch elements (T1, T2), Electrical interference between circuit elements or signal lines disposed below the switch elements T1 and T2 and the switch elements T1 and T2 can be blocked.

The first gate signal SCAN1 may be applied to the first bottom metal pattern LS1 or may be floating. The second gate signal EM may be applied to the second bottom metal pattern LS2 or may be floated.

Figure 10 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention. In FIG. 10, components that are substantially the same as those of the above-described first embodiment are given the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 10, the pixel circuit includes a light emitting element (EL), a driving element (DT) that drives the light emitting element (EL), a plurality of switch elements (T1 to PT7), and a capacitor (Cst). Each of the driving element (DT), the first switch element (T1), the third switch element (T3), and the fifth switch element (T5) can be implemented as an n-channel oxide TFT with low off current, which is advantageous for improving power consumption. . Each of the second switch element (PT2), the fourth switch element (PT4), the sixth switch element (PT6), and the seventh switch element (PT7) may be implemented as a p-channel LTPS TFT with high mobility and high on-current.

The second switch element PT2 is connected between the third node (n3) and the fourth node (n4). The second switch element PT2 is turned on in response to the gate low voltage VGL of the second gate signal EM1 to connect the third node n3 to the fourth node n4. The second switch element PT2 has a first electrode connected to the third node n3, a gate electrode connected to the second gate line GL2 to which the second gate signal EM1 is applied, and a fourth node n4. It includes a connected second electrode.

The fourth switch element PT4 is connected between the third node (n3) and the fifth node (n5). The fourth switch element PT4 is turned on in response to the gate low voltage VGL of the second gate signal EM1 to connect the third node n3 to the fifth node n5. The fourth switch element PT4 includes a first electrode connected to the third node n3, a gate electrode connected to the second gate line GL2, and a second electrode connected to the fifth node n5.

The sixth switch element PT6 is connected between the data line DL and the third node n3. The sixth switch element PT6 is turned on in response to the gate low voltage VGL of the third gate signal SCAN2 and connects the data line DL to which the data voltage Vdata is applied to the third node n3. Connect. The sixth switch element PT6 has a first electrode connected to the data line DL, a gate electrode connected to the third gate line GL3 to which the third gate signal SCAN2 is applied, and a third node connected to n3. Includes a second electrode.

The seventh switch element PT7 is connected between the first constant voltage node PL1 and the first node n1. The seventh switch element PT7 is turned on in response to the gate low voltage VGL of the fourth gate signal EM2 to connect the first constant voltage node PL1 to which the pixel driving voltage VDDEL is applied to the first node ( Connect to n1). The seventh switch element PT7 includes a first electrode connected to the first constant voltage node PL1, a gate electrode connected to the fourth gate line GL4 to which the fourth gate signal EM2 is applied, and a first node n1. It includes a second electrode connected to.

The pixel circuit shown in FIG. 10 is in the order of the first period (INI), the second period (SAMP), the third period (PRG), and the fourth period (EMIS) as shown in FIGS. 11 to 12D. It can be driven.

Referring to FIG. 11, the first period (INI), the second period (SAMP), the third period (PRG), and the fourth period (EMIS) are in the waveforms of the gate signals (SCAN1, SCAN2, EM1, EM2). can be determined by A floating time in which all gate signals SCAN1, SCAN2, EM1, and EM2 are at the gate low voltage VGL may be set between the second period SAMP and the third period PRG.

The first gate signal SCAN1 includes pulses of the gate high voltage VGH generated during the first period INI and the second period SAMP. The voltage of the first gate signal SCAN1 is the gate low voltage VGL during the third period PRG and the fourth period EMIS. The first, third, and fifth switch elements T1, T3, and T5 are turned on in response to the gate high voltage VGH of the first gate signal SCAN1 to operate in the first period INI and the second period. It is on during (SAMP) and off during the third and fourth periods (PRG, EMIS).

The third gate signal SCAN2 includes a pulse of the gate low voltage VGL generated in synchronization with the data voltage Vdata during the second period SAMP. The voltage of the third gate signal SCAN2 is the gate high voltage VGL during the first, third, and fourth periods (INI, PRG, EMIS). The sixth switch element (PT6) is turned on in response to the gate low voltage (VGL) of the second gate signal (SCAN2) and is in the on state for the second period (SAMP), and is switched on in the first, third and fourth periods ( INI, PRG, EMIS) is in the off state.

The second gate signal EM1 includes pulses of the gate high voltage VGH generated during the first and second periods INI and SAMP. The voltage of the second gate signal EM1 is the gate low voltage VGL during the third and fourth periods PRG and EMIS. The second and fourth switch elements PT2 and PT4 are turned on in response to the gate low voltage VGL of the second gate signal EM1 and are turned on during the third and fourth periods PRG and EMIS. , is off during the first and second periods (INI, SAMP).

The fourth gate signal EM2 includes pulses of the gate high voltage VGH generated during the second and third periods SAMP and PRG. The voltage of the fourth gate signal EM2 is the gate low voltage VGH during the first and fourth periods INI and EMIS. The seventh switch element (PT7) is turned on in response to the gate low voltage (VGL) of the fourth gate signal (EM2) and is turned on during the first and fourth periods (INI, EMIS), and is switched on for the second and third periods (INI, EMIS). It is off during the period (SAMP, PRG).

FIGS. 12A to 12D are circuit diagrams showing the operation of the pixel circuit shown in FIG. 10 step by period. FIG. 12A is a circuit diagram showing a current path flowing through a pixel circuit in a first period (INI). FIG. 12B is a circuit diagram showing a current path flowing through the pixel circuit in the second period (SAMP). FIG. 12C is a circuit diagram showing a current path flowing through the pixel circuit in the third period (PRG). FIG. 12D is a circuit diagram showing a current path flowing through a pixel circuit in the fourth period (EMIS).

10, 11, and 12A, the voltage of the first, second, and third gate signals SCAN1, EM1, and SCAN2 during the first period INI is the gate high voltage VGH, while the voltage of the first, second, and third gate signals SCAN1, EM1, and SCAN2 is the gate high voltage VGH. 4 The voltage of the gate signal (EM2) is the gate low voltage (VGL). Accordingly, during the first period, the first, third, fifth, and seventh switch elements T1, T3, T5, and PT7 are turned on, and the second, fourth, and sixth switch elements ( T2, T4, T6) are turned off.

During the first period (INI), the main nodes (n1 to n5) of the pixel circuit are initialized. At the end of the first period (INI), the voltage of the first, second, and fourth nodes (n1, n2, n4) is initialized to the pixel driving voltage (VDDEL), and the voltage of the fifth node (n5) is initialized. Initialized with voltage (Vini).

Referring to FIGS. 10, 11, and 12B, during the second period (SAMP), the data voltage (Vdata) of the pixel data is applied to the third node (n3) and the pixel data is written to the sub-pixel, and at the same time, the driving element ( The threshold voltage (Vth) of DT) is sampled and stored in the capacitor (Cst).

During the second period (SAMP), the voltage of the first, second, and fourth gate signals (SCAN1, EM1, EM2) is the gate high voltage (VGH), while the voltage of the third gate signal (SCAN2) is the gate high voltage (VGH). Low voltage (VGL). Accordingly, during the second period (SAMP), the first, third, fifth, and sixth switch elements (T1, T3, T5, and PT6) are turned on, and the second, fourth, and seventh switch elements ( PT2, PT4, PT7) are turned off.

At the end of the second period (SAMP), the voltage of the third node (n3) is the data voltage (Vdata), and the voltages of the first, second and fourth nodes (n1, n2, n4) are Vdata-Vth. . Here, 'Vth' is the threshold voltage of the driving element (DT). In the second period (SAMP), the voltage of the fifth node (n5) maintains the initialization voltage (Vini).

Referring to FIGS. 10, 11, and 12C, the voltage of the third node (n3) is set to the initialization voltage (Vini) during the third period (PRG).

During the third period PRG, the voltages of the third and fourth gate signals SCAN2 and EM2 are the gate high voltage VGH, while the voltages of the first and second gate signals SCAN1 and EM1 are the gate high voltages VGH. Low voltage (VGL). Accordingly, during the third period PRG, the second and fourth switch elements PT2 and PT4 are turned on, and the first, third, fifth, sixth and seventh switch elements T1, T3, T5, PT6, PT7) are turned off. At the end of the third period PRG, the voltage of the second node n2 is Vdata+Vth, and the voltages of the third and fifth nodes n3 and n5 are the initialization voltage Vini.

Referring to FIGS. 10, 11, and 12D, during the fourth period (EMIS), the voltage of the first, second, and fourth gate signals (SCAN1, EM1, and EM2) is the gate low voltage (VGL). The voltage of the third gate signal (SCAN2) is the gate high voltage (VGL). Accordingly, during the fourth period (EMIS), the second, fourth, and seventh switch elements (PT2, PT4, and PT7) are turned on, and the first, third, fifth, and sixth switch elements ( T1, T3, T5, PT6) are turned off.

The current flowing through the light emitting element (EL) is adjusted according to the gate-source voltage (Vgs) of the driving element (DT). During the fourth period (EMIS), the current (I) flowing to the light emitting element (EL) is am. By this current (I), the voltage of the third, fourth, and fifth nodes (n3, n4, n5) changes to the anode voltage (Voled) of the light emitting element (EL), and the voltage of the second node (n2) is Changes to Vdata+Vth+Voled-Vini. Accordingly, the voltage (Vgs) between the gate and source of the driving device (DT) during the fourth period (EMIS) is Vgs = Vdata + Vth - Vini.

As can be seen from FIGS. 10 to 12D, in the pixel circuit shown in FIG. 10, the first gate electrode (TG) and the second gate electrode (BG) of the driving element (DT) are connected to each other during the second period (SAMP). It is connected through the first and third switch elements (T1, T3). As a result, during the second period (SAMP), the driving element (DT) is driven by a double gate transistor and the on-current increases, so the threshold voltage (Vth) of the driving element (DT) can be quickly and accurately sampled. there is.

In the pixel circuit shown in FIG. 10, the subthreshold slope of the driving element DT is lowered during the fourth period EMIS, thereby improving low gray level expression.

Accordingly, in the pixel circuit shown in FIG. 10, the threshold voltage sampling ability of the driving element DT is improved during the second period (SAMP), and the sub-threshold slope characteristic of the driving element DT is improved during the fourth period (SAMP). This improves the ability to express low gradations.

FIGS. 13 to 16 are diagrams showing the cross-sectional structures of the driving element (DT), the first switch element (T1), and the second switch element (PT2) of the pixel circuit shown in FIG. 10. Since the cross-sectional structures of the driving element DT and the first switch element T1 are substantially the same as those in FIGS. 8 and 9 of the above-described first embodiment, detailed description thereof will be omitted.

Referring to FIGS. 13 and 14 , the semiconductor patterns ACT1 and ACT2 for forming channels of the driving element DT and the first switch element T1 may be formed of an oxide semiconductor. In this case, the fifth and sixth insulating layers (BUF2, GI2) in contact with the semiconductor patterns (ACT1, ACT2) are preferably formed of an oxide, for example, silicon oxide (SiOx). The first to fourth insulating layers BUF1 to ILD3 and the seventh and eighth insulating layers ILD4 and ILD5 may be formed of silicon nitride (SiNx) or silicon oxide (SiOx).

The semiconductor pattern ACT3 for forming the channel of the second switch element P1 may be formed of polycrystalline silicon.

The second switch element PT2 includes a third semiconductor pattern ACT3 disposed on the first insulating layer BUF1, a gate electrode TG3 disposed on the second insulating layer GI1, and a fourth insulating layer ( It includes fifth and sixth source/drain electrode patterns SD5 and SD6 disposed on ILD3). The gate electrode TG3 overlaps the third semiconductor pattern ACT3 with the second insulating layer GI1 interposed therebetween.

In the second switch element PT2, the fifth source/drain electrode pattern SD5 is connected to the fourth node n4 and the second gate electrode BG of the driving element DT, as shown in FIG. 10. This is the second electrode. The fifth source/drain electrode pattern SD5 is in contact with the other upper surface of the second gate electrode BG of the driving element DT through the sixth contact hole penetrating the fourth insulating layer ILD3, and the second to It is contacted to one side of the upper surface of the third semiconductor pattern ACT3 through the seventh contact hole penetrating the fourth insulating layers GI1, ILD2, and ILD3. The sixth source/drain electrode pattern SD6 is a first electrode connected to the third node n3 and the second electrode of the driving element DT, as shown in FIG. 10. The sixth source/drain electrode pattern SD6 is in contact with the other upper surface of the third semiconductor pattern ACT3 through the eighth contact hole penetrating the second to fourth insulating layers GI1, ILD2, and ILD3.

In order to increase the reliability of the first switch element T1, a bottom metal pattern LS may be disposed below the first switch element T1, as shown in FIG. 14. The bottom metal pattern LS is disposed on the second insulating layer GI1 below the first switch element T1 and overlaps the first semiconductor pattern ACT1. The first gate signal SCAN1 may be applied to the bottom metal pattern LS or may be floating.

15 and 16, the second switch element PT2 includes a third semiconductor pattern ACT3 disposed on the first insulating layer BUF1 and a gate electrode disposed on the second insulating layer GI1. TG3), and fifth and sixth source/drain electrode patterns SD5 and SD6 disposed on the eighth insulating layer ILD5.

In the second switch element PT2, the fifth source/drain electrode pattern SD5 is connected to the second gate of the driving element DT through the sixth contact hole penetrating the fourth to eighth insulating layers ILD3 to ILD5. It contacts the other upper surface of the electrode BG and contacts one upper surface of the third semiconductor pattern ACT3 through the seventh contact hole penetrating the second to eighth insulating layers GI1 to ILD5. The sixth source/drain electrode pattern SD6 is in contact with the other upper surface of the third semiconductor pattern ACT3 through the eighth contact hole penetrating the second to eighth insulating layers GI1 to LD5.

As shown in FIG. 16, the bottom metal pattern LS may be disposed below the first switch element T1. The bottom metal pattern LS is disposed on the second insulating layer GI1 below the first switch element T1 and overlaps the first semiconductor pattern ACT1.

Figure 17 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention.

Referring to FIG. 17, the pixel circuit includes a light emitting element (EL), a driving element (DT) that drives the light emitting element (EL), a plurality of switch elements (T01 to T06), and a capacitor (Cst). Each of the driving element (DT) and switch elements (T01 to T06) can be implemented as an n-channel oxide TFT.

The pixel circuit is connected to a data line (DL) to which the data voltage (Vdata) of pixel data is applied, and to gate lines (GL1 to GL4) to which gate signals (SCAN, SCAN2, EM1, and EM2) are applied.

The pixel circuit includes a first constant voltage node (PL1) to which the pixel driving voltage (VDDEL) is applied, a second constant voltage node (PL2) to which the pixel base voltage (VSSEL) is applied, and a third constant voltage node ( It is connected to power nodes to which constant voltage is applied, such as PL3). Power lines to which constant voltage nodes are connected on the display panel may be commonly connected to all pixels.

The basic voltage level of the pixel driving voltage (VDDEL) is higher than the maximum voltage of the data voltage (Vdata) and is set to a voltage at which the driving element (DT) can operate in the saturation region. The initialization voltage Vini may be set to a voltage lower than the pixel driving voltage VDDEL and higher than the pixel base voltage VSSEL. The gate high voltage (VGH) can be set to a voltage higher than the pixel driving voltage (VDDEL), and the gate low voltage (VGL) can be set to a voltage lower than the pixel base voltage (VSSEL).

The driving element (DT) generates current according to the gate-source voltage (Vgs) to drive the light emitting element (EL). The driving element DT includes a first electrode connected to the first node n1, a first gate electrode TG connected to the second node n2, a second electrode connected to the third node n3, and a fourth node. It includes a second gate electrode (BG) connected to (n4). As shown in FIGS. 21 and 22 , the first gate electrode TG and the second gate electrode BG overlap with the semiconductor pattern ACT01 therebetween.

The light emitting element (EL) can be implemented as OLED. The anode electrode of the light emitting element EL is connected to the fourth node n04, and the cathode electrode is connected to the second constant voltage node PL2 to which the pixel base voltage VSSEL is applied. The capacitor Cst is connected between the second node n2 and the fourth node n04.

The first switch element T01 is connected between the third node n3 and the second gate electrode BG of the driving element DT. The first switch element T01 is turned on in response to the gate high voltage VGH of the second gate signal EM1 to connect the third node n3 to the second gate electrode BG of the driving element DT. Connect. The first switch element T01 includes a first electrode connected to the third node n3, a gate electrode connected to the second gate line GL2 to which the second gate signal EM1 is applied, and a first electrode of the driving element DT. 2 It includes a second electrode connected to the gate electrode.

The second switch element T02 is connected between the first node (n1) and the second node (n2). The second switch element T02 is turned on in response to the gate high voltage VGH of the first gate signal SCAN1 to connect the first node n1 to the second node n2. The second switch element T02 has a first electrode connected to the second node n2, a gate electrode connected to the first gate line GL1 to which the first gate signal SCAN1 is applied, and a first node n1. It includes a connected second electrode.

The third switch element T03 is connected between the third node n3 and the fourth node n04. The third switch element T03 is turned on in response to the gate high voltage VGH of the second gate signal EM1 to connect the third node n3 to the fourth node n04. The third switch element T03 includes a first electrode connected to the third node n3, a gate electrode connected to the second gate line GL2, and a second electrode connected to the fourth node n04.

The fourth switch element T04 is connected between the fourth node n04 and the third constant voltage node PL3. The fourth switch element T04 is turned on in response to the gate high voltage VGH of the first gate signal SCAN1 to connect the fourth node n04 to the third constant voltage node PL3 to which the initialization voltage Vini is applied. ). The fourth switch element T04 includes a first electrode connected to the fourth node n04, a gate electrode connected to the first gate line GL1, and a second electrode connected to the third constant voltage node PL3.

The fifth switch element T05 is connected between the data line DL and the third node n3. The fifth switch element T05 is turned on in response to the gate high voltage VGH of the third gate signal SCAN2 and connects the data line DL to which the data voltage Vdata is applied to the third node n3. Connect. The fifth switch element T05 includes a first electrode connected to the data line DL, a gate electrode connected to the third gate line GL3 to which the third gate signal SCAN2 is applied, and a third node connected to n3. Includes a second electrode.

The sixth switch element T06 is connected between the first constant voltage node PL1 and the first node n1. The sixth switch element T06 is turned on in response to the gate high voltage VGH of the fourth gate signal EM2 to connect the first constant voltage node PL1 to which the pixel driving voltage VDDEL is applied to the first node ( Connect to n1). The sixth switch element T06 includes a first electrode connected to the first constant voltage node PL1, a gate electrode connected to the fourth gate line GL4 to which the fourth gate signal EM2 is applied, and a first node n1. It includes a second electrode connected to.

The pixel circuit shown in FIG. 17 is in the order of the first period (INI), the second period (SAMP), the third period (PRG), and the fourth period (EMIS) as shown in FIGS. 18 to 19D. It can be driven.

Referring to FIG. 18, the first period (INI), the second period (SAMP), the third period (PRG), and the fourth period (EMIS) are the waveforms of the gate signals (SCAN1, SCAN2, EM1, and EM2). It can be decided by . A floating time in which all gate signals SCAN1, SCAN2, EM1, and EM2 are at the gate low voltage VGL may be set between the second period SAMP and the third period PRG. Because the switch elements (T01 to T06) are off during the floating time, the main nodes (n1 to n04) are in the floating state.

The first gate signal SCAN1 includes pulses of the gate high voltage VGH generated during the first period INI and the second period SAMP. The voltage of the first gate signal SCAN1 is the gate low voltage VGL during the third period PRG and the fourth period EMIS. The second and fourth switch elements T01 and T04 are turned on in response to the gate high voltage VGH of the first gate signal SCAN1 and are turned on during the first period INI and the second period SAMP. state, and is off during the third and fourth periods (PRG, EMIS).

The third gate signal SCAN2 includes a pulse of the gate high voltage VGH generated in synchronization with the data voltage Vdata during the second period SAMP. The voltage of the third gate signal SCAN2 is the gate low voltage VGL during the first, third, and fourth periods (INI, PRG, EMIS). The fifth switch element (T05) is turned on in response to the gate high voltage (VGH) of the second gate signal (SCAN2) and is in the on state for the second period (SAMP), and is turned on for the first, third and fourth periods ( INI, PRG, EMIS) is in the off state.

The second gate signal EM1 includes pulses of the gate low voltage VGL generated during the first and second periods INI and SAMP. The voltage of the second gate signal EM1 is the gate high voltage VGH during the third and fourth periods PRG and EMIS. The first and third switch elements T01 and T03 are turned on in response to the gate high voltage VGH of the second gate signal EM1 and are turned on during the third and fourth periods PRG and EMIS. , is off during the first and second periods (INI, SAMP).

The fourth gate signal EM2 includes pulses of the gate low voltage VGL generated during the second and third periods SAMP and PRG. The voltage of the fourth gate signal EM2 is the gate high voltage VGH during the first and fourth periods INI and EMIS. The sixth switch element (T06) is turned on in response to the gate high voltage (VGH) of the fourth gate signal (EM2) and is on for the first and fourth periods (INI, EMIS), and is turned on for the second and third periods (INI, EMIS). It is off during the period (SAMP, PRG).

FIGS. 19A to 19D are circuit diagrams showing step-by-step the operation of the pixel circuit shown in FIG. 17. FIG. 19A is a circuit diagram showing a current path flowing through a pixel circuit in a first period (INI). FIG. 19B is a circuit diagram showing a current path flowing through the pixel circuit in the second period (SAMP). FIG. 19C is a circuit diagram showing a current path flowing through the pixel circuit in the third period (PRG). FIG. 19D is a circuit diagram showing a current path flowing through a pixel circuit in the fourth period (EMIS).

Referring to FIGS. 17, 18, and 19A, the voltage of the first and fourth gate signals (SCAN1, EM2) during the first period (INI) is the gate high voltage (VGH), while the voltage of the second and third gate signals (SCAN1, EM2) is the gate high voltage (VGH). The voltage of the signals (SCAN2, EM1) is the gate low voltage (VGL). Accordingly, during the first period, the second, fourth, and sixth switch elements T02, T04, and T06 are turned on, and the first, third, and fifth switch elements T01, T03, and T05 are turned on. ) is turned off. In the first period INI, the driving element DT is turned on, and the light emitting element EL is not driven.

During the first period (INI), main nodes (n1 to n04) of the pixel circuit are initialized. At the end of the first period (INI), the voltage of the first and second nodes (n1, n2) is initialized to the pixel driving voltage (VDDEL), and the voltage of the fourth node (n04) is initialized to the initialization voltage (Vini). It is initialized.

Referring to FIGS. 17, 18, and 19B, during the second period (SAMP), the data voltage (Vdata) of the pixel data is applied to the third node (n3) and the pixel data is written to the subpixel, and at the same time, the driving element ( The threshold voltage (Vth) of DT) is sampled and stored in the capacitor (Cst).

During the second period (SAMP), the voltage of the first and third gate signals (SCAN1, SCAN2) is the gate high voltage (VGH), while the voltage of the second and fourth gate signals (EM1, EM2) is the gate high voltage (VGH). Low voltage (VGL). Accordingly, during the second period (SAMP), the second, fourth, fifth, and sixth switch elements T01, T04, and T05 are turned on, and the first, third, and seventh switch elements T01 , T03, T07) are turned off. During the second period SAMP, the driving element DT is turned off when the gate-source voltage Vgs is lower than the threshold voltage, and the light emitting element EL is not driven.

At the end of the second period (SAMP), the voltage of the third node (n3) is the data voltage (Vdata), and the voltages of the first and second nodes (n1, n2, and n4) are Vdata-Vth. Here, 'Vth' is the threshold voltage of the driving element (DT). During the second period (SAMP), the voltage of the fourth node (n04) maintains the initialization voltage (Vini). The capacitor Cst stores (Vdata+Vth)-Vini at the end of the second period SAMP.

Referring to FIGS. 17, 18, and 19C, the voltage of the third node (n3) is set to the initialization voltage (Vini) during the third period (PRG).

During the third period PRG, the voltage of the second gate signal EM1 is the gate high voltage VGH, while the voltages of the other gate signals SCAN1, SCAN2, and EM2 are the gate low voltage VGL. Accordingly, during the third period PRG, the first and third switch elements T01 and T03 are turned on, and the other switch elements T02, T04, T05, and T06 are turned off. At the end of the third period (PRG), the voltage of the second node (n2) is Vdata+Vth. Since the third node (n3) and the fourth node (n04) are connected during the third period (PRG), the voltages of the third and fourth nodes (n3, n04) are initialized at the end of the third period (PRG). It is voltage (Vini).

Referring to FIGS. 17, 18, and 19D, during the fourth period (EMIS), the voltage of the second and fourth gate signals (EM1, EM2) is the gate high voltage (VGH), while the other gate signals ( The voltage of SCAN1, SCAN2) is the gate low voltage (VGL). Accordingly, during the fourth period (EMIS), the first, third, and sixth switch elements (T01, T03, and T06) are turned on, and the other switch elements (T02, T04, and T05) are turned off. .

The current flowing through the light emitting device (EL) is adjusted according to the gate-source voltage (Vgs) of the driving device (DT). During the fourth period (EMIS), the current (I) flowing to the light emitting element (EL) is am. By this current (I), the voltage of the third node, the second gate electrode (BG) of the driving element (DT), and the fourth nodes (n04) change to the anode voltage (Voled) of the light emitting element (EL), The voltage of the second node (n2) changes to Vdata+Vth+Voled-Vini. Accordingly, the voltage (Vgs) between the gate and source of the driving device (DT) during the fourth period (EMIS) is Vgs = Vdata + Vth - Vini.

As can be seen from FIGS. 17 to 19D, the pixel circuit shown in FIG. 17 is connected to the second gate electrode (BG) of the driving element (DT) and the third node (n3) during the second period (SAMP). This can prevent the on-state current of the driving device DT from decreasing during the second period SAMP. In the pixel circuit shown in FIG. 17, the subthreshold slope of the driving element DT is lowered during the fourth period (EMIS), as can be seen from the curve of "Source contact TR" in FIG. 20, resulting in low gray level expression. It can be improved.

In FIG. 20, the curve of “Source contact TR” is the drain-to-source current (Ids) relative to the gate-to-source voltage (Vgs) of the driving element (DT) during the fourth period (EMIS). “Single gate TR” is the drain-source current (Ids) relative to the gate-source voltage (Vgs) of a three-electrode driving device without a second gate electrode.

FIGS. 21 and 22 are diagrams showing the cross-sectional structures of the driving element DT and the first switch element T01 of the pixel circuit shown in FIG. 17.

Referring to FIGS. 21 and 22 , the semiconductor patterns ACT01 and ACT02 for forming channels of the driving element DT and the first switch element T01 may be formed of an oxide semiconductor. In this case, the fifth and sixth insulating layers (BUF2, GI) in contact with the semiconductor patterns (ACT01, ACT02) are preferably formed of an oxide, for example, silicon oxide (SiOx). The first to fourth insulating layers BUF1 to ILD3 and the seventh and eighth insulating layers ILD4 and ILD5 may be formed of silicon nitride (SiNx) or silicon oxide (SiOx).

The driving element DT includes a first semiconductor pattern ACT01 disposed on the fifth insulating layer BUF2, a first gate electrode TG01 disposed on the sixth insulating layer GI, and an eighth insulating layer ILD5. ), first and second source/drain electrode patterns SD01 and SD02 disposed on the third insulating layer ILD2, and a second gate electrode BG disposed on the third insulating layer ILD2. The first gate electrode TG01 overlaps the first semiconductor pattern ACT01 with the sixth insulating layer GI interposed therebetween. The second gate electrode BG overlaps the first semiconductor pattern ACT01 with the fourth and fifth insulating layers ILD3 and BUF2 interposed therebetween.

In the driving element DT, the first source/drain electrode pattern SD01 is connected to one side of the upper surface of the first semiconductor pattern ACT01 through the first contact hole penetrating the sixth to eighth insulating layers GI to ILD5. is contacted. The second source/drain electrode pattern SD02 is in contact with the other upper surface of the first semiconductor pattern ACT01 through the second contact hole penetrating the sixth to eighth insulating layers GI to ILD5.

The first switch element T01 includes a second semiconductor pattern ACT02 disposed on the fifth insulating layer BUF2, a gate electrode TG02 disposed on the sixth insulating layer GI, and an eighth insulating layer ( It includes third and fourth source/drain electrode patterns SD03 and SD04 disposed on ILD5). The gate electrode TG02 overlaps the second semiconductor pattern ACT02 with the sixth insulating layer GI interposed therebetween.

In the first switch element T01, the third source/drain electrode pattern SD3 is connected to the second contact hole of the driving element DT through the third contact hole penetrating the fourth to eighth insulating layers ILD3 to ILD5. It contacts the upper surface of the gate electrode BG and one side of the upper surface of the second semiconductor pattern ACT02 through the fourth contact hole penetrating the sixth to eighth insulating layers GI to ILD5. The fourth source/drain electrode pattern SD04 is in contact with the other upper surface of the second semiconductor pattern ACT02 through the fifth contact hole penetrating the sixth to eighth insulating layers GI to ILD5.

As shown in FIG. 22 , bottom metal patterns LS01 may be disposed below the first switch elements T01. The bottom metal pattern LS01 is disposed on the second insulating layer ILD1 below the first switch element T01 and overlaps the second semiconductor pattern ACT02. The second gate signal EM2 may be applied to the bottom metal pattern LS01 or may be floating. The second gate signal EM may be applied to the second bottom metal pattern LS2 or may be floated.

Figure 23 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention. In FIG. 23, components that are substantially the same as those of the above-described third embodiment are given the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 23, the pixel circuit includes a light emitting element (EL), a driving element (DT) that drives the light emitting element (EL), a plurality of switch elements (PT01 to PT06), and a capacitor (Cst). Each of the driving element (DT), the second switch element (T02), and the fourth switch element (T04) may be implemented as an n-channel oxide TFT. Each of the first switch element (PT01), the third switch element (PT03), the fifth switch element (PT05), and the sixth switch element (PT06) may be implemented as a p-channel LTPS TFT.

The first switch element PT01 is connected between the third node n3 and the second gate electrode BG of the driving element DT. The first switch element PT01 is turned on in response to the gate low voltage VGL of the second gate signal EM1 to connect the third node n3 to the second gate electrode BG of the driving element DT. Connect. The first switch element PT01 includes a first electrode connected to the third node n3, a gate electrode connected to the second gate line GL2 to which the second gate signal EM1 is applied, and a second electrode of the driving element DT. 2 It includes a second electrode connected to the gate electrode (BG).

The third switch element PT03 is connected between the third node n3 and the fourth node n04. The third switch element PT04 is turned on in response to the gate low voltage VGL of the second gate signal EM1 to connect the third node n3 to the fourth node n04. The third switch element PT03 includes a first electrode connected to the third node n3, a gate electrode connected to the second gate line GL2, and a second electrode connected to the fourth node n04.

The fifth switch element PT05 is connected between the data line DL and the third node n3. The fifth switch element PT05 is turned on in response to the gate low voltage VGL of the third gate signal SCAN2 and connects the data line DL to which the data voltage Vdata is applied to the third node n3. Connect. The fifth switch element PT05 includes a first electrode connected to the data line DL, a gate electrode connected to the third gate line GL3 to which the third gate signal SCAN2 is applied, and a third node connected to n3. Includes a second electrode.

The sixth switch element PT06 is connected between the first constant voltage node PL1 and the first node n1. The sixth switch element PT06 is turned on in response to the gate low voltage VGL of the fourth gate signal EM2 to connect the first constant voltage node PL1 to which the pixel driving voltage VDDEL is applied to the first node ( Connect to n1). The sixth switch element PT06 includes a first electrode connected to the first constant voltage node PL1, a gate electrode connected to the fourth gate line GL4 to which the fourth gate signal EM2 is applied, and a first node n1. It includes a second electrode connected to.

The pixel circuit shown in FIG. 23 is in the order of the first period (INI), the second period (SAMP), the third period (PRG), and the fourth period (EMIS) as shown in FIGS. 24 to 25D. It can be driven.

Referring to FIG. 24, the first period (INI), the second period (SAMP), the third period (PRG), and the fourth period (EMIS) are in the waveforms of the gate signals (SCAN1, SCAN2, EM1, EM2). can be determined by A floating time in which all gate signals SCAN1, SCAN2, EM1, and EM2 are at the gate low voltage VGL may be set between the second period SAMP and the third period PRG.

The first gate signal SCAN1 includes pulses of the gate high voltage VGH generated during the first period INI and the second period SAMP. The voltage of the first gate signal SCAN1 is the gate low voltage VGL during the third period PRG and the fourth period EMIS. The second and fourth switch elements T2 and T4 are turned on in response to the gate high voltage VGH of the first gate signal SCAN1 and are turned on during the first period INI and the second period SAMP. state, and is off during the third and fourth periods (PRG, EMIS).

The third gate signal SCAN2 includes a pulse of the gate low voltage VGL generated in synchronization with the data voltage Vdata during the second period SAMP. The voltage of the third gate signal SCAN2 is the gate high voltage VGL during the first, third, and fourth periods (INI, PRG, EMIS). The fifth switch element (PT05) is turned on in response to the gate low voltage (VGL) of the second gate signal (SCAN2) and is in the on state for the second period (SAMP), and is switched on in the first, third and fourth periods ( INI, PRG, EMIS) is in the off state.

The second gate signal EM1 includes pulses of the gate high voltage VGH generated during the first and second periods INI and SAMP. The voltage of the second gate signal EM1 is the gate low voltage VGL during the third and fourth periods PRG and EMIS. The first and third switch elements PT01 and PT03 are turned on in response to the gate low voltage VGL of the second gate signal EM1 and are turned on during the third and fourth periods PRG and EMIS. , is off during the first and second periods (INI, SAMP).

The fourth gate signal EM2 includes pulses of the gate high voltage VGH generated during the second and third periods SAMP and PRG. The voltage of the fourth gate signal EM2 is the gate low voltage VGH during the first and fourth periods INI and EMIS. The sixth switch element (PT06) is turned on in response to the gate low voltage (VGL) of the fourth gate signal (EM2) and is turned on during the first and fourth periods (INI, EMIS), and is switched on for the second and third periods (INI, EMIS). It is off during the period (SAMP, PRG).

FIGS. 25A to 25D are circuit diagrams showing the operation of the pixel circuit shown in FIG. 23 step by period. FIG. 25A is a circuit diagram showing a current path flowing through a pixel circuit in a first period (INI). Figure 25b is a circuit diagram showing the current path flowing through the pixel circuit in the second period (SAMP). FIG. 25C is a circuit diagram showing a current path flowing through a pixel circuit in the third period (PRG). FIG. 25D is a circuit diagram showing a current path flowing through a pixel circuit in the fourth period (EMIS).

23, 24, and 25A, the voltage of the first, second, and third gate signals SCAN1, EM1, and SCAN2 during the first period INI is the gate high voltage VGH, while the voltage of the first, second, and third gate signals SCAN1, EM1, and SCAN2 is the gate high voltage VGH. 4 The voltage of the gate signal (EM2) is the gate low voltage (VGL). Accordingly, during the first period, the second, fourth, and sixth switch elements T02, T04, and PT06 are turned on, and the first, third, and fifth switch elements PT01, PT03, and PT06 are turned on. ) is turned off.

During the first period (INI), main nodes (n1 to n04) of the pixel circuit are initialized. At the end of the first period (INI), the voltage of the first and second nodes (n1, n2) is initialized to the pixel driving voltage (VDDEL), and the voltage of the fourth node (n04) is initialized to the initialization voltage (Vini). It is initialized.

Referring to FIGS. 23, 24, and 25B, during the second period (SAMP), the data voltage (Vdata) of the pixel data is applied to the third node (n3) and the pixel data is written to the subpixel, and at the same time, the driving element ( The threshold voltage (Vth) of DT) is sampled and stored in the capacitor (Cst).

During the second period (SAMP), the voltage of the first, second, and fourth gate signals (SCAN1, EM1, EM2) is the gate high voltage (VGH), while the voltage of the third gate signal (SCAN2) is the gate high voltage (VGH). Low voltage (VGL). Accordingly, during the second period (SAMP), the second, fourth, and fifth switch elements (T02, T04, and T05) are turned on, and the first, third, and sixth switch elements (PT01, PT03, PT06) is turned off.

At the end of the second period (SAMP), the voltage of the third node (n3) is the data voltage (Vdata), and the voltages of the first and second nodes (n1, n2) are Vdata-Vth. Here, 'Vth' is the threshold voltage of the driving element (DT). In the second period (SAMP), the voltage of the fourth node (n04) maintains the initialization voltage (Vini).

Referring to FIGS. 23, 24, and 25C, the voltage of the third node (n3) is set to the initialization voltage (Vini) during the third period (PRG).

During the third period PRG, the voltages of the third and fourth gate signals SCAN2 and EM2 are the gate high voltage VGH, while the voltages of the first and second gate signals SCAN1 and EM1 are the gate high voltages VGH. Low voltage (VGL). Accordingly, during the third period PRG, the first and third switch elements PT01 and PT03 are turned on, and the second, fourth, fifth and sixth switch elements T02, T04, PT05, and PT06 are turned on. ) is turned off. At the end of the third period (PRG), the voltage of the second node (n2) is Vdata+Vth, and the voltage of the third and fourth nodes (n3, n04) is the initialization voltage (Vini).

Referring to FIGS. 23, 24, and 25D, during the fourth period (EMIS), the voltage of the first, second, and fourth gate signals (SCAN1, EM1, and EM2) is the gate low voltage (VGL). The voltage of the third gate signal (SCAN2) is the gate high voltage (VGL). Accordingly, during the fourth period (EMIS), the first, third, and sixth switch elements (PT01, PT03, and PT06) are turned on, and the second, fourth, and fifth switch elements (T02, T04) are turned on. , PT05) is turned off.

The current flowing through the light emitting device (EL) is adjusted according to the gate-source voltage (Vgs) of the driving device (DT). During the fourth period (EMIS), the current (I) flowing to the light emitting element (EL) is am. By this current (I), the voltage of the third and fourth nodes (n3, n04) and the second gate electrode (BG) of the driving element (DT) changes to the anode voltage (Voled) of the light emitting element (EL), The voltage of the second node (n2) changes to Vdata+Vth+Voled-Vini. Accordingly, the voltage (Vgs) between the gate and source of the driving device (DT) during the fourth period (EMIS) is Vgs = Vdata + Vth - Vini.

As can be seen from FIGS. 23 to 25D, the pixel circuit shown in FIG. 23 is connected to the second gate electrode (BG) of the driving element (DT) and the third node (n3) during the second period (SAMP). This can prevent the on-state current of the driving device DT from decreasing during the second period SAMP. In the pixel circuit shown in FIG. 23, the subthreshold slope of the driving element DT is lowered during the fourth period EMIS, thereby improving low gray level expression.

FIGS. 26 to 29 are diagrams showing the cross-sectional structures of the driving element (DT) and the first switch element (PT01) of the pixel circuit shown in FIG. 23. Since the cross-sectional structure of the driving element DT is substantially the same as that of FIGS. 21 and 22 of the third embodiment described above, detailed description thereof will be omitted.

Referring to FIGS. 26 and 27 , the semiconductor pattern ACT01 for forming the channel of the driving element DT may be formed of an oxide semiconductor. In this case, the fifth and sixth insulating layers (BUF2, GI2) in contact with the semiconductor pattern (ACT01) are preferably formed of an oxide, for example, silicon oxide (SiOx). The first to fourth insulating layers BUF1 to ILD3 and the seventh and eighth insulating layers ILD4 and ILD5 may be formed of silicon nitride (SiNx) or silicon oxide (SiOx).

The semiconductor pattern PACT2 for forming the channel of the first switch element PT01 may be formed of polycrystalline silicon.

The first switch element PT01 includes a semiconductor pattern PACT2 disposed on the first insulating layer BUF1, a gate electrode TG02 disposed on the second insulating layer GI1, and a fourth insulating layer ILD3. It includes third and fourth source/drain electrode patterns SD03 and SD04 disposed on the electrode. The gate electrode TG02 overlaps the semiconductor pattern PACT2 with the second insulating layer GI1 therebetween.

In the first switch element PT01, the third source/drain electrode pattern SD03 is connected to the second gate electrode BG of the driving element DT through the third contact hole penetrating the fourth insulating layer ILD3. It contacts the other side of the upper surface and contacts one side of the upper surface of the semiconductor pattern (PACT2) through the fourth contact hole penetrating the second to fourth insulating layers (GI1, ILD2, ILD3). The fourth source/drain electrode pattern SD04 is in contact with the other upper surface of the semiconductor pattern PACT2 through the fifth contact hole penetrating the second to fourth insulating layers GI1, ILD2, and ILD3.

As shown in FIG. 27, the bottom metal pattern LS may be disposed below the driving element DT. The bottom metal pattern LS is disposed on the second insulating layer GI1 below the driving element DT and overlaps the second gate electrode BG of the driving element DT.

28 and 29, the first switch element PT01 includes a semiconductor pattern PACT2 disposed on the first insulating layer BUF1 and a gate electrode TG02 disposed on the second insulating layer GI1. , and third and fourth source/drain electrode patterns SD03 and SD04 disposed on the eighth insulating layer ILD5.

In the first switch element PT01, the third source/drain electrode pattern SD03 is connected to the second gate of the driving element DT through the third contact hole penetrating the fourth to eighth insulating layers ILD3 to ILD5. It contacts the other upper surface of the electrode BG and contacts one upper surface of the semiconductor pattern PACT2 through the fourth contact hole penetrating the second to eighth insulating layers GI1 to ILD5. The fourth source/drain electrode pattern SD04 is in contact with the other upper surface of the semiconductor pattern PACT2 through the fifth contact hole penetrating the second to eighth insulating layers GI1 to LD5.

As shown in FIG. 29, the bottom metal pattern LS may be disposed below the driving element DT. The bottom metal pattern LS is disposed on the second insulating layer GI1 below the driving element DT and overlaps the second gate electrode BG.

Since the contents of the specification described in the problem to be solved, the means to solve the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display panel 110: data driver
120: Gate driver 130: Timing controller
140: power unit 200: host system
EL: Light emitting element DT: Driving element
T1~T7, T01~T06, PT2, PT4, PT6, PT7, PT01, PT03, PT05, PT06: Switch elements
Cst: capacitor

Claims (18)

A driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node;
a light emitting device including an anode electrode connected to a fifth node, and a cathode electrode to which a pixel base voltage is applied;
a first switch element connected between the first node and the fourth node;
a second switch element connected between the third node and the fourth node;
a third switch element connected between the first node and the second node; and
A pixel circuit including a fourth switch element connected between the third node and the fifth node. According to claim 1,
a capacitor connected between the second node and the fifth node;
a fifth switch element connected between the fifth node and a third constant voltage node to which an initialization voltage is applied;
a sixth switch element connected between a data line to which a data voltage is applied and the third node; and
A pixel circuit further comprising a first constant voltage node to which a pixel driving voltage is applied, and a seventh switch element connected between the first nodes. According to claim 2,
The first switch element includes a first electrode connected to the first node, a gate electrode connected to a first gate line to which a first gate signal is applied, and a second electrode connected to the fourth node,
The second switch element includes a first electrode connected to the third node, a gate electrode connected to a second gate line to which a second gate signal is applied, and a second electrode connected to the fourth node,
The third switch element includes a first electrode connected to the second node, a gate electrode connected to the first gate line, and a second electrode connected to the first node,
The fourth switch element includes a first electrode connected to the third node, a gate electrode connected to the second gate line, and a second electrode connected to the fifth node,
The fifth switch element includes a first electrode connected to the fifth node, a gate electrode connected to the first gate line, and a second electrode connected to the third constant voltage node,
The sixth switch element includes a first electrode connected to the data line, a gate electrode connected to a third gate line to which a third gate signal is applied, and a second electrode connected to the third node,
The seventh switch element is a pixel circuit including a first electrode connected to the first constant voltage node, a gate electrode connected to a fourth gate line to which a fourth gate signal is applied, and a second electrode connected to the first node. According to claim 3,
Each of the first to seventh switch elements and the driving element is an n-channel transistor,
Each of the first to seventh switch elements is turned on in response to the gate high voltage and turned off in response to the gate low voltage,
The voltage of the first gate signal is the gate high voltage during the first and second periods, and the gate low voltage during the third and fourth periods,
The voltage of the second gate signal is the gate low voltage during the first period and the second period, and the gate high voltage during the third period and the fourth period,
The voltage of the third gate signal is the gate high voltage during the second period, and the gate low voltage during the first period, the third period, and the fourth period,
A pixel circuit in which the voltage of the fourth gate signal is the gate low voltage during the second period and the third period, and the gate high voltage during the first period and the fourth period. According to claim 3,
Each of the driving element, the first switch element, the third switch element, and the fifth switch element is an n-channel transistor, and the second switch element, the fourth switch element, the sixth switch element, and the first switch element are n-channel transistors. Each of the 7 switch elements is a p-channel transistor,
Each of the first switch element, the third switch element, and the fifth switch element is turned on in response to a gate high voltage and turned off in response to a gate low voltage,
Each of the second switch element, the fourth switch element, the sixth switch element, and the seventh switch element is turned on in response to the gate low voltage and turned off in response to the gate high voltage,
The voltage of the first gate signal is the gate high voltage during the first and second periods, and the gate low voltage during the third and fourth periods,
The voltage of the second gate signal is the gate high voltage during the first period and the second period, and the gate low voltage during the third period and the fourth period,
The voltage of the third gate signal is the gate low voltage during the second period, the gate high voltage during the first period, the third period, and the fourth period,
The voltage of the fourth gate signal is the gate high voltage during the second period and the third period, and the gate low voltage during the first period and the fourth period. A driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node;
a light emitting element including an anode electrode connected to a fourth node, and a cathode electrode to which a pixel base voltage is applied;
a first switch element connected between the third node and a second gate electrode of the driving element;
a second switch element connected between the first node and the second node; and
A pixel circuit including a third switch element connected between the third node and the fourth node. According to claim 6,
a capacitor connected between the second node and the fourth node;
a fourth switch element connected between the fourth node and a third constant voltage node to which an initialization voltage is applied;
a fifth switch element connected between a data line to which a data voltage is applied and the third node; and
A pixel circuit further comprising a first constant voltage node to which a pixel driving voltage is applied, and a sixth switch element connected between the first nodes. According to claim 7,
The first switch element includes a first electrode connected to the third node, a gate electrode connected to a second gate line to which a second gate signal is applied, and a second electrode connected to the second gate electrode of the driving element,
The second switch element includes a first electrode connected to the second node, a gate electrode connected to a first gate line to which a first gate signal is applied, and a second electrode connected to the first node,
The third switch element includes a first electrode connected to the third node, a gate electrode connected to the second gate line, and a second electrode connected to the fourth node,
The fourth switch element includes a first electrode connected to the fourth node, a gate electrode connected to the first gate line, and a second electrode connected to the third constant voltage node,
The fifth switch element includes a first electrode connected to the data line, a gate electrode connected to a third gate line to which a third gate signal is applied, and a second electrode connected to the third node,
The sixth switch element is a pixel circuit including a first electrode connected to the first constant voltage node, a gate electrode connected to a fourth gate line to which a fourth gate signal is applied, and a second electrode connected to the first node. According to claim 8,
Each of the first to sixth switch elements and the driving element is an n-channel transistor,
Each of the first to sixth switch elements is turned on in response to the gate high voltage and turned off in response to the gate low voltage,
The voltage of the first gate signal is the gate high voltage during the first and second periods, and the gate low voltage during the third and fourth periods,
The voltage of the second gate signal is the gate low voltage during the first period and the second period, and the gate high voltage during the third period and the fourth period,
The voltage of the third gate signal is the gate high voltage during the second period, and the gate low voltage during the first period, the third period, and the fourth period,
A pixel circuit in which the voltage of the fourth gate signal is the gate low voltage during the second period and the third period, and the gate high voltage during the first period and the fourth period. According to claim 8,
Each of the driving element, the first switch element, the third switch element, the fifth switch element, and the sixth switch element is a p-channel transistor, and the driving element, the second switch element, and the fourth switch are each a p-channel transistor. Each element is an n-channel transistor,
Each of the first switch element, the third switch element, the fifth switch element, and the sixth switch element is turned on in response to a gate low voltage and turned off in response to a gate high voltage,
Each of the second switch element and the fourth switch element is turned on in response to the gate high voltage and turned off in response to the gate low voltage,
The voltage of the first gate signal is the gate high voltage during the first and second periods, and the gate low voltage during the third and fourth periods,
The voltage of the second gate signal is the gate high voltage during the first period and the second period, and the gate low voltage during the third period and the fourth period,
The voltage of the third gate signal is the gate low voltage during the second period, the gate high voltage during the first period, the third period, and the fourth period,
The voltage of the fourth gate signal is the gate high voltage during the second period and the third period, and the gate low voltage during the first period and the fourth period. A display panel including a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of subpixels;
a display panel driving circuit that writes pixel data of an input image to the display panel;
Each of the subpixels is,
A driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node;
a light emitting device including an anode electrode connected to a fifth node, and a cathode electrode to which a pixel base voltage is applied;
a first switch element connected between the first node and the fourth node;
a second switch element connected between the third node and the fourth node;
a third switch element connected between the first node and the second node; and
A display device including a fourth switch element connected between the third node and the fifth node. According to claim 11,
The display panel is,
a second insulating layer disposed on the first insulating layer;
a third insulating layer disposed on the second insulating layer;
a fourth insulating layer disposed on the third insulating layer;
a fifth insulating layer disposed on the fourth insulating layer;
a sixth insulating layer disposed on the fifth insulating layer;
a seventh insulating layer disposed on the sixth insulating layer; and
A display device including an eighth insulating layer disposed on the seventh insulating layer. According to claim 12,
The first switch element is,
a first oxide semiconductor pattern disposed on the fifth insulating layer;
a gate electrode disposed on the sixth insulating layer and overlapping the first oxide semiconductor pattern;
a first source/drain electrode pattern disposed on the eighth insulating layer and in contact with one side of the upper surface of the first semiconductor pattern through a first contact hole penetrating the sixth to eighth insulating layers; and
Contacting the other upper surface of the first oxide semiconductor pattern through a second contact hole penetrating the sixth to eighth insulating layers, and contacting the driving element through a third contact hole penetrating the fifth to eighth insulating layers. A display device including a second source/drain electrode pattern in contact with one side of the upper surface of the second gate electrode. According to claim 13,
The driving element is,
a second oxide semiconductor pattern disposed on the fifth insulating layer;
the first gate electrode disposed on the sixth insulating layer and overlapping the second oxide semiconductor pattern;
a third source/drain electrode pattern disposed on the eighth insulating layer and in contact with one side of the upper surface of the second oxide semiconductor pattern through a fourth contact hole penetrating the sixth to eighth insulating layers;
a fourth source/drain electrode pattern disposed on the eighth insulating layer and in contact with the other upper surface of the second oxide semiconductor pattern through a fifth contact hole penetrating the sixth to eighth insulating layers; and
A display device including a second gate electrode disposed on the third insulating layer and overlapping the second oxide semiconductor pattern. According to claim 14,
The second switch element is,
a third oxide semiconductor pattern disposed on the fifth insulating layer;
a gate electrode disposed on the sixth insulating layer and overlapping the third oxide semiconductor pattern;
It is disposed on the eighth insulating layer and contacts the other upper surface of the second gate electrode of the driving element through a sixth contact hole penetrating the fourth to eighth insulating layers, and the sixth to eighth insulating layers a fifth source/drain electrode pattern contacted to one side of the upper surface of the third oxide semiconductor pattern through a seventh contact hole penetrating through them; and
A display device including a sixth source/drain electrode pattern disposed on the eighth insulating layer and in contact with the other upper surface of the third oxide semiconductor pattern through an eighth contact hole penetrating the sixth to eighth insulating layers. . According to claim 14,
The second switch element is
a third semiconductor pattern disposed on the first insulating layer and including polycrystalline silicon;
a gate electrode disposed on the second insulating layer and overlapping the third semiconductor pattern;
A second contact layer is disposed on the fourth insulating layer and contacts the other upper surface of the second gate electrode of the driving element through a sixth contact hole penetrating the fourth insulating layer, and penetrating the second to fourth insulating layers. 7 A fifth source/drain electrode pattern contacting one side of the upper surface of the third semiconductor pattern through a contact hole; and
A display device comprising a sixth source/drain electrode pattern disposed on the fourth insulating layer and in contact with the other upper surface of the third semiconductor pattern through an eighth contact hole penetrating the second to fourth insulating layers. According to claim 14,
The second switch element is
a third semiconductor pattern disposed on the first insulating layer and including polycrystalline silicon;
a gate electrode disposed on the second insulating layer and overlapping the third semiconductor pattern;
It is disposed on the eighth insulating layer and contacts the other upper surface of the second gate electrode of the driving element through a sixth contact hole penetrating the fourth to eighth insulating layers, and the second to eighth insulating layers a fifth source/drain electrode pattern contacting one side of the upper surface of the third semiconductor pattern through a seventh contact hole penetrating the third semiconductor pattern; and
A display device comprising a sixth source/drain electrode pattern disposed on the eighth insulating layer and in contact with the other upper surface of the third semiconductor pattern through an eighth contact hole penetrating the second to eighth insulating layers. A display panel including a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of subpixels;
a display panel driving circuit that writes pixel data of an input image to the display panel;
Each of the subpixels is,
A driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node;
A light emitting element including an anode electrode connected to a fourth node, and a cathode electrode to which a pixel base voltage is applied;
a first switch element connected between the third node and a second gate electrode of the driving element;
a second switch element connected between the first node and the second node; and
A display device including a third switch element connected between the third node and the fourth node.