KR20240074901A - Method to improve profile control during selectively etching of silicon nitride spacers - Google Patents

Abstract

The cyclic etching method includes i) exposing the SiN layer covering the structure on the substrate to a plasma of hydrofluorocarbon (HFC) in a reaction chamber to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer. _{wherein the} HFC has _the formula C exposing the polymer layer to a plasma of an inert gas, wherein the plasma of the inert gas removes the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on the etch front, and iii) the SiN layer on the etch front is selectively and repeating steps i) and steps ii) until removed, thereby forming a substantially vertically upright SiN spacer comprising a SiN layer on the sidewall of the structure.

Description

METHOD TO IMPROVE PROFILE CONTROL DURING SELECTIVELY ETCHING OF SILICON NITRIDE SPACERS}

Cross-reference to related applications

This application claims the benefit of U.S. Patent Application No. 16/265,782, filed February 1, 2019, the entire contents of which are incorporated herein by reference for all purposes.

Technology field

A cyclic atomic layer etch (ALE) method for spacer patterning in semiconductor applications is disclosed. In particular, a cyclic ALE process is disclosed to form vertically erected silicon nitride (SiN) spacers using hydrofluorocarbon (HFC) gas. The disclosed HFC gases have _{the formula C}

The continued size reduction of semiconductor devices poses more and more challenges to the semiconductor manufacturing process. For technology nodes below 14 nm, one of the most important steps is spacer etching. This requires a completely anisotropic etch (no critical dimension (CD) loss) without damaging or consuming exposed materials such as silicon and silicon oxide. This is usually performed by plasma etching using fluorocarbon-based chemistry. However, with increasing aspect ratios associated with advanced technology nodes, conventional etching processes allow for etching with profile control (e.g. footing and surface roughness), no damage to the underlying layer, CD control, etc. Specifications could not be achieved.

In industry, the standard etching process for SiN etching is HFC in combination with an oxidizing agent and/or noble gas, for example an oxidizing agent (e.g. O ₂ ), a noble gas (e.g. Ar or He) and sometimes additional F or CH ₃ F combined with a H-containing gas (eg CH ₄ or CF ₄ ) is used. However, it is difficult to maintain a balance between etch selectivity, profile control and damage to the underlying layer. Previous patents on SiN etching claimed to selectively etch SiN spacers using different HFCs without quantitative information about profile control.

U.S. Patent No. 20130105916A1, issued to Chang et al., discloses a highly selective nitride etch process involving anisotropic etching of SiN _x using HFC plasma to form various thicknesses of SiN _x , SiO ₂ and HFC polymers on Si. . The process is a selective etching of SiN _x using HFC having the formula C _x H _y F _z (where x is 3 to 6 and y > z), which is saturated or unsaturated, linear or cyclic. However, Chang et al. did not disclose any discussion about profile control such as footing control. The etching process disclosed by Chang et al. is not a cyclic process.

US Patent No. 20110068086A1, issued to Suzuki et al., involves plasma etching a target using only saturated molecules, linear or cyclic HFCs, C _x H _y F _z (x is 3 to 5 and y > z). Disclosed is a plasma etching method on a planar wafer. More specifically, Suzuki et al. disclose selective etching of SiN _x over SiO ₂ by using specific HFCs under plasma conditions on planar wafers rather than patterned wafers containing semiconductor structures. As illustrated in the examples, Suzuki et al. etched SiN planar wafers and SiO planar wafers using 2,2-difluoro-n-butane.

US Patent No. 8,501,630 or US Patent No. 20120077347A1 issued to Metz et al. discloses a plasma etching method for selectively etching a substrate. The plasma etching process uses a process composition having a process gas containing C, H and F and a non-oxygen-containing additive gas. The process gas includes CH ₃ F, CHF ₃ , CH ₂ F ₂ or any combination of two or more of these. The plasma etching process disclosed by Metz et al. is not a cyclic process.

US Patent No. 20010005634A1 issued to Kajiwara discloses a dry etching method for forming contact holes by highly selective etching of SiN on SiO ₂ using CH ₂ F ₂ as an etching gas.

U.S. Patent No. 20130105996, issued to Brink et al., discloses a method for a nitrogen-containing dielectric layer contained in a stack comprising a nitrogen-containing dielectric layer formed from bottom to top on a substrate, a layer of interconnection level dielectric material, and a hard mask layer. The energy etching process is initiated. The nitrogen-containing dielectric layer was plasma etched using HFC with C _x H _y F _z (x is 3 to 6 and y > z). Brink et al. did not mention selectivity for Si or SiO ₂ .

US Patent No. 20140273292A1, issued to Posseme et al., includes depositing a SiN layer over an exposed silicon-containing layer disposed over a substrate and an at least partially formed gate stack; modifying a portion of the SiN layer by exposing the SiN layer to a substantially fluorine-free hydrogen or helium containing plasma; and removing the modified portion of the SiN layer by performing a wet cleaning process to form a SiN spacer. In one embodiment, Posseme et al. disclose that the SiN layer is etched using an HFC-containing gas such as CH ₂ F ₂ , CH ₄ , CHF ₃ .

US Patent No. 20150270140A1 issued to Gupta et al. covers Si, Ti, Ta, W, Al, Pd, Ir, Co, Fe, B, Cu, Ni, Pt, Ru, Mn, Mg, Cr, Au, and alloys thereof. , discloses atomic layer or cyclic plasma etch chemistries and processes for etching films containing their oxides, their nitrides, and combinations thereof. Examples include etching Fe and Pd with Cl ₂ and ethanol (EtOH), etching Ni, Co, Pd, or Fe with Cl ₂ and acetylacetonate (Acac).

US Patent No. 20160293438A1 to Zhou et al. discloses a cyclic spacer etching process with improved profile control, but the method is based on NF ₃ /NH ₃ plasma rather than HFC gas.

International Patent Publication No. WO2018/044713A1 to Sherpa et al. discloses that the process gases include H and optionally noble gases; A first step containing H ₂ , or H ₂ and Ar; A method for quasi-atomic layer etching of SiN is disclosed, comprising a second step where the process gases contain N, F, O, and optionally rare elements NF ₃ , O ₂ and Ar.

U.S. Patent No. _9318343B2 , issued to Ranjan et al _. , discloses SiN spacers and silicon (e.g. polycrystalline) gases using process gases containing HFC gases denoted as _C A method for improving etch selectivity during SiN spacer etching comprising a cyclic process of etching and oxidation of silicon) is disclosed. The HFC disclosed in Ranjan et al. is CH ₃ F. Ranjan et al. did not mention the profile of the spacer, such as footing and surface roughness of the spacer.

The discovery of new and novel etching elements applicable to improving profile control for etching silicon-containing spacers, such as SiN spacers, is challenging because, in applications for etching silicon-containing spacers, there is little footing, and fluorine This is because the etch profile requirements must be met, such as virtually no ride formation and achieving a smooth spacer surface after etching. Accordingly, there is a need to provide such an etching element that satisfies these requirements.

i) exposing the SiN layer covering the structure on the substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, wherein the HFC is ii) a polymer layer deposited on the _{SiN layer} having the formula _C exposing to a plasma of an inert gas, wherein the plasma of the inert gas removes the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on the etch front, and iii) the SiN layer covering the etch front is removed. A cyclic etching method is disclosed comprising repeating steps i) and step ii) until thereby forming a vertically upright SiN spacer wherein the SiN layer covers the sidewalls of the structure.

i) exposing the SiN layer covering the structure on the substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, wherein the HFC is ii) a polymer layer deposited on the _{SiN layer} having the formula _C exposing to a plasma of an inert gas, wherein the plasma of the inert gas removes the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on the etch front, and iii) the SiN layer covering the etch front is removed. cyclic etching to form a vertically upright SiN spacer, comprising repeating steps i) and step ii) until the SiN layer forms a vertically upright SiN spacer covering the sidewalls of the structure. A method is also disclosed.

i) exposing the SiN layer covering the gate stack on the substrate in a reaction chamber to a plasma of a hydrofluorocarbon (HFC) selected from the group consisting of C ₂ H ₅ F and C ₃ H ₇ F to modify the surface of the SiN layer ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, such that the plasma of the inert gas is formed on the polymer layer deposited on the SiN layer and the etch front. removing the modified surface of the SiN layer, and iii) repeating steps i) and step ii) until the SiN layer covering the etch front is removed, thereby causing the SiN layer to cover the sidewalls of the gate stack. A cyclic etching method for forming vertically upright SiN gate spacers is also disclosed, comprising forming vertically upright SiN gate spacers.

Any of the disclosed methods may include one or more of the following aspects:

· After step (i),

pumping the reaction chamber to vacuum;

purging the reaction chamber with N ₂ ;

pumping the reaction chamber to vacuum; and

further comprising introducing an inert gas into the reaction chamber to generate a plasma of the inert gas;

· After step (ii),

pumping the reaction chamber to vacuum;

purging the reaction chamber with N ₂ ;

pumping the reaction chamber to vacuum; and

further comprising introducing the HFC into the reaction chamber to generate a plasma of the HFC;

· exposing the SiN layer to a plasma of a gas mixture of HFC and an inert gas;

· At least most of the SiN layer on the sidewalls of the gate stack is not removed;

· Less than 10% of the thickness of the SiN layer on the sidewalls of the gate stack is removed;

· Less than 5% of the thickness of the SiN layer on the sidewalls of the gate stack is removed;

· Less than 1% of the thickness of the SiN layer on the sidewalls of the gate stack is removed;

· No measurable thickness reduction of the SiN layer occurs on the sidewalls of the gate stack;

· The inert gas is selected from N ₂ , Ar, Kr or Xe;

· Inert gas is Ar;

· HFC is C ₂ H ₅ F;

· HFC is C ₃ H ₇ F;

· The substrate comprises a silicon-containing material;

· The substrate is silicon;

· The structure is a gate stack;

· HFC plasma interacts with SiN to form C-rich polymers (C:F > 1);

· C-rich polymer is a polymer layer deposited on top of the SiN layer;

· HFC selectively etch the SiN layer on the structure;

· HFC selectively etch the SiN layer on the substrate;

· Infinite selectivity of SiN over structures;

· Infinite selectivity of SiN versus gate stack;

· Infinite selectivity of SiN over p-Si, SiO, SiON and SiCN;

· ALE over-etch recipe is applied;

· ALE overetch recipes range from approximately 10% ALE overetch to approximately 200% ALE overetch;

· ALE overetch recipes range from approximately 50% ALE overetch to approximately 200% ALE overetch;

· Introducing HFC gas into the reaction chamber at a flow rate ranging from approximately 1 sccm to approximately 10 slm;

· Introducing HFC gas into the reaction chamber at a flow rate ranging from approximately 1 sccm to approximately 100 sccm;

· Introducing an inert gas into the reaction chamber at a flow rate ranging from approximately 1 sccm to approximately 10 slm;

· Introducing an inert gas into the reaction chamber at a flow rate ranging from approximately 10 sccm to approximately 200 sccm;

· The reaction chamber has a pressure ranging from approximately 1 mTorr to approximately 50 Torr;

· The reaction chamber has a pressure ranging from approximately 1 mTorr to approximately 10 Torr;

· The reaction chamber has a pressure ranging from approximately 300 mTorr to approximately 1 Torr;

· The substrate temperature in the chamber ranges from approximately -110°C to approximately 2000°C;

· The substrate temperature in the chamber ranges from approximately -20°C to approximately 1000°C;

· The substrate temperature in the chamber ranges from approximately 25° C. to approximately 700° C.;

· The substrate temperature in the chamber ranges from approximately 25° C. to approximately 500° C.;

· The substrate temperature in the chamber ranges from approximately 25° C. to approximately 50° C.;

· The reaction chamber wall temperature ranges from approximately 25° C. to approximately 100° C.;

· Plasma process time varies from 0.01 to 10000 seconds;

· Plasma process time varies from 1 to 30 seconds;

· N ₂ purge time varies from 1 to 10000 seconds;

· N ₂ purge time varies from 10 to 60 seconds;

· Little footing is formed at each corner between the SiN spacer and the substrate;

· Little excess material remains near the SiN layer and substrate;

· No fluoride residues remain on vertically upright SiN spacers and etch fronts;

· The surface roughness on the surface of the vertically upright SiN spacer and the surface of the etching front after cyclic etching is improved compared to that before cyclic etching;

· The removal step of the polymer layer is an ion bombardment process;

· further comprising adding an oxygen-containing gas; and

· The oxygen-containing gas is selected from the group consisting of O ₂ , O ₃ , CO, CO ₂ , NO, NO ₂ , N ₂ O, SO ₂ , COS, H ₂ O and combinations thereof.

HFC etching gases having the formula C _x H _y F _z where x is 2 to 5 and y > z are also disclosed. The disclosed HFC etching gas includes one or more of the following aspects:

· HFCs are saturated or unsaturated, linear or cyclic HFCs;

· has a purity of approximately greater than 99% by volume;

· has a purity of approximately greater than 99.9% by volume;

· Contains less than 1% by volume of trace gaseous impurities;

· Trace gaseous impurities include water;

· Trace gaseous impurities include _CO2 ;

· Trace gaseous impurities include N ₂ ; and

· HFC etching gas has a water content of less than 20 ppmw.

Notation and nomenclature

The following detailed description and claims use a number of abbreviations, symbols, and terms that are commonly known in the art and include the following:

As used herein, the singular refers to one or more.

As used herein, in the text or in the claims, “about or around” or “approximately” means ±10% of the stated value.

As used herein, in the text or in the claims, “room temperature” means approximately 20°C to approximately 25°C.

The term “wafer” or “patterned wafer” refers to a wafer having a stack of silicon-containing films on a substrate and a patterned hardmask layer on the stack of silicon-containing films formed for pattern etching.

The term “substrate” refers to the material or materials on which the process is performed. A substrate may refer to a wafer having a material or materials on which a process is performed. The substrate may be any suitable wafer used in semiconductor, photovoltaic, flat panel, or LCD-TFT device manufacturing. The substrate may also have one or more layers of different materials already deposited in previous manufacturing steps. For example, the wafer may include a silicon layer (e.g., crystalline, amorphous, porous, etc.), a silicon-containing layer (e.g., SiO ₂ , SiN, SiON, SiCOH, etc.), a metal-containing layer (e.g., copper, cobalt, ruthenium, tungsten, platinum, palladium, nickel, ruthenium, gold, etc.), or a combination thereof. Additionally, the substrate may be planar or patterned. The substrate may be an organic patterned photoresist film. The substrate may be a dielectric material (e.g., ZrO ₂ -based material, HfO ₂ -based material, TiO ₂ -based material, rare earth oxide-based material, ternary oxide-based material, etc.) in MEMS, 3D NAND, MIM, DRAM, or FeRam device applications. It may include a layer of oxide used as an oxide layer or a nitride-based film (eg, TaN, TiN, NbN) used as an electrode. Those skilled in the art will recognize that the terms “film” or “layer” as used herein refer to the thickness of some material placed on or spread over a surface, and that such surface may be a trench or line. Throughout this specification and claims, the wafer and any associated layers on the wafer are referred to as the substrate.

The terms “pattern etching” or “patterned etching” refer to the etching of a non-planar structure, such as a stack of silicon-containing films beneath a patterned hardmask layer.

As used herein, the term “etch” or “etching” refers to an isotropic etching process and/or an anisotropic etching process. Isotropic etching processes involve a chemical reaction between an etching compound and a substrate that results in the removal of some of the material on the substrate. These types of etching processes include chemical dry etching, vapor phase chemical etching, thermal dry etching, etc. Isotropic etching processes create a lateral or horizontal etch profile within the substrate. The isotropic etching process creates depressions or horizontal depressions on the sidewalls of pre-formed openings in the substrate. The anisotropic etching process removes material only perpendicular to the surface of the substrate, which ensures accurate transfer of the mask pattern. The dry etching process may be a plasma etching process. Plasma is any gas in which a significant percentage of atoms or molecules are ionized. The plasma may be a capacitively coupled plasma (CCP) generated by a CCP system consisting essentially of two metal electrodes separated by a short distance located within a reactor. A typical CCP system is powered by a single radio-frequency (RF) power source. One of the two electrodes is connected to a power source and the other is grounded. When an electric field is created between the electrodes, the atoms become ionized and emit electrons. Electrons in the gas are accelerated by the RF field and can ionize the gas directly or indirectly by collision, producing secondary electrons. Plasma can also be called inductively coupled plasma (ICP) or transformer coupled plasma (TCP) generated by an ICP system energized by electromagnetic induction, i.e. by a current generated by a time-varying magnetic field. ) can be. ICP discharge has a relatively high electron density of the order of 10 ¹⁵ cm ^-3 . As a result, ICP discharge has wide applications in cases where high density plasma (HDP) is required. Another advantage of ICP discharges is that they are relatively contamination-free, because the electrodes are completely outside the reaction chamber. The plasma etch process creates a vertical etch profile within the substrate. The plasma etching process creates vertical openings, trenches, channel holes, gate trenches, staircase contacts, capacitor holes, and contact holes in the substrate.

The term “100% etch” means that the ALE process etches the material completely across its thickness. The term “overetch” means that the ALE process continues even after the material has been etched. For example, in the disclosed method, if one ALE recipe has an etch rate of 1 nm/cycle for the SiN layer, and the SiN layer has a thickness of 10 nm, to completely etch across the 10 nm thick SiN 10 cycles are required. This means 100% etching. If the etch cycle is set to more than 10 cycles to etch the SiN layer, the ALE is "overetched." For example, if 15 etching cycles are set to etch the SiN layer, the etch process is a 50% overetch. When setting up 20 etch cycles to etch the SiN layer, the etch process is 100% overetch.

The term “deposit” or “deposition” refers to a series of processes by which material at the atomic or molecular level is deposited as a thin film from a gaseous state (vapor) to a solid state on a wafer surface or on a substrate. A chemical reaction is involved within this process, which occurs after the creation of a plasma of reacting gases. The plasma may be a CCP as described above, generally generated by radio frequency (RF) (alternating current (AC)) or direct current (DC) discharge between two electrodes, i.e. in a space filled with reacting gases. Deposition methods may include atomic layer deposition (ALD) and chemical vapor deposition (CVD).

The term “mask” refers to a layer that resists etching. A hardmask layer may be positioned over the layer to be etched.

The term “aspect ratio” refers to the ratio of the height of a trench (or opening) to the width of the trench (or diameter of the opening).

The term “selectivity” refers to the ratio of the etch rate of one material to the etch rate of another material. The terms “selective etch” or “selectively etch” mean to etch one material more than the other material, or, in other words, to have an etch selectivity of greater than or less than 1:1 between the two materials.

Note that herein, the terms “film” and “layer” may be used interchangeably. It is understood that a film may correspond to or be related to a layer, and that a layer may refer to a film. Additionally, those skilled in the art will recognize that the terms "film" or "layer" as used herein refer to the thickness of some material placed on or spread over a surface, which may range from as large as an entire wafer to as small as a trench or line. You will realize that it exists.

Note that herein, the terms “etching compound” and “etching gas” may be used interchangeably when the etching compound is in a gaseous state at room temperature and ambient pressure. It is understood that an etching compound may correspond to or be related to an etching gas, and that an etching gas may refer to an etching compound.

Standard abbreviations for elements from the Periodic Table of the Elements are used herein. It should be understood that elements may be referred to by these abbreviations (e.g., Si refers to silicon, N refers to nitrogen, O refers to oxygen, C refers to carbon, H refers to hydrogen , F refers to fluorine, etc.).

A unique CAS registration number (i.e., “CAS”), assigned by the Chemical Abstract Service, is provided to identify the specific molecule disclosed.

Note that silicon-containing films, such as SiN and SiO, are listed throughout the specification and claims, without reference to their appropriate stoichiometry. Silicon-containing films include pure silicon (Si) layers such as crystalline Si, poly-silicon (p-Si or polycrystalline Si), or amorphous silicon; Silicon nitride (Si _k N _l ) layer; or a silicon oxide (Si _n O _m ) layer; or a mixture thereof, where k, l, m, and n range from 0.1 to 6 (inclusive). Preferably, the silicon nitride is Si _k N _l , where k and l each range from 0.5 to 1.5. More preferably, the silicon nitride is Si ₃ N ₄ . Herein, SiN in the following description may be used to denote Si _k N _l containing layers. Preferably, the silicon oxide is Si _n O _m , where n is in the range of 0.5 to 1.5 and m is in the range of 1.5 to 3.5. More preferably, the silicon oxide is SiO ₂ . Herein, SiO in the description below may be used to refer to Si _n O _m containing layers. The silicon-containing film can also be a silicon oxide-based dielectric material, such as an organic-based or silicon oxide-based low-k dielectric material, such as the Black Diamond II or III material with the formula SiOCH by Applied Materials, Inc. The silicon-containing film may also include Si _a O _b N _c , where a, b, and c range from 0.1 to 6. Silicon-containing films may also include dopants such as B, C, P, As and/or Ge.

Ranges may be expressed herein as approximately from one particular value, and/or to approximately another particular value. When such ranges are expressed, it should be understood that alternative embodiments may range from one particular value and/or to another particular value, along with all combinations within such range.

Reference herein to “one embodiment” or “an implementation” means that a particular feature, structure, or characteristic described in connection with the implementation can be included in at least one implementation of the invention. The appearances of the phrase “one implementation” in various places in the specification are not necessarily intended to refer to the same implementation, nor are they intended to indicate that a separate or alternative implementation is mutually exclusive of the other implementations. The same applies to the term “execution”.

For a better understanding of the nature and purpose of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which like elements are given identical or similar reference numerals.
1A is a cross-sectional side view of an exemplary pattern formed in the art to create SiN spacers on a base substrate;
1B is a cross-sectional side view of an exemplary SiN spacer on a base substrate with ideal etching results for SiN spacers in the art;
FIG. 1C is a cross-sectional side view of an exemplary SiN spacer on a base substrate following an actual spacer etching process that creates footing at the bottom of the spacer in the art;
Figure 2 is a process flow for a cycle of the disclosed cyclic ALE process;
Figure 3 is a graph of etched thickness versus ALE cycle using CH ₃ F;
Figure 4 is a graph of etched thickness versus ALE cycle using C ₂ H ₅ F;
Figure 5 is a graph of etched thickness versus ALE cycle using C ₃ H ₇ F;
Figure 6a is an EDS plot of a SiN spacer after ALE applying 100% etched sidewalls and 100% overetched sidewalls using C ₂ H ₅ F, respectively (horizontal scan of the sidewalls);
Figure 6b shows an EDS line scan using atoms of a SiN spacer after ALE applying 100% etched sidewalls and 100% overetched sidewalls using C ₂ H ₅ F, respectively (vertical scan of the bottom of the spacer); and
Figure 7 is a sequential etching of a SiN spacer using C ₂ H ₅ F: EDS plotting (left diagram) and EDS line scan (right diagram).

A method for improving profile control to form silicon nitride (SiN) spacers on Si-containing substrates with high selectivity in semiconductor applications is disclosed. The disclosed method applies a cyclic atomic layer etch (ALE) process using a plasma of HFC and a plasma of noble gas to etch the SiN layer on a structure covered by a SiN layer and/or on an underlying Si-containing layer (e.g., a substrate). Selectively etched. As used herein, a structure may be a gate or gate stack.

The disclosed method significantly improves profile control for forming SiN spacers. Important features of the SiN spacers formed include the high selectivity of SiN for underlying Si-containing layers, such as poly-Si (or Si) and SiO ₂ . Additionally, important features of the formed SiN spacers include zero chemical damage to the underlying Si-containing layer, even when using an over-etch recipe, little excess material close to the SiN layer and substrate, and no footing at the lower edge of the spacer. virtually no F residue remaining on the sidewalls of the spacer, etc.

In semiconductor applications, spacers are used on gates or gate stacks by CVD or ALD to isolate the gate contact and source and drain contacts in metal-oxide-semiconductor field-effect transistors (MOSFETs). A layer of material deposited on a structure such as The material may be SiN or the like. The spacer passivates the sidewalls of the gate stack. The disclosed method can be applied to any type of spacer in semiconductor applications, including gate spacers, self-aligned double patterned (SADP) spacers, patterned spacers with self-aligned quadruple patterned (SAQP) spacers, etc. As used herein, the gate stack may be a digital switch, random-access memory (RAM), amplifier, field-effect transistor-based biosensor (BioFET), DNA field-effect transistor (DNAFET), ferroelectric, magnetic, electrolytic, etc. More specifically, the gate stack is used in flash memory, such as 3D NAND and NOR, silicon-oxide-nitride-oxide-silicon (SONOS), high-gauge devices including strain interfaces including global and local strains, ferroelectric gate stacks, electrolyte interfaces, etc. -k can be a gate stack.

1A - 1C show exemplary cross-sectional side views of exemplary SiN spacer formations on a base substrate. 1A shows, but is not limited to, a trench pattern formed to create SiN spacers. SiN coated structures 10 and 12 are formed on top of substrate 102 . Although multiple SiN coated structures can be formed on top of substrate 102 , only two structures 10 and 20 are shown. Substrate 102 may be a FinFET (fin field-effect transistor) substrate composed of Si-containing materials such as Si, poly-Si, SiO ₂ , etc. The symbol 104 represents a layer of SiN covering the structure 106 on the substrate 102 . Structure 106 , also called a pillar in the art, may be a gate stack covered by a SiN layer 104 . In ideal circumstances, the etch front, the SiN layer covering the top of the structure 106 or the top of the filler and the top of the substrate 102 or the bottom of the trench horizontally should be removed, leaving a structure 106 with little footing at the bottom edges. ), vertically upright and uniform SiN sidewalls should be obtained. Herein, “a ₁ ” and “a ₂ ” refer to the thickness of the SiN layer on the sidewall 104 at different heights of the structure or gate stack. The height of “ a ₁ ” may be close to the top of the pillar, for example about one third of the overall height of the structure 106 below the top of the pillar; “a ₂ ” may be at a height proximal to the substrate 102 at a height of about one third of the total height of the structure 106 above the substrate 102 . Because the structure 106 beneath the SiN layer 104 may be curved at the bottom adjacent the substrate 102 (not shown), the value of "a ₂ " is equivalent to "a ₁ " with the SiN spacer standing vertically. It may be smaller than the value of . “b” and “c” represent the thickness of the SiN layer on top of structure 106 and on top of substrate 102 , respectively. “b” and “c” herein are the thickness of the etch front. Additionally, “c” may also represent the removed thickness of substrate 102 after removing the SiN layer. In this case, “c” may be a negative value. As shown in Figure 1B , a vertically erect and uniform SiN sidewall 204 coating is formed on the structure 206 , and an etch front horizontally covers the top of the structure 206 and the top of the substrate 202 . An idealized SiN spacer etching result is presented, with the upper SiN layer removed. However, the actual spacer etch process often leaves excess material near the SiN layer and substrate, resulting in footing 308 at the bottom of the spacer, as shown in Figure 1C . Herein, the horizontal length of footing 308 adjacent to substrate 302 , “d”, is defined to indicate the size of the footing.

A cyclic ALE process disclosed to control the etch profile of SiN spacers formed on Si-containing substrates overcomes the defects of footing when manufacturing SiN spacers. The cyclic ALE process disclosed to control the etch profile of SiN spacers formed on Si-containing substrates also produces vertically upright spacers without tapering when manufacturing SiN spacers. The disclosed cyclic ALE process includes a surface modification step or deposition step and a surface removal step or etching step within one ALE cycle. During the surface modification step, a polymer thin film is deposited on the surface of the SiN layer (Figure 1a , see SiN layer ( 104 )) in the reaction chamber. It is deposited on the surface of the modifying SiN layer. The polymer thin film is formed by a plasma of HFC gas or a gas mixture of HFC gas and an inert gas such as N ₂ , Ar, Kr, Xe, preferably Ar. HFC gas reacts with the material SiN on the surface of the SiN layer to form a polymer thin film, also called a modified surface layer, which is a C-rich polymer (C:F > 1) on the surface of the SiN layer, where chemical bonds It is formed in the interlayer between the polymer thin film and the surface of the SiN layer. In the surface removal step, the modified surface layer is etched or removed by a pure inert gas (e.g. Ar) plasma through energetic ion bombardment that sputters the modified surface layer, which is highly volatile and is pumped away from the chamber. It can be. After the surface removal step, the surface modification step is repeated to form a cyclic ALE process. By cyclic ALE, an ALE overetch recipe can be applied to further remove the SiN layer on the etch front due to the infinite selectivity of SiN over the structure or gate stack. The ALE overetch recipe can range from approximately 10% ALE overetch to approximately 200% ALE overetch, preferably approximately 50% ALE overetch to approximately 200% ALE overetch. This process can be cycled and allows staged removal of material, increasing pattern accuracy and minimizing footing of SiN spacers. Between the surface modification step and the surface removal step or after the deposition step and the etching step, an N ₂ purge step is applied. The N ₂ purge step includes a vacuum pump step to pump HFC gas out of the reaction chamber before the N ₂ purge step and a vacuum pump step to pump N ₂ out of the reaction chamber after the N ₂ purge step.

An ideal cyclic ALE process is based on self-limiting reactions, meaning that the reactants react only on the available surface sites on the substrate while keeping the underlying layers intact. ALE process conditions can be optimized by tracking the self-limiting properties of reactant flow rates and exposure times. A constant N ₂ purge was used at the end of each step to remove excess etchant from the system to prevent any synergistic reactions.

Referring to Figure 2 , in one cycle of the disclosed ALE process, a plasma etch gas formed from a gas mixture of HFC gas and Ar deposits a polymer thin film on the surface of the SiN layer in the reaction chamber in step 1. The polymer thin film is then etched or removed in step 2 by a pure inert gas (e.g. Ar) plasma. After each step, the reaction chamber undergoes a pump/N ₂ purge/pump process, which pumps the reaction chamber to vacuum before proceeding to the next step, charges N ₂ into the reaction chamber to purge it, and purges the reaction chamber. Including pumping back to vacuum.

The disclosed cyclic ALE method is to selectively plasma etch _SiN using an HFC gas having _the formula _C May include steps. The HFC plasma interacts with SiN to form a C-rich polymer (C:F > 1), which is deposited on top of the SiN layer to form a polymer layer. The disclosed HFC gas can be used to selectively etch single atomic layers of the polymer layer and also the SiN layer by mixing with an inert gas in a plasma chamber. Accordingly, SiN spacers are formed with improved profile control such as high selectivity, minimized footing, limited fluorine formation, and smooth surfaces of the SiN spacers. Inert gases may be Ar, Kr and Xe. Preferably, it is Ar.

HFC gases disclosed for forming polymer layers on SiN layers include the following HFC gases: fluoroethane C ₂ H ₅ F (CAS# 353-36-6) and 1-fluoropropane C ₃ H ₇ F ( CAS# 460-13-9) may be included. These HFC gases are used to deposit a polymer layer on the SiN layer by mixing with an inert gas in a plasma chamber. An interlayer between the polymer layer and the SiN layer is formed to modify the surface of the SiN layer. Subsequently, a plasma of an inert gas such as Ar selectively removes the polymer layer and also the interlayer. This is equivalent to removing a single atomic layer of the SiN layer. In this way, SiN spacers are formed with improved profile control such as high selectivity, minimized footing, limited fluorine formation, and smooth surfaces of the SiN spacers. The inert gas may be Ar, Kr and Xe, preferably Ar.

The disclosed HFC gases are provided with a purity of greater than 99% v/v, preferably greater than 99.9% v/v, by removing major impurities N ₂ , CO _x , SO _x , H ₂ O and the like.

The disclosed HFC gases contain less than 1% by volume of trace gaseous impurities, which include less than 150 ppm by volume of impurity gases such as N ₂ and/or H ₂ O and/or CO ₂ . Preferably, the water content in the plasma etch gas is less than 20 ppmw by weight. Purified products can be produced by distillation and/or by passing the gas or liquid through a suitable adsorbent such as a 4 Å molecular sieve.

The disclosed cyclic ALE method includes providing a plasma process chamber with a substrate disposed therein. The plasma process chamber may be any enclosure or chamber within the device, in which the etching method may include, for example and without limitation, reactive ion etching (RIE), capacitively coupled plasma using a single or multiple frequency RF source. (CCP), inductively coupled plasma (ICP), electron cyclotron resonance (ECR), microwave plasma reactor, remote plasma reactor, pulsed plasma reactor, or a method capable of selectively removing a portion of a silicon-containing film or generating active species. It is performed in any chamber or enclosure used for plasma etching, such as other types of etching systems. A preferred chamber is a CCP chamber.

Those skilled in the art will recognize that different plasma reaction chamber designs provide different electronic temperature control. Suitable commercially available plasma reaction chambers include Applied Materials' magnetically enhanced reactive ion etcher sold under the trade name eMAX ^TM or Lam Research Dual CCP's reactive ion etcher dielectric etch product family sold under the trade name 2300® Flex ^TM . However, it is not limited to this. Here, RF power can be pulsed to control plasma properties, thereby further improving etch performance (selectivity and damage).

Oxygen-containing gas may be introduced into the reaction chamber to remove high polymer deposits or reduce the thickness of high polymer deposits. Oxygen-containing gases include, but are not limited to, oxidizing agents such as O ₂ , O ₃ , CO, CO ₂ , NO, NO ₂ , N ₂ O, SO ₂ , COS, H ₂ O, and combinations thereof. It is known that adding oxygen or oxygen-containing gases to the plasma chemistry increases the F/C ratio of the plasma species and reduces polymer formation ( see, for example , US Pat. No. 6,387,287 to Hung et al.). The disclosed HFC gas and oxygen-containing gas may be mixed together prior to introduction into the reaction chamber.

Alternatively, the oxygen-containing gas is continuously introduced into the chamber and the initiated HFC gas is introduced pulsed into the chamber. The oxygen-containing gas accounts for approximately 0.01% to approximately 99.99% by volume of the mixture introduced into the chamber.

In the disclosed cyclic ALE method, the plasma process time can vary from 0.01 seconds to 10000 seconds. Preferably it is 1 second to 30 seconds. The N ₂ purge time can vary from 1 second to 10000 seconds. Preferably it is 10 seconds to 60 seconds.

The temperature and pressure within the reaction chamber are maintained at conditions suitable for the silicon-containing film to react with the activated etching gas. For example, the pressure within the chamber may be maintained at approximately 1 mTorr to approximately 50 Torr, preferably approximately 1 mTorr to approximately 10 Torr, more preferably approximately 300 mTorr to approximately 1 Torr, as desired by the etch parameters. You can. Likewise, the substrate temperature within the chamber is approximately -110°C to approximately 2000°C, preferably approximately -70°C to approximately 1500°C, more preferably approximately -20°C to approximately 1000°C, and even more preferably approximately 25°C to approximately 25°C. It may range from approximately 700°C, even more preferably from approximately 25°C to approximately 500°C, and even more preferably from approximately 25°C to approximately 50°C. Chamber wall temperature can range from approximately 25°C to approximately 100°C depending on process requirements.

In one implementation, the disclosed HFC gas is introduced into a reaction chamber containing a substrate having a structure formed thereon, such as a gate stack with a covered SiN layer. Gas may be introduced into the chamber at a flow rate ranging from approximately 1 sccm to approximately 10 slm. Preferably, it is 1 sccm to 100 sccm. The inert gas may be introduced into the chamber at a flow rate ranging from approximately 1 sccm to approximately 10 slm. Preferably, it is 10 sccm to 200 sccm. Those skilled in the art will recognize that flow rates may vary depending on the tool.

The disclosed cyclic etching method includes the steps of i) placing a patterned substrate on a substrate holder within a plasma process chamber or reaction chamber, wherein the patterned substrate has a SiN layer covering at least one structure on the substrate; ii) introducing an HFC gas or a mixture of an HFC gas and an inert gas into the reaction chamber to generate a plasma therein; As a step, once the plasma is generated, the plasma deposits a polymer layer on the SiN layer that modifies the surface of the SiN layer, and the HFC gas is a saturated or unsaturated, linear or cyclic HFC of the formula C _x H _y F _z (Eq. where x is 2 to 5 and y > z), and the inert gas is N ₂ , Ar, Kr, Xe, preferably Ar; iii) pumping the HFC gas or a mixture of HFC gas and inert gas out of the reaction chamber until the reaction chamber reaches a high vacuum; iv) purging the reaction chamber with N ₂ ; v) pumping the reaction chamber back to high vacuum, i.e. pumping N ₂ out of the reaction chamber until the reaction chamber reaches high vacuum; vi) introducing an inert gas into the reaction chamber to generate a plasma of the inert gas; vii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, wherein the plasma of the inert gas causes the polymer layer deposited on the SiN layer on the etch front and the modified surface of the SiN layer on the etch front through ion bombardment. removing; vii) pumping the reaction chamber to high vacuum, i.e. pumping the inert gas out of the reaction chamber until the reaction chamber reaches high vacuum; viii) purging the reaction chamber with N ₂ ; ix) pumping the reaction chamber to high vacuum; and x) repeating steps ii) to ix) until the SiN layer on the etch front is selectively removed, thereby forming substantially vertically upright SiN spacers comprising a SiN layer on the sidewalls of the gate stack. Additionally includes. An overetch recipe may be applied herein, for example between 50% overetch and 200% overetch.

In an ideal case, the ion bombardment process removes only the modified surfaces of the SiN layer and the polymer layer on the etch front, i.e., the SiN layer and the SiN layer on the top of the pillar and the bottom of the trench, leaving the SiN layer on the sidewalls unchanged. leave it as is In practice, the thickness of the SiN layer on the sidewall may vary slightly due to structures having small deviations and/or curved bottoms. The disclosed cyclic etching method avoids removing at least a majority of the SiN layer on the sidewalls of the gate stack. Preferably, less than 10% of the thickness of the SiN layer on the sidewalls of the gate stack, especially the SiN layer proximal to the bottom of the structure, is removed. More preferably, less than 5% of the thickness of the SiN layer on the sidewalls of the gate stack is removed. Even more suitably, less than 1% of the thickness of the SiN layer on the sidewalls of the gate stack is removed. Even more preferably, no measurable thickness reduction of the SiN layer occurs on the sidewalls of the gate stack.

Compared to conventional SiN spacer etch processes, the disclosed cyclic ALE process using HFC gases disclosed herein maintains chemical integrity while reducing significant surface roughness or chemical contaminants (e.g., F residues) on the underlying material. From the examples below, SiN footing at the lower edge of the spacer can be reduced by more than 70% without causing harm. More specifically, the cyclic ALE process using C ₂ H ₅ F produced no fluoride residues on the bottom and sidewalls of the trench. As used herein, no fluoride residue means that approximately less than 0.05% fluoride residue remains on the bottom and sidewalls of the trench, preferably less than 0.03%. The disclosed cyclic ALE process using the disclosed HFC gas also produces a smooth surface of the SiN spacer.

Example

The following non-limiting examples are provided to further illustrate embodiments of the invention. However, the examples are not intended to be all-inclusive or limit the scope of the invention described herein.

The following examples were performed in a CCP plasma chamber with various conditions for each step. Plasma power, pressure, gas flow rate, reaction time, etc. were very well controlled. The pressure range was 300 mtorr to 1 Torr. The temperature range was 25C° to 50C°. The gas flow rate for CH ₃ F or C ₂ H ₅ F or C ₃ H ₇ F varied from 1 sccm to 10 sccm. The flow rate for noble gas varied from 10 sccm to 200 sccm. The noble gas used was Ar. RF plasma power ranged from 50 W to 100 W. The plasma process time or reaction time varied from 1 to 30 seconds. N ₂ purge time varied from 10 to 60 seconds. The desired purity of CH ₃ F or C ₂ H ₅ F or C ₃ H ₇ F was >99.9% by removing major impurities such as N ₂ , CO _x , C _x H _y F _z , SO _x , H ₂ O, etc.

The sample used in the examples below was a patterned spacer wafer as shown in Figure 1A , where the substrate was a Si substrate.

The ellisometer is manufactured by J.A.Woollam Co. It was M-2000. The scanning electron microscope (SEM) for imaging the patterned structures was a JOEL JSM-7500 SEM. The XPS for characterizing the surface was Kratos XPS - Supra Model. The atomic force microscope (AFM) for examining the surface was Park NX10 AFM. Transmission electron microscopy (TEM) to image the patterned structures was performed using a FEI Tecnai Osiris FEG/TEM operating at 200 kV in bright field (BF) TEM mode and high resolution (HR) TEM mode. Electron diffusion spectra (EDS) were acquired on a Bruker Quantax EDS system.

Example 1 CH ₃ F cyclic ALE process

A CH ₃ F cyclic ALE process was performed under optimized ALE conditions. Referring to Figure 2 , the etching gas was CH ₃ F. The deposition step by CH ₃ F (step 1) was performed with RF power of 75 W, pressure of 300 mTorr, Ar gas flow rate of 100 sccm, CH ₃ F flow rate of 5 sccm, and the reaction time for the deposition step was 4 seconds. The removal step (step 2) was performed with RF power of 50 W, pressure of 500 mTorr, Ar gas flow rate of 100 sccm, no CH ₃ F and reaction time of 30 seconds. The time for the Pump/N ₂ purge/pump process between Stage 1 and Stage 2 and vice versa was 90 seconds. Figure 3 shows etched thickness versus ALE cycle for CH ₃ F. As the ALE cycle increases, the SiN etched thickness becomes increasingly deeper, the selectivity of SiN toward p-Si, SiO, and SiON becomes increasingly higher, and the selectivity of SiN toward SiCN may remain unchanged. The etched thickness of SiN per cycle using CH ₃ F for various ALE cycles is listed in Table 1 .

[Table 1]

Example 2 C ₂ H ₅ F cyclic ALE process

A C ₂ H ₅ F cyclic ALE process was performed under optimized ALE conditions. Referring to Figure 2 , the etching gas was C ₂ H ₅ F. The deposition step by C ₂ H ₅ F (step 1) was performed with RF power of 75 W, pressure of 300 mTorr, Ar gas flow rate of 100 sccm, C ₂ H ₅ F flow rate of 5 sccm, and the reaction time for the deposition step was 4 seconds. It was. The ablation step (step 2) was performed with RF power of 50 W, pressure of 500 mTorr, Ar gas flow rate of 100 sccm, no C ₂ H ₅ F and reaction time of 35 seconds. The time for the Pump/N ₂ purge/pump process between Stage 1 and Stage 2 and vice versa was 90 seconds. Figure 4 shows etched thickness versus ALE cycle for C ₂ H ₅ F. As the ALE cycle increases, the SiN etched thickness increases linearly and no etching occurs for p-Si, SiO, SiON and SiCN. The results of the C ₂ H ₅ F cyclic ALE process show that the selectivity of SiN for p-Si, SiO, SiON and SiCN is very high, almost infinite selectivity.

Compared to the cyclic ALE process using CH ₃ F, C ₂ H ₅ F gas shows higher etch selectivity of SiN over p-Si, SiO, SiON and SiCN and lower etch rate, thus A small amount of etching was obtained. The etched thickness of SiN per cycle using C ₂ H ₅ F for various ALE cycles is listed in Table 1 .

Example 3 C ₃ H ₇ F cyclic ALE process

A C ₃ H ₇ F cyclic ALE process was performed under optimized ALE conditions. Referring to Figure 2 , the etching gas was C ₃ H ₇ F. The deposition step by C ₃ H ₇ F (step 1) was performed with RF power of 75 W, pressure of 300 mTorr, Ar gas flow rate of 100 sccm, C ₃ H ₇ F flow rate of 5 sccm, and the reaction time for the deposition step was 4 seconds. It was. The removal step (step 2) was performed with RF power of 50 W, pressure of 500 mTorr, Ar gas flow rate of 100 sccm, no C ₃ H ₇ F and reaction time of 40 seconds. The time for the Pump/N ₂ purge/pump process between Stage 1 and Stage 2 and vice versa was 150 seconds. Figure 5 shows etched thickness versus ALE cycle for C ₃ H ₇ F. The amount of etched thickness increased linearly with the number of ALE cycles, with an etch rate of 2.0 to 2.4 nm/cycle. Infinite etch selectivity of SiN over other materials was also obtained under optimized conditions. The etched thickness of SiN per cycle using C ₃ H ₇ F for various ALE cycles is listed in Table 1 .

Example 4 CH ₃ F and C ₂ H ₅ SEM of SiN spacer patterned wafer cyclic ALE using F

Referring to Figure 1A , the dimensions of the SiN spacer patterned wafer before etching are as follows: "a" is 34 nm; “b” is 34 nm; “c” is 34 nm. The substrate 102 is a Si substrate. The main factors involved after etching are damage to the Si substrate, sidewall deposition, footing at the edge between the spacer and the substrate, fluoride residue on the SiN layer and substrate or etch front, surface roughness of the SiN layer and substrate or etch front, etc. . Table 2 shows the thickness of the etch front after cyclic ALE of SiN spacer using CH ₃ F and C ₂ H ₅ F according to different cyclic ALE modes: 50% etch, 100% etch, 100% over-etch and 200% over-etch. List. Note that ALE 100% etch and ALE 100% overetch using C ₂ H ₅ F gave optimized results, demonstrating that very little footing formed on the underside of the spacer.

[Table 2]

Example 5C ₂ H ₅ TEM of SiN spacer patterned wafer cycling ALE using F

The ALE 100% etch and 100% overetch using C ₂ H ₅ F demonstrated in Example 4 were further tested by TEM.

Referring to Figure 1A , the dimensions of the SiN spacer patterned wafer before etching are as follows: "a" is 34 nm; “b” is 34 nm; “c” is 34 nm. The substrate 102 is a Si substrate. TEM-ready samples were prepared using an in-situ focused ion beam (FIB) lift-out technique on a FEI Strata 400 Dual Beam FIB/SEM. Samples were capped with protective carbon and e-Pt/I-Pt before milling. TEM lamella thickness was approximately 100 nm. Samples were imaged using a FEI Tecnai Osiris FEG/TEM operating at 200 kV in bright field (BF) TEM mode and high resolution (HR) TEM mode. TEM results of cyclic ALE using C ₂ H ₅ F are listed in Table 3.

With the ALE -100% etching, no over-etching occurred, the SiN on the top of the pillar was not completely etched, and the left (L) and right (R) thicknesses of the SiN layer on the sidewall ("a ₂ ", The total height of the close gate stack (about one-third) was 32.6 and 32.3 nm, respectively, and the left and right footings (“d”) were 6.6 nm and 8.2 nm. The thickness of the SiN layer on the sidewall (“a ₂ “) was reduced by about 5%. On the other hand, with ALE-100% overetching, the SiN on the top of the pillar was completely etched, the left and right thicknesses (“a ₂ ”) of the SiN layer on the sidewall were 30.4 and 31.1 nm, respectively, and the left and right footings were were 6.0 nm and 3.9 nm. The thickness of the SiN layer on the sidewall (“a ₂ “) decreased by about 9.5%. Accordingly, less than 10% of the thickness of the SiN layer on the sidewalls of the gate stack is removed. The decrease in the thickness (a ₂ ) of the SiN layer on the sidewall may be due to a curvature of the structure or gate stack adjacent to the substrate that curves the inner surface of the SiN layer adjacent to the structure or gate stack. The decrease in the thickness (a ₂ ) of the SiN layer on the sidewall can also be due to small deviations.

Si depression refers to the amount of thickness of the Si substrate that has been etched. The Si depression was measured 10 nm away from the lower edge of the SiN sidewall toward the left and right. With ALE-100% etching, no over-etching occurred and the left and right Si depressions were 1.446 nm and 1.285 nm, respectively. On the other hand, with ALE-100% overetching, the left and right Si depressions were 4.096 nm and 4.194 nm, respectively.

The surface roughness of the SiN spacer after ALE applying 100% etching and 100% overetching using C ₂ H ₅ F includes the surface roughness of the top of the filler (T) and the surface roughness of the bottom of the trench (B). Table 3 also includes surface roughness results. With ALE 100% etching, 2 to 3 atomic layer levels (al) of the SiN layer still remain on top of the filler (positive value), meaning that the SiN layer on top of the filler has not been completely removed. do. In this case, the interface between the SiN layer and the top of the filler is smooth and planar, which is equivalent to the surface roughness without etching. The bottom of the trench etched by the ALE-100% etch also shows that 2 to 3 atomic layers of SiN layer remain on the bottom of the trench. With ALE-100% overetching, both the top of the pillar and the bottom of the trench were etched to a level of 2 to 3 atomic layers (negative values).

[Table 3]

Example 6 C ₂ H ₅ EDS of SiN spacer patterned wafer cyclic ALE using F

Figure 6a shows the EDS plot of a SiN spacer after ALE applying 100% etched sidewalls and 100% overetched sidewalls using C ₂ H ₅ F, respectively (horizontal scan of the sidewalls). With 100% etching, no over-etching occurred and there was no F residue on the sidewalls. With 100% overetching, there is no F residue on either sidewall.

Figure 6b shows an EDS line scan using atoms of a SiN spacer after cyclic ALE applying 100% etched sidewalls and 100% overetched sidewalls using C ₂ H ₅ F, respectively (vertical scan of the bottom of the spacer). With 100% etching, there is no F residue on the sidewall. With 100% overetching, there is no F residue on either sidewall.

Example 7 C ₂ H ₅ Cyclic ALE vs. Continuous Etch using F

Table 4 is a comparison of continuous etch and cyclic ALE. The result was that by the continuous etching process, the Si depression was 2.9 nm; A polymer layer was formed on the sidewall; It shows that the footing was 16.2 nm at the left edge and 15.3 nm at the right edge. On the other hand, by the cyclic ALE process, the result was a Si depression of 4.1 to 4.2 nm; A minimal polymer layer was formed on the sidewall; It shows that footing was 6.0 nm on the left and 3.9 nm was formed on the right. Compared to continuous etching, the cyclic ALE process reduces footing by approximately 75%. Therefore, compared to that with a continuous etching process using C ₂ H ₅ F to etch the SiN spacer, with the cyclic ALE process, both Si depressions and surface roughness are improved, and little footing is formed. Herein, little footing can be defined by “d” ≤ approximately 6 nm.

[Table 4]

Figure 7 shows sequential etching of a SiN spacer using C ₂ H ₅ F: EDS plotting (left diagram) and EDS line scan (right diagram). Apparently, with subsequent etching, F residues were present on the sidewalls (about 22-36 nm) and the bottom of the trench (about 36-58 nm). On the other hand, the F residue did not appear in Figures 6a and 6b .

Table 5 lists the measured percentage of fluoride residue remaining on the bottom and sidewalls of the trench after cyclic ALE and continuous etching, respectively. The cyclic ALE process mode left little fluoride on the bottom and sidewalls of the trench, while the continuous etch method created fluoride residue on the bottom and sidewalls of the trench.

Accordingly, the cyclic ALE process mode using C ₂ H ₅ F produced no fluoride residues and reduced etchant residues on the surfaces of the etch front and sidewalls. The cyclic ALE process mode using C ₂ H ₅ F produces minimal SiN footing and little damage to the top of the SiN spacer.

[Table 5]

Example 8 C for Cyclic ALE SiN Planar Wafers ₂ H ₅ Surface roughness using F

Surface roughness—RMS of thin films of SiN on planar wafers was measured by AFM before and after cyclic ALE using C ₂ H ₅ F. Before cyclic ALE using C ₂ H ₅ F, RMS (rms) = 2.9 nm. After cyclic ALE using C ₂ H ₅ F, RMS = 1.1 nm. Therefore, a smaller RMS was obtained after cyclic ALE using C ₂ H ₅ F, showing the improved surface smoothing effect of ALE using C ₂ H ₅ F.

In summary, the disclosed cyclic ALE of SiN spacers using disclosed HFCs such as C ₂ H ₅ F, C ₃ H ₇ F can minimize SiN footing (e.g., reduce footing by approximately 75% compared to continuous etching). reduction), no F residues are generated on the top of the filler, bottom and sidewalls of the trench, no chemical contamination, and no surface roughness degradation after the cyclic ALE process. Disclosed cyclic ALE of SiN spacers using disclosed HFCs such as C ₂ H ₅ F, C ₃ H ₇ F improves etch profile control for etching SiN spacers formed on Si-containing substrates in semiconductor applications with high selectivity .

Numerous additional modifications of the details, materials, steps, and arrangements of parts described and illustrated herein for the purpose of explaining the essence of the invention may be made by those skilled in the art without departing from the spirit and scope of the invention as set forth in the appended claims. You will understand that it can be done. Accordingly, the present invention is not limited to the specific embodiments of the above-described embodiments and/or the accompanying drawings.

Although embodiments of the invention have been shown and described, modifications may be made by those skilled in the art without departing from the spirit or teachings of the invention. The embodiments described herein are illustrative only and not limiting. Many variations and modifications of the compositions and methods are possible and are within the scope of the present invention. Accordingly, the scope of protection is not limited to the embodiments described herein, but is limited only by the following claims, which scope includes all equivalents to the subject matter of the claims.

Claims (15)

As a cyclic etching method,
i) exposing the SiN layer covering the structure on the substrate in a reaction chamber to a plasma of hydrofluorocarbons (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, wherein the HFC has the formula CxHyFz, where x is 2 to 5 and y > z, and the HFC is a saturated or unsaturated, linear or cyclic HFC;
ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, such that the modified surface of the SiN layer on the polymer layer deposited on the SiN layer and the etch front removing; and
iii) Repeat steps i) and ii) until the SiN layer deposited on the etch front is removed, thereby forming a vertically upright SiN spacer with the SiN layer deposited on the sidewalls of the structure. Including the steps of:
The method of claim 1 , wherein the plasma of HFC in step i), the plasma of inert gas in step ii), or both are pulsed plasmas. According to paragraph 1,
After step i),
pumping the reaction chamber to a vacuum;
purging the reaction chamber with N ₂ ;
pumping the reaction chamber to a vacuum; and
introducing the inert gas into the reaction chamber to generate the pulsed plasma of the inert gas; and
After step ii),
pumping the reaction chamber to a vacuum;
purging the reaction chamber with N ₂ ;
pumping the reaction chamber to a vacuum; and
Introducing the HFC into the reaction chamber to generate the pulsed plasma of the HFC. According to paragraph 1,
A method of cyclic etching, wherein single or multiple RF sources are applied to generate the pulsed plasma of the HFC in step i) and to generate the pulsed plasma of the inert gas in step ii), respectively. According to any one of claims 1 to 3,
The hydrofluorocarbon (HFC) is mixed with an oxygen-containing gas selected from O ₂ , O ₃ , CO, CO ₂ , NO, NO ₂ , N ₂ O, SO ₂ , COS, H ₂ O, or combinations thereof. , cyclic etching method. According to any one of claims 1 to 3,
The cyclic etching method wherein the inert gas is N ₂ , Ar, Kr or Xe. According to any one of claims 1 to 3,
The cyclic etching method wherein the HFC is C ₂ H ₅ F or C ₃ H ₇ F. According to any one of claims 1 to 3,
wherein the HFC selectively etches the SiN layer on the structure. According to any one of claims 1 to 3,
A cyclic etching method, wherein no footing is formed at each corner between the vertically upright SiN spacer and the substrate. A cyclic etching method for forming vertically upright SiN spacers, comprising:
i) polymer deposited on the SiN layer covering the structure on the substrate by exposing the SiN layer to a plasma of a mixture of hydrofluorocarbons (HFC) and oxygen-containing gases in a reaction chamber to modify the surface of the SiN layer forming a layer, wherein the HFC has the formula CxHyFz, where A step selected from O ₂ , O ₃ , CO, CO ₂ , NO, NO ₂ , N ₂ O, SO ₂ , COS, H ₂ O or combinations thereof;
ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, such that the modified surface of the SiN layer on the polymer layer deposited on the SiN layer and the etch front removing; and
iii) Repeat steps i) and ii) until the SiN layer deposited on the etch front is removed, thereby forming a vertically upright SiN spacer with the SiN layer deposited on the sidewalls of the structure. Including the steps of:
A cyclic etching method, wherein the plasma of the mixture in step i), the plasma of the inert gas in step ii), or both are pulsed plasmas. According to clause 9,
A method of cyclic etching, wherein single or multiple RF sources are applied to generate the pulsed plasma of the mixture in step i) and to generate the pulsed plasma of the inert gas in step ii), respectively. According to claim 9 or 10,
wherein the HFC is C ₂ H ₅ F or C ₃ H ₇ F and selectively etches the SiN layer on the structure. According to claim 9 or 10,
A cyclic etching method, wherein no footing is formed at each corner between the vertically upright SiN spacer and the substrate. A cyclic etching method for forming vertically upright SiN gate spacers, comprising:
i) exposing the SiN layer covering the gate stack on the substrate in a reaction chamber to a plasma of a hydrofluorocarbon (HFC) selected from the group comprising C ₂ H ₅ F or C ₃ H ₇ F to form a surface of the SiN layer forming a polymer layer deposited on the SiN layer that modifies;
ii) exposing the polymer layer deposited on the SiN layer to an Ar plasma, wherein the Ar plasma removes the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on the etch front; and
iii) Repeat steps i) and ii) until the SiN layer deposited on the etch front is removed, thereby forming a vertically upright SiN gate spacer with the SiN layer deposited on the sidewalls of the gate stack. Including the step of forming,
Wherein the plasma of HFC in step i), the Ar plasma in step ii), or both are pulsed plasmas. According to clause 13,
A method of cyclic etching, wherein single or multiple RF sources are applied to generate the pulsed plasma of the HFC in step i) and to generate the Ar pulsed plasma in step ii), respectively. According to claim 13 or 14,
A cyclic etching method, wherein no footing is formed at each corner between the vertically upright SiN gate spacer and the substrate.