KR20240068509A - Method of operating a storage device and method of operating a storage system including storage device - Google Patents

Abstract

A method of operating a storage device and a method of operating a storage system including the storage device are disclosed. A method of operating a storage device including a non-volatile memory device and a storage controller that communicates with a host and controls the non-volatile memory device according to an embodiment of the present disclosure includes the storage controller using a public key received from a first host. storing, wherein the storage controller transmits a random number to the second host in response to a host authentication initiation request from a second host that has obtained the public key and a private key corresponding to the public key, wherein the storage controller Receiving a signature generated based on the private key and the random number from the second host, verifying the signature based on the public key by the storage controller, and if the signature verification is successful, the storage controller It may include changing first device parameters according to a request from the second host.

Description

{Method of operating a storage device and method of operating a storage system including storage device}

The technical idea of the present disclosure relates to a method of operating a storage device, and more specifically, to a method of operating a storage device that changes device parameters according to a request from an authenticated host, and a storage system including the storage device and the host. It is about how to operate.

Storage devices such as Universal Flash Storage (UFS) and embedded Multi Media Card (eMMC) are widely used. The storage device contains parameters that can be written once for security reasons, and the parameters cannot be changed once written, which is a factor in lowering the recycling rate of the storage device during the manufacturing stage of the storage system including the storage device. do. There is a need for a method in which the host can change the parameters while preventing the end user from changing the parameters.

The technical idea of the present disclosure is to provide a method of operating a storage device in which a parameter having a security writeable attribute can be changed through authentication of a host, and a method of operating a storage system including the storage device.

According to an exemplary embodiment of the present disclosure, a method of operating a storage device including a non-volatile memory device and a storage controller that communicates with a host and controls the non-volatile memory device includes: storing a public key, the storage controller transmitting a random number to the second host in response to a host authentication initiation request from a second host that has obtained the public key and a private key corresponding to the public key, receiving, by the storage controller, a signature generated based on the private key and the random number from the second host; verifying, by the storage controller, the signature based on the public key; and if the signature verification is successful, The storage controller may include changing first device parameters according to a request from the second host.

According to the technical idea of the present disclosure, the storage device performs host authentication based on a public key provided from the host and changes the state of the storage device according to the request of the authenticated host, without changing the security level for the end user. Parameters that can be written once can be changed according to the host's request. Accordingly, the storage device can be reused.

1 is a block diagram showing a storage system according to an exemplary embodiment of the present disclosure.
Figure 2 is a flowchart showing a method of operating a storage device according to an exemplary embodiment of the present disclosure.
Figure 3 is a flowchart showing operations between a host and a storage device according to an exemplary embodiment of the present disclosure.
4A and 4B illustratively show transitions of states of a storage device according to an example embodiment of the present disclosure.
Figure 5 schematically illustrates storage areas of a non-volatile memory device according to an example embodiment of the present disclosure.
Figure 6 is a flowchart illustrating a command and response transmission operation between a host and a storage device according to an exemplary embodiment of the present disclosure.
FIG. 7A shows a command block for a public key setting command according to an exemplary embodiment of the present disclosure, and FIG. 7B shows a data block for data corresponding to the public key setting command.
FIG. 8A shows a command block for a public key setting command according to an exemplary embodiment of the present disclosure, and FIG. 8B shows a data block for data corresponding to the public key setting command.
FIG. 9A shows a command block for an authentication command according to an exemplary embodiment of the present disclosure, and FIG. 9B shows a data block for data corresponding to an authentication command.
Figure 10 is a flowchart showing a command and response transmission operation between a host and a storage device according to an exemplary embodiment of the present disclosure.
FIG. 11A shows a command block for a reset all key command according to an exemplary embodiment of the present disclosure, and FIG. 11B shows a data block for data corresponding to the reset all key command.
Figure 12 shows an operation of a storage device according to an exemplary embodiment of the present disclosure.
Figure 13 is a flowchart showing a method of operating a storage device according to an exemplary embodiment of the present disclosure.
14 illustrates software layers of a host and a storage device according to an example embodiment of the present disclosure.
Figure 15 is a block diagram showing a non-volatile memory device according to an exemplary embodiment of the present disclosure.
Figure 16 is a block diagram showing a UFS system according to an exemplary embodiment of the present disclosure.
FIG. 17 is a diagram for explaining a 3D VNAND structure applicable to a UFS device according to an exemplary embodiment of the present invention.
FIG. 18 is a diagram for explaining a B-VNAND structure applicable to a UFS device according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing a storage system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a storage system 10 may include a storage device 100 and a host 200 . The storage system 10 may be one of devices that store data, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

The host 200 may refer to a data processing device capable of processing data, such as a central processing unit (CPU), processor, microprocessor, or application processor (AP). The host 200 may run an operating system (OS) and/or various applications. In one embodiment, storage system 10 may be included in a mobile device, and host 200 may be implemented as an application processor (AP). In one embodiment, the host 200 may be implemented as a System-On-a-Chip (SoC) and, accordingly, may be embedded in an electronic device.

The host 200 may communicate with the storage device 100 through various interfaces. For example, the storage device 100 and the host 200 may be connected according to the interface protocol defined in the Universal Flash Storage (UFS) standard, and accordingly, the storage device 100 may be a UFS device. , the host 200 may be a UFS host. However, the present disclosure is not limited to this, and the storage device 100 and the host 200 may be connected according to various standard interfaces.

The host 200 may control data processing operations for the storage device 100, for example, data read operations or data write operations (or storage operations). The host 200 transmits a command (CMD) and data requesting a data processing operation of the storage device 100 to the storage device 100, and the storage device 100 performs a data operation according to the command (CMD). A response (RES) indicating the operation result may be transmitted to the host 200. The host 200 may transmit commands (CMD) related to general operation of the storage device 100, such as read commands and write commands, and the host 200 may also transmit commands to provide security functions of the storage device 100. A command (CMD) according to the security protocol of the interface with the storage device 100, such as a secure input command and a secure output command, may be transmitted. The storage device 100 may transmit data generated by performing an operation according to a request from the host 200 or read from the non-volatile memory 120 to the host 200.

The host 200 may include a security manager 210, and the security manager 210 may provide security functions for communication between the host 200 and the storage device 100. The security manager 210 may generate security commands and data, provide them to the storage device 100, and perform operations for security functions based on the response (RES) and/or data provided from the storage device 100. can be performed.

The security manager 210 may obtain a public key with a unique value for the storage device 100 and a private key (or referred to as a secret key) corresponding to the public key. For example, security manager 210 can generate public keys and private keys. As another example, the security manager 210 may receive a public key and a private key generated for the storage device 100 by another host. For example, the public key and private key generated by the host 200 (or another host) may be managed on a separate server, and when the host connected to the storage device 100 changes, the changed host receives the public key from the server. and receive a private key.

The security manager 210 may include a key storage (for example, 211 in FIG. 6) implemented as a non-volatile memory element, and the security manager 210 may store the public key and private key in the key storage.

The security manager 210 can transmit the public key and private key to the storage device 100 based on the security command, and then authenticate that the host 200 has legitimate control authority based on the public key and private key. there is.

The storage device 100 may be manufactured as one of various types of storage devices depending on the host interface, which is a communication method with the host 400. For example, the storage device 100 is a multimedia card in the form of SSD (Solid State Driver), MMC, eMMC, RS-MMC, and micro-MMC, and a secure card in the form of SD, mini-SD, and micro-SD. Secure digital card, USB (universal storage bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type storage device , It may be composed of any one of various types of storage devices, such as a PCI-E (PCI express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc. .

The storage device 100 may be manufactured in one of various types of packages. For example, the storage device 100 may include package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), and wafer- It can be manufactured in any one of various types of package forms, such as level fabricated package (WSP), wafer-level stack package (WSP), etc.

The storage device 100 may include a device controller 110 and a non-volatile memory device (NVM device) 120. The device controller 121 controls the non-volatile memory device 120 to write data to the non-volatile memory device 120 in response to a write request from the host 200, or in response to a read request from the host 200. In response, the non-volatile memory 130 may be controlled to read data stored in the non-volatile memory device 120.

The non-volatile memory device 120 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. In one embodiment, the plurality of memory cells may be NAND flash memory cells. However, the present invention is not limited thereto, and in another embodiment, the plurality of memory cells may be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

Memory cells are single-level cells (SLC) that store one data bit, multi-level cells (MLC) that store two data bits, and triple-level cells that store three data bits. It can be configured as a Triple Level Cell (TLC) or a Quad Level Cell (QLC) that can store four data bits.

The non-volatile memory 130 may include a plurality of memory blocks, for example, first to nth blocks (BLK1 to BLKn, where n is an integer of 2 or more). Each memory block may include a plurality of memory cells. Each memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the non-volatile memory device 120 or reading data stored in the non-volatile memory device 120. A memory block may be a unit for erasing data.

The device controller 110 of the storage device 100 according to an embodiment of the present disclosure may include a security manager 11 and a state manager 12. The security manager 11 may store the public key received from the host 200. For example, the security manager 11 stores the public key in a key storage (e.g., 1 in FIG. 6) implemented as a non-volatile memory, and when a host authentication request is received from the host 200, the host authentication request is based on the public key. Authentication can be performed.

The state manager 12 may manage the state (eg, initial state, locked state, and unlocked state) of the storage device 100. When the public key transmitted from the host 200 is stored in the storage, the storage device 100 may change the state of the storage device 100 from the initial state to the locked state. If host authentication is successful, the state manager 120 may change the state of the storage device 100 from the locked state to the unlocked state or from the locked state to the initial state.

Parameters for operating settings of the storage device 100 may be stored in the storage device 100. For example, parameters may be stored in a specific area of the non-volatile memory device 120 or in a non-volatile memory provided inside the storage controller 110. Parameters can have one of various properties, such as read-only properties, one-time writable properties, read and write properties, etc. The storage device 100 may change a one-time writable parameter (hereinafter referred to as a first parameter) in an unlocked state or an initial state. For example, the storage device 100 may initialize the first parameter. Here, initialization may mean setting the value of the already written first parameter to invalid. In the embodiment, the first parameter is a value set by the host 200, and is an RPMB key used for authentication for access to the replay protected memory block (RPMB) and a RPMB key used for partitioning of the non-volatile memory device 120. It may include setting values, etc.

In the storage system 10 according to an embodiment of the present disclosure, the host 200 generates a public key with a unique value for the storage device 100 and a private key corresponding to the public key, and the storage device 100 Host authentication may be performed based on a public key provided from the host 200, and the state of the storage device 100 may be changed and the first parameter may be changed according to a request from the authenticated host 200. The storage device 200 may change the first parameter according to a request from the host 200 while preventing the end user from changing the first parameter.

Figure 2 is a flowchart showing a method of operating a storage device according to an embodiment of the present disclosure.

The method of FIG. 2 can be performed in a storage device (100 in FIG. 1), and the operation of the storage device 100 described with reference to FIG. 1 can also be applied to this embodiment.

Referring to FIG. 2, the storage device 100 may receive a public key from a host (200 in FIG. 1) (S101). The public key may be generated by the host 200 or the host 200 may obtain it from another host.

The storage device 100 may store the received public key (S102). The storage device 100 may store the public key in a non-volatile memory, for example, in a specific area of the non-volatile memory device (120 in FIG. 1) or in a non-volatile memory provided in the device controller 110. You can. In response to storing the public key, the state of the storage device 100 may change from the initial state to the locked state.

The storage device 200 may transmit a random number to the host 200 in response to an authentication initiation request from the host 200 (S103). The storage device 200 may generate a random number in response to an authentication initiation request from the host 200 and transmit the random number to the host 200 . As an example, the random number may be 32 bytes of data.

The storage device 200 may receive a signature (or digital signature) generated based on a private key and a random number from the host 200 (S104). In an embodiment, the host 200 may process random numbers received from the storage device 200 based on a hash algorithm (or hash function) to generate a hash value, and encrypt the hash value using a private key. . The storage device 200 may receive a hash algorithm used to generate a hash value along with a random number.

The storage device 200 may verify the signature based on the public key (S105). The storage device 200 may verify the signature based on the stored public key in step S102. In an embodiment, the storage device 200 generates a first hash value by decrypting the signature based on the public key, and generates a second hash value by processing a random number based on a hash algorithm received with the signature. can be created. The storage device 200 may verify the signature by comparing the first hash value and the second hash value. If the first hash value and the second hash value are the same, the storage device 200 may determine that signature verification and host authentication are successful.

The storage device 200 may change the first device parameter according to a request from the host 200 when signature verification is successful, that is, when host authentication is successful (S106). As described with reference to FIG. 1, the first device parameter may be a one-time writable setting value. In an embodiment, when the host is authenticated, the state of the storage device 200 may change from the locked state to the unlocked state. The storage device 200 may change the first device parameter in an unlocked state. In an embodiment, when the host is authenticated, the storage device 200 may change from the locked state to the initial state in response to a security command from the host 200. For example, the security command may be a key reset command, and the keys stored in the storage device 200, including the public key, may be reset in the initial state.

Figure 3 is a flowchart showing operations between a host and a storage device according to an embodiment of the present disclosure. The flowchart of FIG. 3 shows the operation between the host 200 and the storage device 200 of FIG. 1, and the description of the operation of the host 200 and the storage device 200 with reference to FIGS. 1 and 2 is provided in this embodiment. It can be applied to .

Referring to FIG. 3, the host 200 may obtain a public key and a private key (S210). In an embodiment, the host 200 may generate a public key with a unique value for the storage device 100 and a private key corresponding to the public key. In an embodiment, the public key and private key are generated by another host to which storage device 100 was connected, and host 200 may receive the public key and private key generated by the other host. For example, the public key and private key may be managed in a separate server to which the host 200 can be connected wired or wirelessly, and the host 200 may receive the public key and private key from the server.

The host 200 may transmit the public key to the storage device 100 (S220). In an embodiment, the host 200 may transmit the public key to the storage device 100 along with a security command requesting public key setting.

The storage device 100 may store the public key received from the host 200 (S110). As described above with reference to FIG. 2 , the state of the storage device 100 may change from the initial state to the locked state as the storage device 100 stores the public key.

Afterwards, the host 200 may transmit a request to start host authentication to the storage device 100 (S230). In an embodiment, the host 200 may transmit a challenge command to the storage device 100. In response to a request to start host authentication from the host 200, the storage device 100 may generate a random number (S120) and transmit the random number to the host 200 (S130).

The host 200 may generate a signature based on the received random number and private key (S240). The host 200 may transmit the signature to the storage device 100. In an embodiment, the host 200 may transmit a signature to the storage device 100 along with a command indicating an authentication request. In an embodiment, the host 200 may transmit a signature to the storage device 100 along with a security command indicating a specific security operation, such as a key clear command.

The storage device 100 may verify the signature based on the public key (S140). The storage device 100 may transmit a verification result, for example, verification success or failure, to the host 200 (S150). If the signature verification is successful, that is, if host authentication is performed indicating that the host 200 is a host with authority to control the storage device 100, the storage device 100 may change the first device parameter (S160). . Here, controlling the storage device 100 may include controlling the read and write functions of the storage device 100 as well as controlling the security functions of the storage device 100.

In an embodiment, the storage device 100 changes from the locked state to the unlocked state, and in the unlocked state, the storage device 100 may change the first device parameter. As described above, the first device parameter may have a one-time writable attribute. For example, the first device parameter may be an RPMB key.

In an embodiment, the storage device 100 may change from the locked state to the initial state. The first device parameter may include a plurality of keys stored in the storage device 100, including a public key, and the plurality of keys may be reset as the storage device 100 is changed to its initial state. For example, key values of multiple keys may be invalidated.

4A and 4B exemplarily show transitions between states of a storage device according to an embodiment of the present disclosure.

Referring to FIGS. 4A and 4B , the storage device 100 in FIG. 1 may include an initial state (ST1), a locked state (ST2), and an unlocked state (ST3). The initial state (ST1) may represent a state in which the parameters of the storage device are not set, that is, a state in which the parameters are reset. The lock state (ST2) may be a state in which security parameters related to security settings including the first parameter cannot be accessed or changed. The unlocked state (ST2) may be a state in which security parameters including the first parameter can be accessed and changed.

Referring to FIG. 4A, as the public key is set in the storage device 100, that is, as the storage device 100 stores the public key received from the host 100, the storage device 100 is in an initial state ( It can be changed from ST1) to unlocked state (ST2). Thereafter, as the host 100 connected to the storage device 100 is authenticated as a host, the storage device 100 may change from the locked state (ST2) to the unlocked state (ST3). The first parameter may be changed in the unlocked state (ST3). Here, the change of the first parameter follows the request of the host 200. When the first parameter change is completed, the storage device 100 may change back to the locked state (ST2).

Referring to FIG. 4b, after the storage device 100 changes from the initial state (ST1) to the locked state (ST2) according to the public key setting, the storage device 100 changes to the locked state (ST2) in response to the host authentication and reset command. ) can be changed to the initial state (ST1). For example, in step S250 of FIG. 3, the host 200 may transmit a signature along with a reset command to the storage device 100, and the storage device 100 may be authenticated as a host through signature verification. may change from the locked state (ST2) to the initial state (ST1) according to the reset command. For example, the reset command is a security command and may include a reset all key command that requests reset of all keys. In the initial state (ST2), a plurality of keys stored in the storage device 100 may be reset.

Figure 5 schematically explains storage areas of a non-volatile memory device according to an embodiment of the present disclosure.

Referring to FIG. 5 , the non-volatile memory device 120 may include a boot area 121, a user data area 122, and a well-known area 123. The boot area 121, the user data area 122, and the well-known area 123 may each include at least one logical unit.

The boot area 121 may include basic information needed to configure a file system. In an example embodiment, boot area 121 may contain information necessary for a file system to access the volume. For example, the boot area 121 may include a loader necessary for an operating system that operates the storage system (10 in FIG. 1), and the boot area 121 may load a kernel file of the operating system.

The user data area 122 can store user data. For example, the user data area 122 may store data requested to be stored in the storage device 100 by a host (200 in FIG. 1).

The well-known area 123 may store data (eg, commands, parameters) for performing a specific function defined for the SCSI or UFS standard. Parameters including the first device parameter of the storage device 100 may be stored in the well-known area 123. When the storage device 100 enters the unlocked or initial state as described above due to host authentication, data stored in the well-known area 123 may be changed (or reset). In an embodiment, well-known area 123 may include an RPMB logical unit, and the RPMB logical unit may include an RPMB key. The RPMB key may be changed or initialized when the storage device 100 is in an unlocked or locked state.

FIG. 6 is a flowchart illustrating a command and response transmission operation between a host and a storage device according to an embodiment of the present disclosure. Descriptions of the operations of the host 200 and the storage device 200 described with reference to FIGS. 1 to 5B may be applied to the present embodiment. For convenience of explanation, some configurations and operations of the host 200 and the storage device 100 will be shown together.

Referring to FIG. 6, the host 200 and the storage device 100 may include key storage 211 and 1, respectively, and the host 200 may store a public key and a private key in the key storage 211. there is. To set the public key and authenticate the host based on the public key, a plurality of steps, such as steps S10, S20, S30, and S40, are performed in response to each command transmitted from the host 200 to the storage device 100. It can be.

In step S10, the host 200 may transmit a first security command (SCMD1) to the storage device 100 (S11). The first security command (SCMD1) indicates data output and is disclosed to the storage device 100. It may be a Set Public Key Command requesting to set a key. Here, the first security command (SCMD1) and the security commands described below, such as the second security command (SCMD2) and the third security command (SMCD3), are security commands according to the interface method between the storage device 100 and the host 200. It may be specified according to the protocol.

The host 200 may transmit the first data DT1 to the storage device 100 as output data corresponding to the first security command SCMD1. The first data DT1 may include a public key.

The storage device 100 may store the public key in the key storage 1 in response to the first security command (SCMD1) received from the host 200. Accordingly, the public key may be set.

The storage device 100 may transmit a command response indicating that the public key has been set to the host 200 in response to the first security command (SCMD1) (S13).

In step S20, the storage device 100 may transmit a second security command (SCMD2) requesting initiation of host authentication to the storage device 100 (S14). The second security command (SCMD2) is a data input command, that is, it may be a command to request data from the storage device 100. In an embodiment, the second security command (SCMD2) may include a challenge command. The storage device 100 may generate a random number in response to the second security command SCMD2 and transmit second data DT2 including the random number to the host 200. Additionally, the storage device 100 may transmit a command response indicating that the response to the second security command (SCMD2) has been completed to the host 200 (S16).

The host 200 may generate a signature (digital signature) based on the random number and public key received from the storage device 100. Thereafter, in step S30, the host 200 may transmit a third security command (SCMD3) requesting host authentication to the storage device 100 (S17). The third security command (SCMD3) is a data output command. In the embodiment, the third security command (SCMD3) requests authentication based on data transmitted to the storage device 100 together with the third security command (SCMD3). It may be an authentication command. The host 200 may transmit third data (DT3) corresponding to the third security command (SCMD3) to the storage device (S18). The third data DT3 may include a signature generated by the host 200 and may also include a hash algorithm (or hash function) used to generate the signature. The storage device 100 may verify the signature based on the public key stored in the key storage 1 and the received hash function. The storage device 100 may transmit a command response including the verification result to the host 200 (S19). As described above, if verification is successful, that is, if the host is authenticated, the storage device 10 may be changed to an unlocked state.

In step S40, if the command response received in step S19 includes successful verification, the host 200 may transmit a query command (QCMD) requesting a first parameter change to the storage device 100 ( S20). The storage device 100 may change the first parameter in response to a query command (QCMD) in an unlocked state. For example, the query command may include an RPMB key reset command, and the storage device 100 may reset the RPMB key in response to the RPMB key reset command. The storage device 100 may transmit a query response indicating that the first parameter has changed according to the query command (QCMD) to the host 200 (S21).

FIG. 7A shows a command block for a Set Public Key Command according to an exemplary embodiment of the present disclosure, and FIG. 7B shows a data block for data corresponding to the set public key command.

Referring to FIG. 7A, the first command block CDB1 is a command block for a challenge command and may be implemented with 12 bytes (eg, 0th to 11th bytes).

The 0th byte may have a value of A2h as an operation code. The first byte is a code representing the security protocol and may have a value of ECh. The second and third bytes are codes indicating that they are specific to the security protocol and may have values of 01h and 10h. The 7th bit of the 4th byte represents INC_512 and may have a value of 0b. The 6th to 9th bytes may indicate the transmission length, and the 11th byte is a control byte and may be set to '00h' and not used. The 0th to 6th bits, the 5th byte, and the 10th byte of the 4th byte may be reserved.

Referring to FIG. 7B, the first data block DB1 is a data block for data corresponding to a public key setting command. The first data block DB1 may include at least 4 bytes (eg, 0th byte to 3rd byte). The 0th byte includes a tag, the 1st byte and the 2nd byte represent the length of data, and at least one byte including the 3rd byte may include the value of the public key.

FIG. 8A shows a command block for a Set Public Key Command according to an exemplary embodiment of the present disclosure, and FIG. 8B shows a data block for data corresponding to the set public key command.

Referring to FIG. 8B, the second command block CDB2 is a command block for a public key setting command and may be implemented with 12 bytes (eg, 0th to 11th bytes). Each of the bytes may include 7 bits (eg, 0th to 7th bits).

The 0th byte may have a value of B5h as an operation code. The first byte is a code representing the security protocol and may have a value of ECh. The second and third bytes are codes indicating that they are specific to the security protocol and may have values of 01h and 10h. The 4th to 11th bytes may be the same as the 4th to 11th bytes of the first command block CDB1 of FIG. 8A.

Referring to FIG. 8B, the second data block DB1 is a data block for data corresponding to the challenge command. The second data block DB2 may include 32 bytes (eg, 0th byte to 31st byte). The 0th to 31st bytes may each include a random number.

FIG. 9A shows a command block for an authentication command according to an exemplary embodiment of the present disclosure, and FIG. 9B shows a data block for data corresponding to an authentication command.

Referring to FIG. 9A, the third command block CDB3 is a command block for an authentication command and may be implemented with 12 bytes (eg, 0th to 11th bytes).

The 0th byte may have a value of B5h as an operation code. The first byte is a code representing the security protocol and may have a value of ECh. The second and third bytes are codes indicating that they are specific to the security protocol and may have values of 03h and 10h. The 4th to 11th bytes may be the same as the 4th to 11th bytes of the first command block CDB1 of FIG. 8A.

Referring to FIG. 9B, the third data block DB3 is a data block for data corresponding to an authentication command. The first data block DB1 may include at least 4 bytes (eg, 0th byte to 3rd byte). The 0th byte includes a hash algorithm (or hash function), the 1st and 2nd bytes represent the length of data, and at least one byte including the 3rd byte may include the value of the signature.

FIG. 10 is a flowchart illustrating a command and response transmission operation between a host and a storage device according to an embodiment of the present disclosure. Descriptions of the operations of the host 200 and the storage device 200 described with reference to FIGS. 1 to 5B may be applied to the present embodiment. For convenience of explanation, some configurations and operations of the host 200 and the storage device 100 will be shown together.

Referring to FIG. 10, the host 200 and the storage device 100 may include key storage 211 and 1, respectively, and the host 200 may store a public key and a private key in the key storage 211. there is. To set the public key and authenticate the host based on the public key, a plurality of steps, such as steps S10, S20, and S50, may be performed in response to each command transmitted from the host 200 to the storage device 100. there is. Steps S10 and S20 are the same as steps S10 and S20 in FIG. 6. Therefore, overlapping explanations will be omitted.

In step S50, the host 200 may transmit the fourth security command (SCMD4) to the storage device 100 (S51). The fourth security command (SCMD4) is a command indicating data output and may include, for example, a reset key command (or reset all key command). The host 200 may transmit the fourth data (DT4) corresponding to the fourth security command (SCMD4) to the storage device (S52). The fourth data DT4 may include a signature generated by the host 200 and may also include a hash algorithm (or hash function) used to generate the signature. The storage device 100 may verify the signature based on the public key stored in the key storage 10 and the received hash function. Storage device 100 may reset all keys (eg, public keys and authentication keys) stored in key storage 1. In other words, all keys stored in key storage 1 may be invalidated. The storage device 100 may transmit a command response indicating that the keys have been reset to the host 200 (S53). In an embodiment, host 200 may reset the keys stored in key storage 211 , such as public keys, private keys, and Authentication keys can be reset. In an embodiment, the host 200 generates a new public key and a private key and provides the public key to the storage device 100 in step S10, thereby controlling the storage device 100 to set the public key. You can.

FIG. 11A shows a command block for a reset all key command according to an exemplary embodiment of the present disclosure, and FIG. 11B shows a data block for data corresponding to the reset all key command.

Referring to FIG. 11A, the fourth command block CDB4 may be implemented with 12 bytes (eg, 0th to 11th bytes).

The 0th byte may have a value of B5h as an operation code. The first byte is a code representing the security protocol and may have a value of ECh. The second and third bytes are codes indicating that they are specific to the security protocol and may have values 04h and 10h. The 4th to 11th bytes may be the same as the 4th to 11th bytes of the first command block CDB1 of FIG. 8A.

Referring to FIG. 11B, the fourth data block DB4 is a data block for data corresponding to the reset all key command. The fourth data block DB4 may include at least four bytes (eg, the 0th byte to the 3rd byte). The 0th byte includes a hash algorithm (or hash function), the 1st and 2nd bytes represent the length of data, and at least one byte including the 3rd byte may include the value of the signature.

Figure 12 shows the operation of a storage device according to an embodiment of the present disclosure.

Referring to FIG. 12, the storage device 100 may be connected to the first host 200a. The first host 200a may generate a public key and a private key with unique values for the storage device 100 and store them in the key storage 201a. The storage device 100 may receive a public key from the first host 200a and store the public key.

Thereafter, the storage device 100 may be connected to the second host 200b after the connection with the first host 100a is terminated. The second host 200a may obtain the public key and private key generated by the first host 201a and store them in the key storage 201b. The storage device 100 may perform a host authentication step, for example, steps S20, S30, and S30 of FIG. 6 and steps S20 and S50 of FIG. 10 together with the second host 200a.

Even if the host connected to the storage device 100 changes, the second host 200b obtains the public key and private key generated by the host, for example, the first host 200a, and the storage device 100 is connected to the second host ( At the request of 200b), host authentication is performed based on the public key and private key, and when the host is authenticated, the first parameter can be changed. Accordingly, the reuse rate of the storage device 100 may be increased.

Figure 13 is a flowchart showing a method of operating a storage device according to an embodiment of the present disclosure.

The method of FIG. 13 can be performed in a storage device (100 in FIG. 1), and the operation of the storage device 100 described above can also be applied to this embodiment.

Referring to FIG. 13, the storage device 100 may receive a public key from the first host (200a of FIG. 12) (S201). The public key may be generated by the host 200 or the host 200 may obtain it from another host.

The storage device 100 may store the received public key (S202). The storage device 100 may store the public key in a non-volatile memory, and the state of the storage device 100 may change from the initial state to the locked state in response to storage of the public key.

The storage device 200 may transmit a random number to the second host 200a in response to an authentication initiation request from the second host 200a (200a of FIG. 12) (S203). The storage device 200 may generate a random number in response to an authentication initiation request from the second host 200a and transmit the random number to the host 200. As an example, the random number may be 32 bytes of data.

The storage device 200 may receive a signature (or digital signature) generated based on a private key and a random number from the second host 200a (S204). In an embodiment, the second host 200a processes random numbers received from the storage device 200 based on a hash algorithm (or hash function) to generate a hash value, and encrypts the hash value using a private key. You can. The storage device 200 may receive a hash algorithm used to generate a hash value along with a random number.

The storage device 200 may verify the signature based on the public key (S205). The storage device 200 may change the first device parameter according to a request from the host 200 when signature verification is successful, that is, when host authentication is successful (S206). As described with reference to FIG. 1, the first device parameter may be a one-time writable setting value. In an embodiment, when the host is authenticated, the state of the storage device 200 may change from the locked state to the unlocked state. The storage device 200 may change the first device parameter in the unlocked state. In an embodiment, when the host is authenticated, the storage device 200 may change from the locked state to the initial state in response to a security command from the second host 200a. For example, the security command may be a key reset command, and the keys stored in the storage device 200, including the public key, may be reset in the initial state.

Figure 14 shows software layers of a host and a storage device according to an embodiment of the present disclosure.

Referring to FIG. 14, the host 200 includes a security manager 210, an application 220, a file system 230, a command manager 240, a data transfer manager 250, a link manager 260, and a physical layer ( PHY) (270).

The security manager 210 may provide security functions for communication between the host 200 and the storage device 100. The security manager 210 includes a key storage 211 that stores public keys, private keys, and other authentication keys, a hash processing unit 212 that generates a hash value (e.g., a first hash value) based on a hash algorithm, a private key, and It may include a signature generator 213 that generates a signature based on a random number received from the storage 100.

The application 220 running on the host 200 may access the storage device 100 through the file system 230. The command manager 240 may generate a command indicating an access request when the application 220 wants to access the storage device 100 (or another external device). The data transmission manager 250 controls data transmission with the storage device 100, the link manager 260 controls connection management with the storage device 100, and the physical layer 270 controls the physical connection with the storage device 100. Manage data communications.

The storage device 100 includes a security manager 11, device parameters 13, state manager 12, command manager 14, data transfer manager 15, link manager 16, and physical layer 17. It can be included.

The security manager 11 includes a key storage 1 that stores the public key and other authentication keys received from the host 100, a random number generator 2 that generates a random number in response to an authentication initiation request to the host 200, and a host 200. A hash processing unit 3 that processes random numbers based on a hash algorithm received from 200 to generate a hash value (e.g., a second hash value), and a signature checker 4 that verifies the signature from the host 200. It can be included.

The device parameters 13 include parameters with read-only properties, parameters with one-time writable properties, and parameters with read and write properties, etc. Likewise, it can contain parameters with various properties.

The state manager 12 may manage the state (eg, initial state, locked state, and unlocked state) of the storage device 100 and the state of the device parameters 13 . As described above, when the public key transmitted from the host 200 is stored in the storage, the state manager 12 may change the state of the storage device 100 from the initial state to the locked state. If host authentication is successful, the state manager 120 may change the state of the storage device 100 from the locked state to the unlocked state or from the locked state to the initial state. The state manager 12 can set or reset (or initialize) the device parameters 13.

The command manager 14 may interpret commands received from the host 200 and control the storage device 100 to perform operations according to the commands. The data transmission manager 15 controls data transmission with the host 200, the link manager 16 controls connection management with the host 200, and the physical layer 17 controls physical data communication with the host 200. Manage.

Figure 15 is a block diagram showing a non-volatile memory device according to an embodiment of the present disclosure.

Referring to FIG. 15, the non-volatile memory device 120 may include a control logic circuit 120, a memory cell array 122, a page buffer circuit 123, a voltage generator 124, and a row decoder 125. You can. Although not shown in FIG. 15, the non-volatile memory device 120 may further include a memory interface circuit, and may further include a command decoder, an address decoder, etc.

The control logic circuit 121 can generally control various operations within the non-volatile memory device 120. For example, the control logic circuit 121 may output various control signals in response to a command (CMD) and/or address (ADDR) received from a device controller (110 in FIG. 1). For example, the control logic circuit 121 may output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

The memory cell array 122 may include a plurality of memory blocks BLK1 to BLKn (n is a positive integer), and each of the memory blocks BLK1 to BLKn may include a plurality of memory cells. there is. The memory cell array 122 may be connected to the page buffer circuit 123 through bit lines BL, and has word lines WL, string select lines SSL, and ground select lines GSL. It can be connected to the row decoder 125 through.

In an example embodiment, the memory cell array 122 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells each connected to word lines vertically stacked on the substrate. US Patent Publication No. 7,679,133, US Patent Publication No. 8,553,466, US Patent Publication No. 8,654,587, US Patent Publication No. 8,559,235, and US Patent Application Publication No. 2011/0233648 are incorporated herein by reference. are combined. In an example embodiment, the memory cell array 122 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

The page buffer circuit 123 may include a plurality of page buffers (PB1 to PBm) (m is an integer of 3 or more), and the plurality of page buffers (PB1 to PBm) may include a plurality of bit lines (BL). It can be connected to each memory cell through. The page buffer circuit 123 may select at least one bit line among the bit lines BL in response to the column address Y-ADDR. The page buffer circuit 123 may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer circuit 123 may apply a bit line voltage corresponding to data to be programmed to the selected bit line. During a read operation, the page buffer circuit 123 may detect data stored in the memory cell by detecting the current or voltage of the selected bit line.

The voltage generator 124 may generate various types of voltages to perform program, read, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generator 124 may generate a program voltage, a read voltage, a program verification voltage, an erase voltage, etc. as a word line voltage (VWL).

The row decoder 125 may select one of a plurality of word lines (WL) and one of a plurality of string select lines (SSL) in response to the row address (X-ADDR). For example, during a program operation, the row decoder 125 may apply a program voltage and a program verification voltage to the selected word line, and during a read operation, the row decoder 125 may apply a read voltage to the selected word line.

Referring to FIGS. 1 and 14 together, the memory cell array 122 may store a plurality of parameters including a first parameter. When the storage device (100 in FIG. 1) is unlocked, the first parameter may be reset. In other words, the first parameter may be set to invalid data.

Figure 16 is a block diagram showing a UFS system according to an embodiment of the present disclosure.

The UFS system 1000 is a system that follows the UFS standard published by the Joint Electron Device Engineering Council (JEDEC) and may include a UFS host 1100, a UFS device 1200, and a UFS interface 1300. The description of the storage system 10 of FIG. 1 described above may also be applied to the UFS system 1000 of FIG. 16 to the extent that it does not conflict with the following description of FIG. 16 .

Referring to FIG. 16, the UFS host 1100 and the UFS device 1200 may be interconnected through the UFS interface 1300. When the host 200 of FIG. 1 is an application processor, the UFS host 1100 may be implemented as part of the application processor. The UFS device 1200 may correspond to the storage device 100 of FIG. 1, and the UFS device controller 1210 and non-volatile memory 1220 may correspond to the device controller 110 and non-volatile memory device 120 of FIG. 1. can correspond to each. The UFS system 1000 generates a public key with a unique value for the UFS device 1200 and a private key corresponding to the public key, and provides the UFS device 1200 from the UFS host 1100. performs host authentication based on the public key, changes the state of the UFS device 1200 at the request of the authenticated UFS host 1100, and sets a one-time writable parameter (first parameter) in the unlocked or initial state. You can change it. Accordingly, the first parameter can be changed according to a request from the UFS host 1100 while preventing the end user from changing the first parameter.

The UFS host 1100 may include a UFS host controller 1110, an application 1120, a UFS driver 1130, a host memory 1140, and a UFS interconnect (UIC) layer 1150. UFS device 1200 may include a UFS device controller 1210, non-volatile memory 1220, storage interface 1230, device memory 1240, UIC layer 1250, and regulator 1260. The non-volatile memory 1220 may be composed of a plurality of memory units 1221, and the memory units 1221 may include V-NAND flash memory with a 2D structure or 3D structure, but may include PRAM and/or RRAM. It may also include other types of non-volatile memory, such as: The UFS device controller 1210 and the non-volatile memory 1220 may be connected to each other through a storage interface 1230. The storage interface 1230 may be implemented to comply with standard protocols such as Toggle or ONFI.

The application 1120 may refer to a program that wishes to communicate with the UFS device 1200 in order to use the functions of the UFS device 1200. The application 1120 may transmit an input-output request (IOR) to the UFS driver 1130 for input/output to the UFS device 1200. An input/output request (IOR) may mean a read request, write request, and/or discard request of data, but is not necessarily limited thereto.

The UFS driver 1130 can manage the UFS host controller 1110 through UFS-HCI (host controller interface). The UFS driver 1130 may convert the input/output request generated by the application 1120 into a UFS command defined by the UFS standard and transmit the converted UFS command to the UFS host controller 1110. One input/output request can be converted into multiple UFS commands. UFS commands may basically be commands defined by the SCSI standard, but may also be commands exclusive to the UFS standard.

The UFS host controller 1110 may transmit the UFS command converted by the UFS driver 1130 to the UIC layer 1250 of the UFS device 1200 through the UIC layer 1150 and the UFS interface 1300. In this process, the UFS host register 1111 of the UFS host controller 1110 may function as a command queue (CQ).

The UIC layer 1150 on the UFS host 1100 side may include MIPI M-PHY 1151 and MIPI UniPro 1152, and the UIC layer 1250 on the UFS device 1200 side may also include MIPI M-PHY (1152). 1251) and MIPI UniPro (1252).

The UFS interface 1300 includes a line transmitting a reference clock (REF_CLK), a line transmitting a hardware reset signal (RESET_n) for the UFS device 1200, and a pair of lines transmitting a pair of differential input signals (DIN_t and DIN_c). and a pair of lines transmitting a pair of differential output signals (DOUT_t and DOUT_c).

The frequency value of the reference clock provided from the UFS host 1100 to the UFS device 1200 may be one of four values: 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not necessarily limited thereto. The UFS host 1100 may change the frequency value of the reference clock even during operation, that is, while data is being transmitted and received between the UFS host 1100 and the UFS device 1200. The UFS device 1200 may generate clocks of various frequencies from a reference clock provided from the UFS host 1100 using a phase-locked loop (PLL) or the like. Additionally, the UFS host 1100 may set the value of the data rate between the UFS host 1100 and the UFS device 1200 through the frequency value of the reference clock. That is, the value of the data rate can be determined depending on the frequency value of the reference clock.

The UFS interface 1300 may support multiple lanes, and each lane may be implemented as a differential pair. For example, a UFS interface may include one or more receive lanes and one or more transmit lanes. In Figure 16, a pair of lines transmitting a differential input signal pair (DIN_T and DIN_C) can constitute a receiving lane, and a pair of lines transmitting a differential output signal pair (DOUT_T and DOUT_C) can constitute a transmitting lane. . Although FIG. 16 shows one transmission lane and one reception lane, the number of transmission lanes and reception lanes can be changed.

The receiving lane and the transmitting lane can transmit data through serial communication, and the structure in which the receiving lane and the transmitting lane are separated allows full-duplex between the UFS host 1100 and the UFS device 1200. communication is possible. That is, the UFS device 1200 can transmit data to the UFS host 1100 through the transmission lane even while receiving data from the UFS host 1100 through the reception lane. Additionally, control data, such as commands from the UFS host 1100 to the UFS device 1200, and data that the UFS host 1100 wants to store in the non-volatile memory 1220 of the UFS device 1200 or from the non-volatile memory 1220. User data to be read may be transmitted through the same lane. Accordingly, there is no need to provide a separate lane for data transmission between the UFS host 1100 and the UFS device 1200 in addition to a pair of reception lanes and a pair of transmission lanes.

The UFS device controller 1210 of the UFS device 1200 may generally control the operation of the UFS device 1200. The UFS device controller 1210 can manage the non-volatile memory 1220 through a logical unit (LU) 1211, which is a logical data storage unit. The number of LUs (1211) may be 8, but is not limited thereto. The UFS device controller 1210 may include a flash translation layer (FTL), and uses address mapping information of the FTL to determine a logical data address transmitted from the UFS host 1100, such as LBA. (logical block address) can be converted to a physical data address, for example, a PBA (physical block address). In the UFS system 1000, a logical block for storing user data may have a size within a predetermined range. For example, the minimum size of a logical block may be set to 4Kbytes.

When a command from the UFS host 1100 is input to the UFS device 1200 through the UIC layer 1250, the UFS device controller 1210 performs an operation according to the input command and sends a completion response when the operation is completed. It can be transmitted to the UFS host (1100).

As an example, when the UFS host 1100 wants to store user data in the UFS device 1200, the UFS host 1100 may transmit a data storage command to the UFS device 1200. Upon receiving a response indicating that user data is ready-to-transfer from the UFS device 1200, the UFS host 1100 may transmit the user data to the UFS device 1200. The UFS device controller 1210 temporarily stores the transmitted user data in the device memory 1240, and stores the user data temporarily stored in the device memory 1240 based on the address mapping information of the FTL in the non-volatile memory 1220. You can save it to the selected location.

As another example, when the UFS host 1100 wants to read user data stored in the UFS device 1200, the UFS host 1100 may transmit a data read command to the UFS device 1200. The UFS device controller 1210, which has received the command, may read user data from the non-volatile memory 1220 based on the data read command and temporarily store the read user data in the device memory 1240. In this read process, the UFS device controller 1210 can detect and correct errors in the read user data using a built-in error correction code (ECC) engine (not shown). More specifically, the ECC engine can generate parity bits for write data to be written in the non-volatile memory 1220, and the parity bits generated in this way are stored in the non-volatile memory 1220 along with the write data. It can be saved. When reading data from the non-volatile memory 1220, the ECC engine corrects errors in the read data using parity bits read from the non-volatile memory 1220 along with the read data, and outputs error-corrected read data. You can.

Additionally, the UFS device controller 1210 may transmit user data temporarily stored in the device memory 1240 to the UFS host 1100. In addition, the UFS device controller 1210 may further include an advanced encryption standard (AES) engine (not shown). The AES engine may perform at least one of encryption and decryption of data input to the UFS device controller 1210 using a symmetric-key algorithm.

The UFS host 1100 stores commands to be transmitted to the UFS device 1200 in order in the UFS host register 1111, which can function as a command queue, and transmits the commands to the UFS device 1200 in that order. . At this time, the UFS host 1100 even if the previously transmitted command is still being processed by the UFS device 1200, that is, even before receiving notification that the previously transmitted command has completed processing by the UFS device 1200. The next command waiting in the command queue can be transmitted to the UFS device 1200, and accordingly, the UFS device 1200 can also receive the next command from the UFS host 1100 while processing the previously transmitted command. The maximum number (queue depth) of commands that can be stored in such a command queue may be, for example, 32. Additionally, the command queue can be implemented as a circular queue type that indicates the start and end of the command sequence stored in the queue through a head pointer and a tail pointer, respectively.

Each of the plurality of memory units 1221 may include a memory cell array (not shown) and a control circuit (not shown) that controls the operation of the memory cell array. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. A three-dimensional memory cell array may include vertical NAND strings that are vertically oriented such that at least one memory cell is located on top of other memory cells.

VCC, VCCQ, VCCQ2, etc. may be input to the UFS device 1200 as power voltages. VCC is the main power voltage for the UFS device 1200 and can have a value of 2.4 to 3.6V. VCCQ is a power supply voltage for supplying a low range voltage, and is mainly for the UFS device controller 1210. It can have a value of 1.14~1.26V. VCCQ2 is a power supply voltage to supply a voltage range lower than VCC but higher than VCCQ. It is mainly for input/output interfaces such as MIPI M-PHY (1251), and can have a value of 1.7~1.95V. The power voltages may be supplied to each component of the UFS device 1200 through the regulator 1260. The regulator 1260 may be implemented as a set of unit regulators each connected to a different one of the above-described power supply voltages.

Figure 17 is a diagram for explaining a 3D VNAND structure that can be applied to a UFS device according to an embodiment of the present invention. When the storage module of the UFS device is implemented as a 3D Vertical NAND (VNAND) type flash memory, each of the plurality of memory blocks constituting the storage module may be expressed as an equivalent circuit as shown in FIG. 17. The memory block BLKi shown in FIG. 17 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to FIG. 17 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor (SST), a plurality of memory cells (MC1, MC2, ..., MC8), and a ground selection transistor (GST). In FIG. 28, each of the plurality of memory NAND strings NS11 to NS33 is shown to include eight memory cells MC1, MC2, ..., MC8, but is not limited thereto.

The string select transistor (SST) may be connected to the corresponding string select line (SSL1, SSL2, SSL3). A plurality of memory cells (MC1, MC2, ..., MC8) may each be connected to corresponding gate lines (GTL1, GTL2, ..., GTL8). Gate lines (GTL1, GTL2, ..., GTL8) may correspond to word lines, and some of the gate lines (GTL1, GTL2, ..., GTL8) may correspond to dummy word lines. The ground select transistor (GST) may be connected to the corresponding ground select line (GSL1, GSL2, GSL3). The string select transistor (SST) may be connected to the corresponding bit lines (BL1, BL2, BL3), and the ground select transistor (GST) may be connected to the common source line (CSL).

Word lines (eg, WL1) of the same height may be connected in common, and ground selection lines (GSL1, GSL2, GSL3) and string selection lines (SSL1, SSL2, SSL3) may be separated from each other. In Figure 28, the memory block (BLK) is shown as connected to eight gate lines (GTL1, GTL2, ..., GTL8) and three bit lines (BL1, BL2, BL3), but is not necessarily limited to this. no.

FIG. 18 is a diagram for explaining a B-VNAND structure applicable to a UFS device according to an embodiment of the present disclosure. When the non-volatile memory included in the UFS device is implemented as a B-VNAND (Bonding Vertical NAND) type flash memory, the non-volatile memory may have the structure shown in FIG. 18.

Referring to FIG. 18, the memory device 4000 may have a C2C (chip to chip) structure. In the C2C structure, an upper chip including a cell region (CELL) is manufactured on a first wafer, and a lower chip including a peripheral circuit region (PERI) is fabricated on a second wafer that is different from the first wafer. This may mean connecting a chip and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the top metal layer of the upper chip and the bonding metal formed on the top metal layer of the lower chip. For example, when the bonding metal is made of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be made of aluminum or tungsten.

Each of the peripheral circuit area (PERI) and cell area (CELL) of the memory device 4000 may include an external pad bonding area (PA), a word line bonding area (WLBA), and a bit line bonding area (BLBA).

The peripheral circuit area (PERI) includes a first substrate 4110, an interlayer insulating layer 4115, a plurality of circuit elements 4120a, 4120b, and 4120c formed on the first substrate 4110, and a plurality of circuit elements 4120a. , 4120b, 4120c) and first metal layers (4130a, 4130b, 4130c) connected to each other, and second metal layers (4140a, 4140b, 4140c) formed on the first metal layers (4130a, 4130b, 4130c). You can. In one embodiment, the first metal layers 4130a, 4130b, and 4130c may be formed of tungsten with relatively high resistance, and the second metal layers 4140a, 4140b, and 4140c may be formed of copper with relatively low resistance. You can.

In this specification, only the first metal layers (4130a, 4130b, 4130c) and the second metal layers (4140a, 4140b, 4140c) are shown and described, but are not limited thereto, and the layers on the second metal layers (4140a, 4140b, 4140c) At least one more metal layer may be further formed. At least some of the one or more metal layers formed on top of the second metal layers 4140a, 4140b, and 4140c are made of aluminum, etc., which has a lower resistance than the copper forming the second metal layers 4140a, 4140b, and 4140c. It can be.

The interlayer insulating layer 4115 is formed on the first substrate to cover the plurality of circuit elements 4120a, 4120b, 4120c, the first metal layer 4130a, 4130b, 4130c, and the second metal layer 4140a, 4140b, 4140c. It is disposed on (4110) and may include an insulating material such as silicon oxide, silicon nitride, etc.

Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b of the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 4171b and 4172b of the peripheral circuit area (PERI) may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area (CELL) by a bonding method. , the lower bonding metals 4171b and 4172b and the upper bonding metals 4271b and 4272b may be formed of aluminum, copper, or tungsten.

The cell area (CELL) may provide at least one memory block. The cell area CELL may include a second substrate 4210 and a common source line 4220. On the second substrate 4210, a plurality of word lines 4231-4238; 4230 may be stacked along a direction perpendicular to the top surface of the second substrate 4210 (Z-axis direction). String select lines and a ground select line may be disposed above and below each of the word lines 4230, and a plurality of word lines 4230 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH extends in a direction perpendicular to the top surface of the second substrate 4210 and may penetrate the word lines 4230, the string select lines, and the ground select line. there is. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 4250c and the second metal layer 4260c. For example, the first metal layer 4250c may be a bit line contact, and the second metal layer 4260c may be a bit line. In one embodiment, the bit line 4260c may extend along a first direction (Y-axis direction) parallel to the top surface of the second substrate 4210.

In one embodiment shown in FIG. 18, the area where the channel structure (CH) and the bit line 4260c are placed may be defined as the bit line bonding area (BLBA). The bit line 4260c may be electrically connected to circuit elements 4120c that provide the page buffer 4293 in the bit line bonding area BLBA and the peripheral circuit area PERI. For example, the bit line 4260c is connected to the upper bonding metals 4271c and 4272c in the peripheral circuit area (PERI), and the upper bonding metals 4271c and 4272c are connected to the circuit elements 4120c of the page buffer 4293. It can be connected to the lower bonding metals 4171c and 4172c.

In the word line bonding area WLBA, the word lines 4230 may extend along a second direction (X-axis direction) parallel to the top surface of the second substrate 4210, and a plurality of cell contact plugs 4241 -4247; 4240). The word lines 4230 and the cell contact plugs 4240 may be connected to each other at pads provided by at least some of the word lines 4230 extending to different lengths along the second direction. A first metal layer 4250b and a second metal layer 4260b may be sequentially connected to the top of the cell contact plugs 4240 connected to the word lines 4230. The cell contact plugs 4240 are connected to the peripheral circuit through the upper bonding metals 4271b and 4272b of the cell area (CELL) and the lower bonding metals 4171b and 4172b of the peripheral circuit area (PERI) in the word line bonding area (WLBA). It can be connected to the area (PERI).

The cell contact plugs 4240 may be electrically connected to circuit elements 4120b that provide the row decoder 4294 in the peripheral circuit area (PERI). In one embodiment, the operating voltage of the circuit elements 4120b providing the row decoder 4294 may be different from the operating voltage of the circuit elements 4120c providing the page buffer 4293. For example, the operating voltage of the circuit elements 4120c that provide the page buffer 4293 may be greater than the operating voltage of the circuit elements 4120b that provide the row decoder 4294.

A common source line contact plug 4280 may be disposed in the external pad bonding area PA. The common source line contact plug 4280 is made of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 4220. A first metal layer 4250a and a second metal layer 4260a may be sequentially stacked on the common source line contact plug 4280. For example, the area where the common source line contact plug 4280, the first metal layer 4250a, and the second metal layer 4260a are disposed may be defined as the external pad bonding area PA.

Meanwhile, input/output pads 4105 and 4205 may be disposed in the external pad bonding area PA. Referring to FIG. 18, a lower insulating film 4101 may be formed on the lower part of the first substrate 4110 to cover the lower surface of the first substrate 4110, and a first input/output pad 4105 may be formed on the lower insulating film 4101. can be formed. The first input/output pad 4105 is connected to at least one of the plurality of circuit elements 4120a, 4120b, and 4120c disposed in the peripheral circuit area PERI through the first input/output contact plug 4103, and the lower insulating film 4101 ) can be separated from the first substrate 4110. Additionally, a side insulating film is disposed between the first input/output contact plug 4103 and the first substrate 4110 to electrically separate the first input/output contact plug 4103 from the first substrate 4110.

Referring to FIG. 18, an upper insulating film 4201 may be formed on the second substrate 4210 to cover the top surface of the second substrate 4210, and a second input/output pad 4205 may be formed on the upper insulating film 4201. can be placed. The second input/output pad 4205 may be connected to at least one of the plurality of circuit elements 4120a, 4120b, and 4120c disposed in the peripheral circuit area PERI through the second input/output contact plug 4203.

Depending on the embodiment, the second substrate 4210 and the common source line 4220 may not be disposed in the area where the second input/output contact plug 4203 is disposed. Additionally, the second input/output pad 4205 may not overlap the word lines 4230 in the third direction (Z-axis direction). Referring to FIG. 29, the second input/output contact plug 4203 is separated from the second substrate 4210 in a direction parallel to the top surface of the second substrate 4210, and the interlayer insulating layer 4215 of the cell region CELL It may be connected to the second input/output pad 4205.

Depending on embodiments, the first input/output pad 4105 and the second input/output pad 4205 may be formed selectively. For example, the memory device 4000 includes only the first input/output pad 4105 disposed on the top of the first substrate 4110, or the second input/output pad 4205 disposed on the top of the second substrate 4210. It can only include Alternatively, the memory device 4000 may include both the first input/output pad 4105 and the second input/output pad 4205.

The metal pattern of the uppermost metal layer exists as a dummy pattern in each of the external pad bonding area (PA) and bit line bonding area (BLBA) included in each of the cell area (CELL) and the peripheral circuit area (PERI). The top metal layer may be empty.

The memory device 4000 has a cell area (CELL) on the uppermost metal layer of the peripheral circuit area (PERI) corresponding to the upper metal pattern 4272a formed on the uppermost metal layer of the cell area (CELL) in the external pad bonding area (PA). ) can form a lower metal pattern (4176a) of the same shape as the upper metal pattern (4272a). The lower metal pattern 4176a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, the lower metal pattern of the peripheral circuit area (PERI) is formed on the upper metal layer of the cell area (CELL) in response to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area (PERI) in the external pad bonding area (PA). An upper metal pattern of the same shape as may be formed.

Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b of the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 4171b and 4172b of the peripheral circuit area (PERI) may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area (CELL) by a bonding method. .

Additionally, in the bit line bonding area (BLBA), the lower part of the peripheral circuit area (PERI) is formed on the uppermost metal layer of the cell area (CELL) corresponding to the lower metal pattern 4152 formed on the uppermost metal layer of the peripheral circuit area (PERI). An upper metal pattern 4292 of the same shape as the metal pattern 4152 may be formed. A contact may not be formed on the upper metal pattern 4292 formed on the uppermost metal layer of the cell region (CELL).

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached patent claims.

10: Storage systems 200, 200a, 200b: Host
100: storage device 110: device controller
120: non-volatile memory device

Claims (20)

A method of operating a storage device including a non-volatile memory and a storage controller that communicates with a host and controls the non-volatile memory, comprising:
storing, by the storage controller, a public key received from a first host;
transmitting, by the storage controller, a random number to the second host in response to a host authentication initiation request from a second host that has obtained the public key and a private key corresponding to the public key;
receiving, by the storage controller, a signature generated based on the private key and the random number from the second host;
the storage controller verifying the signature based on the public key; and
If the signature verification is successful, the storage controller changes first device parameters according to a request from the second host. The method of claim 1, wherein changing the first device parameter comprises:
A method of operating a storage device, comprising changing a one-time writable setting value among setting values for operating settings of the storage device. The method of claim 2, wherein the one-time writable setting value is stored in a first area of the non-volatile memory. The method of claim 3, wherein changing the first device parameter comprises:
A method of operating a storage device, further comprising changing the state of the first area from a locked state to an unlocked state. 2. The method of claim 1, wherein the non-volatile memory includes a replay protected memory block (RPMB),
The step of changing the first device parameter is,
A method of operating a storage device, comprising: initializing an authentication key used to authenticate access to the replay-protected memory block. The method of claim 1, wherein changing the first device parameter comprises:
A method of operating a storage device, comprising: initializing one or more keys including the public key stored in the storage device. The method of claim 6, wherein changing the first device parameter comprises:
A method of operating a storage device, comprising changing the state of the storage device from a locked state to an initial state. The method of claim 1, wherein storing the public key comprises:
Receiving a first security command requesting public key setting from the first host; and
A method of operating a storage device, comprising receiving first data including the public key from the first host. The method of claim 1, wherein transmitting the random number to the host includes
Receiving a second security command requesting initiation of host authentication from the second host;
generating the random number; and
A method of operating a storage device, comprising transmitting second data including the random number to the second host in response to the second security command. The method of claim 1, wherein receiving the signature comprises:
receiving a third security command requesting authentication based on the signature;
and
A method of operating a storage device, comprising receiving third data including the signature and hash algorithm. The method of claim 1, wherein receiving the signature comprises:
Receiving a fourth security command requesting key reset; and
A method of operating a storage device, comprising receiving third data including a signature and a hash algorithm. The method of claim 11, wherein changing the first device parameter comprises:
A method of operating a storage device, comprising: initializing a plurality of keys stored in the storage device including the public key in response to the fourth security command. The method of claim 1, wherein the verifying step includes:
generating a first hash value by decrypting the signature based on the private key;
generating a second hash value by processing the random number value based on the hash algorithm; and
A method of operating a storage device, comprising comparing the first hash value and the second hash value. According to claim 1,
A method of operating a storage device, wherein the first host and the second host are the same. According to claim 1,
A method of operating a storage device, wherein the storage device is a UFS device interconnected with the host through the UFS (Universal Flash Storage) standard. In a method of operating a storage device that communicates with a host,
A storage controller provided in the storage device receiving a public key from the host;
the storage controller storing the public key in a key storage area;
transmitting, by the storage controller, a random number to the host in response to a host authentication request from the host;
receiving, by the storage controller, a private key corresponding to the public key and a signature generated based on the random number from the host;
the storage controller verifying the signature based on the public key; and
A method of operating a storage device including the storage controller changing a first device parameter when verification of the signature is successful. The method of claim 16, wherein changing the first device parameter comprises:
changing the state of the storage device from a locked state to an unlocked state; and
A method of operating a storage device, comprising changing a one-time writable setting value among setting values for operating settings of the storage device. The method of claim 16, wherein changing the first device parameter comprises:
A method of operating a storage device, comprising initializing all keys stored in the storage device including the public key. In a method of operating a storage system including a host and a storage device,
the host obtaining a public key corresponding to the storage device and a private key corresponding to the public key;
the host transmitting the public key to the storage device;
the storage device storing the public key;
transmitting, by the storage device, a random number to the host in response to a host authentication initiation request received from the host;
the host generating a signature based on the private key and the random number;
the host transmitting the signature to the storage device;
verifying, by the storage device, a signature based on the public key; and
If the signature verification is successful, the storage controller changes a first device parameter according to a request from the host. The method of claim 19, wherein changing the first device parameter comprises:
A method of operating a storage system, comprising changing a one-time writable setting value among setting values for operating settings of the storage device.