KR20240065985A - Semiconductor package module and semiconductor device including the same - Google Patents

Abstract

A plurality of chiplet dies, which may be composed of a semiconductor die including one or more cores, an individualized upper package in which the plurality of chiplet dies are each mounted on an upper package substrate, and a plurality of the individualized upper packages. Production of a semiconductor package through a semiconductor package module including a lower module substrate on which packages are mounted, electrically connecting the plurality of individualized upper packages, and electrically connecting the plurality of individualized upper packages and external connection terminals. Costs can be reduced, the yield of semiconductor packages can be improved, and the PI/SI characteristics of semiconductor packages can be improved.

Description

Semiconductor package module and semiconductor device including the same}

The present invention relates to a semiconductor package, and more specifically, to a semiconductor package including a chiplet die.

A semiconductor package is a semiconductor chip implemented in a form suitable for use in electronic products. Typically, a semiconductor package mounts a semiconductor chip on a printed circuit board (PCB) and electrically connects them using bonding wires or bumps. As semiconductor packages become faster and have higher capacities, the power consumption of semiconductor packages is increasing. Accordingly, the importance of the PCB/package structure to respond to the size/performance of the semiconductor package and to provide stable power supply to the semiconductor package is increasing.

The problem to be solved by the technical idea of the present invention is to provide a semiconductor package that can increase the production efficiency of the semiconductor package and improve the thermal and electrical characteristics of the semiconductor package.

The problem to be solved by the technical idea of the present invention is not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the description below.

In order to solve the above problem, the technical idea of the present invention is to provide a plurality of chiplet dies that can be composed of a semiconductor die including one or more cores, and the plurality of chiplet dies are each mounted on an upper package substrate. An individualized upper package is mounted, and a lower module on which the plurality of individualized upper packages are mounted, electrically connecting the plurality of individualized upper packages, and electrically connecting the plurality of individualized upper packages and external connection terminals. A semiconductor package module including a substrate is provided.

In addition, the technical idea of the present invention is a plurality of chiplet dies that may be composed of a semiconductor die including one or more cores, an individualized upper package in which the plurality of chiplet dies are each mounted on an upper package substrate, and a plurality of individualized upper packages. A lower module substrate on which the upper packages are mounted, electrically connecting the plurality of individualized upper packages, and electrically connecting the plurality of individualized upper packages and external connection terminals, each of the plurality of chiplet dies and the upper An upper connection terminal electrically connecting the package substrate, a lower connection terminal electrically connecting the plurality of individualized upper packages and the lower module substrate, and a passive element provided on the plurality of individualized upper packages and the lower module substrate. , is provided along the outer edge of the upper surface of the lower module substrate, includes a stiffener for improving warpage, and each of the plurality of chiplet dies includes an interface circuit configured in a differential manner, and the pitch of the upper connection terminal is smaller than the pitch of the lower connection terminal, the width of the upper connection terminal is smaller than the width of the lower connection terminal, and at least one passive element is provided on the upper surface, lower surface, and inside of the upper package substrate, and the lower module A semiconductor package module is provided, comprising at least one passive element on the top, bottom, and inside of a substrate.

In the semiconductor package according to the technical idea of the present invention, the production cost of the semiconductor package is reduced, the yield of the semiconductor package is improved, and the PI/SI characteristics of the semiconductor package are reduced through a semiconductor package module in which packages including chiplet dies are mounted. can be improved.

1 is a side view of a semiconductor package module according to an embodiment of the present invention.
Figure 2 is an enlarged view showing a portion of the upper package substrate of a semiconductor package module according to an embodiment of the present invention.
Figure 3 is a plan view of a semiconductor package module according to an embodiment of the present invention viewed from above in the -Z-axis direction.
Figure 4 is a side view showing a semiconductor package module according to an embodiment of the present invention.
Figure 5 is a side view showing a semiconductor package module according to an embodiment of the present invention.
Figure 6 is a plan view showing a semiconductor package module according to an embodiment of the present invention.
Figure 7 is a side view showing a semiconductor package module according to an embodiment of the present invention.
Figure 8 is a side view showing a semiconductor package module according to an embodiment of the present invention.
Figure 9 is a side view showing a semiconductor package module according to an embodiment of the present invention.
Figure 10 is a side view showing a semiconductor package module according to an embodiment of the present invention.
Figure 11 is a side view showing a semiconductor device on which a semiconductor package module is mounted according to an embodiment of the present invention.

Hereinafter, embodiments of the technical idea of the present disclosure will be described in detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

1 is a cross-sectional view of a semiconductor package module according to an embodiment of the present invention. Figure 2 is an enlarged view showing a portion of the upper package substrate of a semiconductor package module according to an embodiment of the present invention. Figure 3 is a plan view of a semiconductor package module according to an embodiment of the present invention viewed from above in the -Z-axis direction.

1 to 3, the semiconductor package module 1, which is an embodiment of the present invention, includes an upper package (100a, 100b), a lower module substrate 200, a stiffener 300, and passive elements 410 and 420. It can be included.

The upper package 100 may include an upper package substrate 120, a first semiconductor chip 110a, an upper connection terminal 111, and passive elements 131 and 132. The upper package 100 is each provided with chiplet dies constituting a semiconductor die including one or more cores, so the upper package 100 may be an individualized package. That is, the upper package 100 in this specification may mean an individualized upper package 100.

The upper package substrate 120 may be, for example, a printed circuit board (PCB). The upper package substrate 120 may be mounted on the lower module substrate 200 through the upper connection terminal 111. As shown in FIG. 2 , the upper package substrate 120 may include a core layer 122, a wiring portion 124, a via 125, and a solder resist (SR) layer 126. The planar area of the upper package substrate 120 may be, for example, 50*50 mm2 or less. Of course, the planar area of the upper package substrate 120 is not limited to the above values.

The core layer 122 may include, for example, glass fiber such as FR4 and resin. However, the material of the core layer 122 is not limited thereto. For example, the core layer 122 may include build up films such as Bismaleimide-Triazine (BT) resin, Poly Carbonate (PC) resin, Ajinomoto Build-up Film (ABF), or other laminate resin. . However, the material of the core layer 122 is not limited to the materials described above. The core layer 122 may have a relatively thin thickness. For example, the core layer 122 has a first thickness D1, and the first thickness D1 is about a thickness that allows the formation of stack vias for vias formed on the upper and lower portions of the core layer 122. You can. The first thickness D1 may be, for example, about 0 μm to 200 μm. Depending on the embodiment, the upper package substrate 110 may not include a core layer, and may correspond to the case where the first thickness D1 is 0 μm. In the semiconductor package module 1 of this embodiment, the first thickness D1 of the core layer 122 may be about 40 μm to 100 μm. Of course, the first thickness D1 of the core layer 122 is not limited thereto.

The wiring portion 124 may include an upper wiring portion 124u and a lower wiring portion 124d. Each of the upper wiring portion 124u and the lower wiring portion 124d may include multiple wiring layers. The number of wiring layers of the upper wiring portion 124u and the lower wiring portion 124d may be the same or different. In the semiconductor package module 1 of this embodiment, the wiring unit 124 may include 8 to 14 wiring layers. However, the number of wiring layers of the wiring unit 124 is not limited thereto. For example, in the semiconductor package module 1 of this embodiment, when the wiring portion 124 includes 8 wiring layers and the number of wiring layers in the upper wiring portion 124u and the lower wiring portion 124d is the same, the upper wiring portion 124u 124u may include a PGSG wiring layer toward the top of the core layer 122, and the lower wiring portion 124d may include a SGPG wiring layer toward the bottom of the core layer 122. However, the order of the wiring layers is not limited to the above-described order.

The thickness of the wiring portion 124 may vary depending on the number of wiring layers. The thickness of the wiring portion 124 may be, for example, about 100 to 1000 μm. However, the thickness of the wiring portion 124 is not limited to the above-mentioned numerical range. For example, assuming that the wiring portion 124 has an 8-layer wiring layer structure and a thickness of about 500 μm, and that the upper wiring portion 124u and the lower wiring portion 124d have the same number of wiring layers, the upper wiring portion 124u The second thickness D2 of (124u) may be about 250㎛.

The wiring unit 124 may include metal wiring corresponding to each wiring layer, an interlayer insulating layer that insulates the metal wirings, and metal vias that connect the metal wirings. Metal wires and metal vias may include, for example, copper (Cu). However, the material of metal wiring and metal vias is not limited to Cu. The interlayer insulating layer may include, for example, poly propylene glycol (PPG). Of course, the material of the interlayer insulating layer is not limited to PPG. Meanwhile, due to the material of the interlayer insulating layer, the upper package substrate 110 may correspond to, for example, a thin core PPG PCB.

The SR layer 126 may be a layer that protects the core layer 122 and the wiring portion 124 from external physical and chemical damage. The SR layer 126 may include an upper SR layer 126u on the upper wiring portion 124u and a lower SR layer 126d on the lower wiring portion 124d. The third thickness D3 of each of the upper SR layer 126u and the lower SR layer 126d may be, for example, about 20 μm. However, the thickness of the upper SR layer 126u and the lower SR layer 126d is not limited to 20㎛.

The first semiconductor chip 110a may be mounted on the upper package substrate 120 through the upper connection terminal 111 using a flip-chip method. However, mounting the first semiconductor chip 110a using the wire bonding method is not entirely excluded. The upper connection terminal 111 is different only in size, but its structure and materials are the same as those described for the lower connection terminal 160, which will be described later. Meanwhile, the upper connection terminal 111 may be referred to as a fine bump. An underfill 112 may be filled between the first semiconductor chip 110a and the upper package substrate 120 and between the upper connection terminals 111.

The first upper package 100a may further include a molding layer 140. The molding layer 140 may cover the side surface of the first semiconductor chip 110a and the top surface of the upper package substrate 120. The molding layer 140 may or may not cover the top surface of the first semiconductor chip 110a. The molding layer 140 may include, for example, an epoxy mold compound (EMC). In some embodiments, the horizontal width and horizontal area of the molding layer 140 may have the same value as the horizontal width and horizontal area of the upper package substrate 120. For example, the sidewall of the upper package substrate 120 and the sidewall of the molding layer 140 may be aligned in the vertical direction to form a coplanar plane. Description of the second upper package 100b is omitted to the extent that it overlaps with the first upper package 100a.

The first semiconductor chip 110a may be, for example, a System On Chip (SOC) or a logic chip. Here, the logic chip is an application processor (AP), microprocessor, central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), controller, or application specific integrated circuit (ASIC). It may include etc. In the semiconductor package module 1 of this embodiment, the first semiconductor chip 110a may be a SOC, and may include at least one of a logic circuit, a memory circuit, a digital integrated circuit (IC), a wireless radio frequency integrated circuit (RFIC), and an input/output circuit. It may include one or more circuits. In addition, the first semiconductor chip 110a is an ARM (Advanced RISC Machine) server SOC, including a DRAM I/F for DIMM (Dual In-line Memory Module) and a PCIe (Peripheral Component Interconnect express) I/F that serves as a switch. , and CPU, etc. The first semiconductor chip 110a may have a thickness of about 200 to 800 μm, for example. However, the thickness of the first semiconductor chip 110a is not limited to the above-mentioned numerical range.

In this specification, a semiconductor chip may mean a semiconductor chiplet die. The chiplet die may be a unit constituting a semiconductor die including one or more cores. The chiplet dies can be gathered together to function as one semiconductor die.

The chiplet dies, which can function as a single semiconductor die, can each be individualized and configured into an individualized upper package. Individualized upper packages may be mounted on a lower module substrate, and the individualized upper packages may be electrically connected to each other by the lower module substrate. As the individualized upper packages are mounted on the lower module substrate, the semiconductor package module including the lower module substrate can be configured as a package capable of performing the function of one semiconductor die.

Produced semiconductor chips may have different performances. Each of the produced semiconductor chips can be manufactured into an upper package and tested. The semiconductor package module 1 of the present invention can be produced by testing each of the upper packages and mounting the upper packages showing the same range of performance on the lower module substrate 200. When testing a semiconductor chip after mounting it on a package, the performance of the package may be determined based on a low-performance semiconductor chip, which may result in loss of production yield and performance. Therefore, the semiconductor package of the present invention can improve the performance of the semiconductor package and improve production yield.

As semiconductor products are becoming larger in line with the demand for high performance, problems with yield and manufacturing costs may arise. The present invention produces semiconductor chips as chiplets and packages them individually, thereby improving semiconductor production yield and reducing production costs.

The lower connection terminal 160 may include, for example, a solder ball, a solder bump, or a pillar and a solder ball. Solder balls have a spherical or ball shape and include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), and lead. (Pb) and/or alloys thereof. The pillar has a pillar shape, such as a cylinder or a square pillar, and may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or a combination thereof. However, the materials of solder balls and pillars are not limited to the above materials. In the semiconductor package module 1 of this embodiment, the lower connection terminal 160 may be arranged in an array structure on the lower surface of the upper package substrate 120. Additionally, the lower connection terminal 160 may have a pitch of 0.8 mm or less. For example, the lower connection terminal 160 may have a pitch of about 0.5 mm. However, the pitch of the lower connection terminal 160 is not limited to the above-mentioned values. For reference, an array structure of solder balls, or a board or package containing such a structure, is called BGA (Ball Grid Array). Meanwhile, an underfill 150 may be filled between the first semiconductor chip 110a and the upper package substrate 120 and the lower connection terminal 160.

The passive elements 131 and 132 may be disposed on the lower surface and inside the upper package substrate 120. As shown in FIG. 1, at least one passive element 131 on the lower surface of the upper package substrate 120 may be arranged to be spaced apart from the lower connection terminal. At least one internal passive element 132 may be disposed between the upper and lower surfaces of the upper package substrate 120. The arrangement of the lower passive element 131 and the inner passive element 132 is not limited to the above description. The passive elements 131 and 132 may include, for example, one of an inductor, a resistor, and a capacitor.

The semiconductor package module 1, which is an embodiment of the present invention, may include a second upper package 100b. The description of the second upper package 100b will be omitted to the extent it overlaps with the description of the first upper package 100a.

The semiconductor chip 110a may include a memory cell array. The semiconductor chip 110a may include a physical layer and a direct access area. The physical layer of the semiconductor chip 110a may include interface circuits for communication with devices. Likewise, the second semiconductor chip 110b may also include a memory cell array, a physical layer including an interface circuit, and a direct access region. The first semiconductor chip 110a and the second semiconductor chip 110a may be electrically connected to each other through the lower module substrate 200 including the connection wire 220. The first upper package 100a may receive signals from the second upper package 100b through a physical layer, or may transmit signals to the second upper package 100b. Signals and/or data received through the physical layer of the first semiconductor chip 110a may be transmitted to the second semiconductor chip 110b. Conversely, signals and/or data received through the physical layer of the second semiconductor chip 110b may be transmitted to the first semiconductor chip 110a.

The interface circuit can transmit and receive signals between the semiconductor chips 110a and 110b in a differential or single-ended manner. A signal is generated using a differential signal received from the receiving device 102, and various functions inside the device can be performed based on the differential signal and the generated signal. Alternatively, the receiving device of the communication system may receive data using the received differential signal. For example, the communication system may be a system applied to the previously described interface circuit for transmitting and receiving various signals. Detailed descriptions of the differential method and single-ended method will be omitted in this specification.

The lower module substrate 200 may refer to a substrate on which the upper packages 100a and 100b are mounted. That is, the upper packages 100a and 100b can be mounted on the central portion of the lower module board 200 through the lower connection terminal 160. The lower module substrate 200 may be similar to the upper package substrate 110 described above except for size. Specifically, the planar area of the lower module substrate 200 may be, for example, 100*100 mm ² or less. However, the planar area of the lower module substrate 200 is not limited to the above values.

The lower module substrate 200 may include a core layer, a wiring portion, and an SR layer like the upper package substrate 120. The core layer, wiring portion, and SR layer of the lower module substrate 200 are the same as those described with respect to the core layer 122, wiring portion 124, and SR layer 126 of the upper package substrate 120. Meanwhile, depending on the embodiment, the thickness of each of the core layer, wiring portion, and SR layer of the lower module substrate 200 is greater than that of the corresponding core layer 122, wiring portion 124, and SR layer of the upper package substrate 120. It may be thicker than the SR layer 126. Additionally, depending on the embodiment, the number of wiring layers in the wiring portion of the lower module substrate 200 may be greater than the number of wiring layers in the wiring portion 124 of the upper package substrate 120. For example, the lower module substrate 200 may correspond to a thin core High Density Interconnect (HDI) PCB.

External connection terminals 210 may be arranged in an array structure on the lower surface of the lower module substrate 200. The material and structure of the external connection terminal 210 are the same as those described for the lower connection terminal 160. The pitch p1 of the external connection terminal 210 may be greater than the pitch p2 of the lower connection terminal 160. Additionally, the width w1 of the external connection terminal 210 may be larger than the width w2 of the lower connection terminal 160. For example, the external connection terminal 210 may have a pitch of about 0.8 to 1.3 mm. In the semiconductor package module 1 of this embodiment, the pitch of the external connection terminal 210 may be, for example, about 1.0 mm. However, the pitch of the external connection terminal 210 is not limited to the above-mentioned values.

Passive elements 410 and 420 may be disposed on the lower and upper surfaces of the lower module substrate 200. As shown in FIG. 1, at least one passive element 420 on the top surface of the lower module substrate 200 may be disposed inside the stiffener 300 on the upper surface of the lower module substrate 200. The passive element 410 on the bottom of the lower module substrate 200 may be disposed in the central portion of the lower module substrate 200 and spaced apart from the external connection terminal 210. However, the arrangement of the passive elements 410 and 420 is not limited to the above description. The passive elements 410 and 420 may include, for example, one of an inductor, a resistor, and a capacitor.

The stiffener 300 may be configured to surround an outer shell along the circumference of the lower module substrate 200 on the upper surface of the lower module substrate 200 . For example, the horizontal cross section of the lower stiffener 300 may have a square ring shape surrounding the upper packages 100a and 100b disposed in the central portion, as shown in FIG. 3 . However, the horizontal cross-sectional shape of the stiffener 300 is not limited to a square ring shape. The vertical cross section of the stiffener 300 may have an 'l' shape. By mechanically supporting the lower module substrate 200, the stiffener 300 can improve thermal characteristics of the lower module substrate 200, for example, warpage characteristics of the lower module substrate 200.

The stiffener 300 may include metal such as steel or Cu. However, the material of the stiffener 300 is not limited to this. The stiffener 300 may be adhered and fixed to the lower module substrate 200 through the adhesive layer 310. As an exemplary embodiment, the top surface of the stiffener 300 may have substantially the same height as the top surfaces of the upper packages 100a and 100b or may be higher than the top surfaces of the upper packages 100a and 100b.

The semiconductor package module 1 has a structure in which upper packages 100a and 100b including an upper package substrate 120 are mounted on a lower module substrate 200. Additionally, the upper package substrate 120 and the lower module substrate 200 may have a thin core layer or a coreless structure and may include a small number of wiring layers. Accordingly, it is possible to solve problems caused by a thick core layer, large-sized vias, and a large number of wiring layers in existing semiconductor packages.

For reference, in a semiconductor package including an existing server-side SOC, in order to respond to the increase in size/performance of the SOC, when the semiconductor chip is mounted in a flip-chip structure on one package substrate, the package substrate is 100 *A large size of about 100 mm ² , a thick core layer of 800 μm or more, and many wiring layers of 14 to 22 layers are required. Also large size drill vias due to the thick core layer, and ABF can be used. Accordingly, existing semiconductor packages are disadvantageous in terms of manufacturing cost and delivery of the package substrate, and may also have poor power/signal integrity (PI/SI) characteristics. Meanwhile, in the case of a thick core layer, it is difficult to apply an embedded capacitor (eCAP), and even when applying a land-side capacitor (LSC), there is a problem that the effect of applying the CAP is reduced due to the increasing impedance. The package substrate of these existing semiconductor packages may correspond to a thick core ABF PCB.

In contrast, the semiconductor package module 1 of this embodiment can solve the above-described problem by using the upper and lower package substrates. For example, the semiconductor package module 1 of this embodiment includes a lower module substrate 200 and an upper package substrate 120, and the upper semiconductor chips 110a and 110b are formed on the upper package substrate 120 using a flip-chip method. It can be implemented as . The lower module substrate 200 and the upper package substrate 120 each have a thin core layer or no core layer structure, include 8 to 12 layers of wiring layers, and have small-sized stacked vias or staggered structures. ) may include vias. Accordingly, the manufacturing cost and supply/demand aspects of the package substrate can be improved. In addition, DSC, LSC, and eCAP can be easily applied to improve PI/SI characteristics.

The upper package substrate 120 has a size of about 50*50mm ² , so a 1/4 size mobile PCB can be used, thereby reducing costs. The lower module board 200 has a large size of about 100*100mm ² and implements a pitch of 0.8mm or more, and has a thin core layer and a small wiring layer, enabling cost reduction by utilizing a looser DR (Design Rule) HDI PCB. You can. Furthermore, since capacitors such as eCAP/LSC/DSC can be applied to the lower module substrate 200 and the upper package substrate 120, SI characteristics can be further improved.

Meanwhile, the semiconductor package module 1 of this embodiment may include a stiffener 300. In other words, the semiconductor package module 1 of this embodiment may include a stiffener 300 disposed on the lower module substrate 200. Through this, the warpage characteristics of the lower module substrate 200, which is one of the thermal characteristics of the semiconductor package, can be improved.

Figure 4 is a side view showing a semiconductor package module 1a according to an embodiment of the present invention. Descriptions to the extent they overlap with what was previously explained will be omitted. Referring to FIG. 4 , the top packages 100a and 100b may further include a top passive element 133. The top passive element 133 may be disposed on the upper surface of the upper package substrate 120, spaced apart from the semiconductor chips 110a and 110b, and around the semiconductor chips 110a and 110b. At least one top passive element 133 may be disposed in each top package 100a and 100b. The arrangement of the top passive elements 133 is not limited by the above description.

Figure 5 is a side view showing a semiconductor package module 1b according to an embodiment of the present invention. Descriptions to the extent they overlap with what was previously explained will be omitted. Referring to FIG. 5 , the lower module substrate 200 may include an internal passive element 430. The internal passive element 430 may be disposed between the upper and lower surfaces of the lower module substrate 200. The internal passive element 430 may be located between the lower module substrate 200 on which the first upper package 100a and the second upper package 100b are mounted. The arrangement of the internal passive elements 430 is not limited by the above description.

Figure 6 is a plan view showing a semiconductor package module 1 according to an embodiment of the present invention. Descriptions to the extent they overlap with what was previously explained are omitted. Referring to FIG. 6 , as an exemplary embodiment, the upper package 100 may include four upper packages 100a, 100b, 100c, and 100d. Detailed descriptions of the third upper package 100c and fourth upper package 100d are the same as those of the first upper package 100a and are therefore omitted. The lower module substrate 200 may include connection wires for transmitting and receiving electrical signals between the upper packages 100a, 100b, 100c, and 100d. In addition, each semiconductor chip (110a, 110b, 110c, 110d) constituting each upper package (100a, 100b, 100c, 100d) transmits and receives electrical signals between the upper packages (100a, 100b, 100c, 100d). It may include an interface circuit for The semiconductor package module 1 of the present invention may include a plurality of upper packages, and the number of upper packages is not limited by this specification.

Figure 7 is a side view showing a semiconductor package module 1c according to an embodiment of the present invention. Descriptions to the extent they overlap with what was previously explained will be omitted. Referring to FIG. 7, unlike the semiconductor package module 1 of FIG. 1, it may not include a stiffener 300 and an adhesive layer 310.

Figure 8 is a side view showing a semiconductor package module 1d according to an embodiment of the present invention. Descriptions to the extent that they overlap with the content described above are omitted. Referring to FIG. 8 , the molding layer 140 of one or more of the upper packages 100 may not be formed. As an exemplary embodiment, FIG. 8 shows that the molding layer 140 is not formed in the first upper package 100a, but the molding layer 140 is formed in the second upper package 100b. The molding layer 140 may not be formed in all upper packages, and whether the molding layer 140 is formed is not limited by the present specification.

Figure 9 is a side view showing a semiconductor package module 1e according to an embodiment of the present invention. Descriptions to the extent they overlap with what was previously explained will be omitted. Referring to FIG. 9 , the molding layer 140 of one or more of the upper packages 100 may be configured to cover the upper surface of the upper package substrate. The height of the stiffener 300 may be formed to be the same as the height of the upper surface of the molding layer 140. In an exemplary embodiment, as shown in FIG. 9, the molding layers 140 of the first upper package 100a and the second upper package 100b are each of the first semiconductor chip 110a and the second semiconductor chip 110b. It can be formed to cover the upper surface. In addition, the molding layer 140 is formed so that the height of the upper surface of the molding layer 140 provided in the first upper package 100a is the same as the height of the upper surface of the molding layer 140 provided in the second upper package 100b. This can be formed.

Figure 10 is a side view showing a semiconductor package module 1f according to an embodiment of the present invention. Descriptions to the extent that they overlap with the content described above are omitted. Referring to FIG. 10 , the semiconductor package module 1f may further include a heat sink 320. The heat sink 320 may be in the form of a lid, and the peripheral portion of the side may extend downward and be located on the lower module substrate 200. The heat sink 320 may be fixed to the lower package substrate 200 through an adhesive layer 310.

The heat sink 320 may function to dissipate heat generated from the semiconductor chips 110a and 110b of the upper packages 100a and 100b. The heat sink 320 may include a thermally conductive material with high thermal conductivity. For example, the heat sink 320 may include a metal such as Cu, aluminum (Al), or a carbon-containing material such as graphene, graphite, and/or carbon nanotubes. However, the material of the heat sink 320 is not limited to the materials described above. Depending on the embodiment, the heat sink 320 may include a single metal layer or a plurality of stacked metal layers. Additionally, depending on the embodiment, a heat pipe may be included in the semiconductor package module 1f instead of a heat sink.

In the semiconductor package module 1f of this embodiment, the heat sink 320 may be disposed in a structure that directly contacts the upper surfaces of the semiconductor chips 110a and 110b through the TIM layer 170. Here, the TIM layer 170 may include a thermally conductive and electrically insulating material. For example, the TIM layer 170 may include polymer mixed with metal powder such as silver or copper, epoxy, thermal grease, white grease, or a combination thereof. The heat sink 320 may be replaced with a stiffener having the same shape. Additionally, the heat sink 320 may replace the role of the stiffener described above.

Figure 11 is a side view showing a semiconductor device on which a semiconductor package module is mounted according to an embodiment of the present invention. Descriptions to the extent they overlap with what was previously explained will be omitted. Referring to FIG. 11, the semiconductor package module 1, which is an embodiment of the present invention, may be mounted on the system substrate 500. The semiconductor package module 1 may be electrically connected to the system board 500 through an external connection terminal 210. A system connection terminal 510 is located on the bottom of the system board 500, and can be connected to the outside and configured to transmit and receive electrical signals. For example, the system connection terminal 510 may be configured in the form of a ball, pin, or land, but is not limited thereto.

Above, embodiments of the technical idea of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be modified into other specific forms without changing the technical idea or essential features. You will understand that it can be done. Therefore, the embodiments described above are illustrative in all respects and should not be understood as limiting.

1, 1a, 1b, 1c, 1d, 1e, 1f: semiconductor package module
100: upper package
100a, 100b, 100c, 100d: first to fourth upper packages
110: semiconductor chip
110a, 110b, 110c, 110d: first to fourth semiconductor chips
120: upper package substrate
131, 132, 133: passive elements
220: connection wiring
300: Stiffener
410, 420, 430: passive elements
500: system board

Claims (10)

A plurality of chiplet dies, which may be comprised of a semiconductor die containing one or more cores;
an individualized upper package in which a plurality of the chiplet dies are each mounted on an upper package substrate; and
a lower module substrate on which the plurality of individualized upper packages are mounted, electrically connecting the plurality of individualized upper packages, and electrically connecting the plurality of individualized upper packages and external connection terminals;
A semiconductor package module containing a. According to claim 1,
Each of the plurality of chiplet dies includes an interface circuit,
A semiconductor package module, wherein the interface circuit is configured in a differential manner. According to claim 1,
An upper connection terminal electrically connecting each of the plurality of chiplet dies to the upper package substrate,
Further comprising a lower connection terminal electrically connecting the plurality of individualized upper packages and the lower module substrate,
A semiconductor package module, wherein the pitch of the upper connection terminal is smaller than the pitch of the lower connection terminal, and the width of the upper connection terminal is smaller than the width of the lower connection terminal. According to claim 1,
Each of the individualized upper packages further includes a molding layer covering a top surface of the upper package substrate,
A semiconductor package module, wherein the upper surface of the molding layer is formed to be higher than or equal to the upper surface of the chiplet dies. According to claim 1,
The plurality of individualized upper packages and the lower module substrate further include passive components,
At least one passive element is provided on the top, bottom, and inside of the upper package substrate,
A semiconductor package module comprising at least one passive element on a top, bottom, and interior of the lower module substrate. According to claim 1,
The lower module substrate further includes a core layer,
A semiconductor package module, wherein the core layer has a thickness that allows the formation of stacked vias with respect to vias formed on the upper and lower portions of the core layer. According to claim 1,
It is provided along the outer edge of the upper surface of the lower module substrate and further includes a stiffener for improving warpage,
A semiconductor package module, wherein the stiffener has a square ring shape or a lid shape. According to claim 1,
The lower module substrate further includes a core layer,
A semiconductor package module comprising a core layer having a thickness of 200 μm or less capable of forming stacked vias with respect to vias formed on the top or bottom of the core layer. According to claim 1,
Further comprising a system board on which the semiconductor package module is mounted,
A semiconductor device, wherein the system substrate is electrically connected to the semiconductor package module through the external connection terminal. A plurality of chiplet dies, which may be comprised of a semiconductor die containing one or more cores;
an individualized upper package in which a plurality of the chiplet dies are each mounted on an upper package substrate;
a lower module substrate on which the plurality of individualized upper packages are mounted, electrically connecting the plurality of individualized upper packages, and electrically connecting the plurality of individualized upper packages and external connection terminals;
an upper connection terminal electrically connecting each of the plurality of chiplet dies to the upper package substrate;
a lower connection terminal electrically connecting the plurality of individualized upper packages and the lower module substrate;
Passive elements provided on the plurality of individualized upper packages and the lower module substrate;
a stiffener provided along the outer edge of the upper surface of the lower module substrate to improve warpage; Including,
Each of the plurality of chiplet dies includes an interface circuit configured in a differential manner,
The pitch of the upper connection terminal is smaller than the pitch of the lower connection terminal, and the width of the upper connection terminal is smaller than the width of the lower connection terminal,
A semiconductor package module comprising at least one passive element on the top, bottom, and inside of an upper package substrate, and at least one passive element on the top, bottom, and inside of the lower module substrate.