KR20240059521A - Sub-nano unit data storage memory device using nanofins and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a sub-nano-level information storage memory device using nanofins and a manufacturing method thereof, designed to have ultra-high integration and high efficiency characteristics by designing a new cell structure using sub-nano-level information storage materials. The capacitor of the information storage memory device is a lower electrode of a nanofin structure having a height of a first size and a thickness of a second size smaller than the first size; It includes a dielectric layer formed on the side and bottom surfaces of a trench area formed with a bottom surface at a height less than 1 size; an upper electrode embedded in the trench area with the lower electrode and the dielectric layer interposed therebetween; .

Description

Sub-nano unit data storage memory device using nanofins and method for manufacturing the same}

The present invention relates to an ultra-highly integrated, high-efficiency memory device, and specifically, a sub-nano-level information storage memory device using nanofins to have ultra-highly integrated, high-efficiency characteristics by designing a new cell structure using a sub-nano-level information storage material, and a method of manufacturing the same. It's about.

Efforts to cope with the two-dimensional scale faced by semiconductor integrated circuits since 2018 can be broadly divided into two types.

The first is the More Moore approach, which develops a new patterning technique and makes the device size very small. The second is the More than Moore method, which breaks away from the flat dimension and stacks the device composition layers in a three-dimensional direction in the vertical direction.

The first representative case is the EUV process. In this method, pattern miniaturization is basically the key, and the development of light sources, photoresists, masks, and pellicles related to this are major topics.

The second case is commonly referred to as three-dimensional (3D) integration.

Meanwhile, the IEEE's International Roadmap for Devices and Systems (IRDS), which announces roadmaps for semiconductors and electronic devices, proposed PPAC standards required in terms of devices to effectively respond to future big data, cloud, IoT mobility, etc. in its 2020 report. .

PPAC is an abbreviation that combines the first letters of Performance, Power, Area, and Cost.

Recently, as the number of application fields that require processing large amounts of data at high speeds, such as deep learning and artificial sensation, has increased, PPAC requirements have become increasingly important.

Extreme ultraviolet patterning technology, Gate All Around (GAA) structure, and 3D integration were presented and demonstrated as important technologies for realizing this.

Currently, technological limitations in planar geometric scaling have begun to emerge from various factors. For example, as the channel length became very short, below 10 nm, the short channel effect began to appear as a major device operation failure. In this regard, it has become difficult to control characteristics such as on/off and subthreshold swing of switching elements.

In response to overcoming these technical limitations, overcoming technologies were presented in terms of materials and structures. Representative examples include high dielectric constant gate insulating films such as HfO ₂ or ZrO ₂ , FinFETs with non-planar structures, and Strained Channels that apply stress to the channel.

In addition, research and development in terms of materials and structures continues in response to overcome technological limitations.

For example, the development of existing DRAM products focused on increasing integration by reducing the circuit line width, but as the line width entered the 10 nm range, physical limitations such as current leakage and interference from capacitors increased significantly. Although new materials and equipment, such as high dielectric constant (high K) deposition materials and extreme ultraviolet (EUV), have been introduced to prevent this, the semiconductor industry predicts that there will be great difficulties in miniaturization below 10 nanometers.

Therefore, memory chips such as 3D DRAM with a new structure that breaks the existing paradigm are being proposed.

As an example, an INTEL 3D DRAM model as shown in Figure 1 is being proposed.

Intel's 1T-MC structure is,

A structure where 4 layers of PL1/insulation/PL2/insulation/PL3/insulation/PL4 are stacked on top of the BCAT transistor, a hole is dug, HZO (AFE thin film) is deposited on the wall of the hole by ALD, a top electrode is created, and connected to the BCAT below. am.

However, although this structure has the advantage of being simple, there is a structural limitation that the PL metal must be deposited sufficiently thick to store sufficient charge, and this structure has problems of increased manufacturing costs and reduced uniformity.

Therefore, there is a need to develop technology for a new cell structure using subnano-level information storage materials with ultra-high integration and high efficiency characteristics.

Republic of Korea Patent Publication No. 10-2022-0146336 Republic of Korea Patent Publication No. 10-2021-0098834 Republic of Korea Patent Publication No. 10-2022-0156434

The present invention is intended to solve the problems of memory devices of the prior art, and is a sub-nano-level information storage memory device using nanofins that has ultra-high integration and high efficiency characteristics by designing a new cell structure using sub-nano-level information storage materials, and the same. The purpose is to provide a manufacturing method.

The present invention designs a sub-nano scale capacitor by applying a scale-free thin film material, and maintains similarity to the commercialization process in the manufacturing process, making it advantageous in terms of manufacturing cost and securing productivity and device characteristics. The purpose is to provide a nanoscale information storage memory device and a manufacturing method thereof.

The present invention implements a multi-capacitor with a nanofin structure, allowing nanoelectrodes with micro-level height and low resistance characteristics compared to nanowires to be manufactured without using the EUV process, and sub-nano unit information storage using nanofins. The purpose is to provide a memory device and a manufacturing method thereof.

The present invention creates nanoscale fins through ALD deposition on the trench sidewall, and manufactures multi-capacitors with nanofin structures in a horizontally overlapping form rather than vertically stacked, forming a metal layer with a thickness of hundreds of nanometers and forming a hole in the thick metal. The purpose is to provide a sub-nano unit information storage memory device using nanofins and a manufacturing method thereof that can secure a higher level of memory capacity by increasing the number of multi-capacitors without processing.

The purpose of the present invention is to provide a sub-nano unit information storage memory device using nanofins, which is advantageous in securing a higher level of memory capacity by vertically stacking horizontally overlapping multi-capacitors, and a method of manufacturing the same.

Other objects of the present invention are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the above object, the subnano unit information storage memory device using nanopins according to the present invention has a capacitor of the subnano unit information storage memory device using nanopins, the height of the first size and the first size smaller than the first size. A lower electrode of a nanofin structure having a thickness of a second size; A trench area formed inside the lower electrode of the nanofin structure with a bottom surface at a height smaller than the height of the first size in a form that is open in the upper direction. It is characterized in that it includes a dielectric layer formed on the side and bottom surfaces; an upper electrode embedded in the trench area with the lower electrode and the dielectric layer interposed therebetween.

Here, the lower electrode of one nanofin structure is characterized in that a plurality of trench regions are formed in a separate form on the inside to form a plurality of capacitors.

Additionally, the upper electrode of each capacitor formed in each trench region is connected to the drain of a different cell selection transistor.

And the capacitor of the sub-nano unit information storage memory device using nanofins is characterized by having an overlapping structure that is repeated in the horizontal direction.

In order to increase capacity, the nanofin-structured capacitors are characterized in that layers having an overlapping structure in which nanofin-structured capacitors are repeated in the horizontal direction are repeatedly stacked in the vertical direction.

And the layer having an overlapping structure in which nanofin-structured capacitors are repeated in the horizontal direction is formed on a substrate including a Buried Channel Array Transistor (BCAT).

In addition, a plurality of capacitors that form a pair with one lower electrode as a common electrode are each driven independently.

In order to construct a plurality of capacitors that form a pair with one lower electrode as a common electrode, a plurality of separate trench regions are formed inside the lower electrode of the nano-fin structure, and a dielectric layer is formed in each trench region. and upper electrodes are formed, the upper electrodes are connected to the drains of different cell selection transistors, and the cell is selected by selective driving of the word line (W/L) and the bit line (B/L).

Then, a cell is selected by selectively driving the word line (W/L) and bit line (B/L), and when one lower electrode having a horizontally repeated overlapping structure is selected and driven, the cell is selected and driven by the voltage difference. The dielectric layer in between causes polarization, and the cell selection transistor of other neighboring capacitors is closed, so the dielectric layer is not affected.

Additionally, when the selected cell is in operation, the nanofins constituting the lower electrodes of other unselected cells are characterized in that they are in a floating state.

And the dielectric layer is characterized by depositing an AFE (Antiferroelectric) film or FE (Ferroelectric) film through an ALD (Atomic Layer Deposition) process.

And the dielectric layer is characterized as an HfO ₂ thin film deposited through an ALD (Atomic Layer Deposition) process.

In addition, Fe-RAM non-volatile memory is constructed using the ferroelectricity of the HfO ₂ thin film, or DRAM volatile memory is constructed using the antiferroelectricity of the HfO ₂ thin film.

A method of manufacturing a sub-nano unit information storage memory device using nanofins according to the present invention for achieving another purpose includes the steps of forming a multi-layer structure material layer and etching it to a certain depth to define a first direction capacitor formation area; Filling the directional capacitor formation area with an insulating material layer and forming an upper spacer layer on the entire upper surface; Etching the multilayer structure material layer on which the upper spacer layer is formed to define a second directional capacitor formation area perpendicular to the first direction. ; Forming a nanofin forming material layer in the second direction capacitor forming area; Filling the second direction capacitor forming area with an insulating material layer and removing the exposed insulating material layer in the first direction capacitor forming area to form a nanofin forming material. It is characterized in that it includes the step of exposing the side of the layer; forming a dielectric layer on the side of the exposed nanofin forming material layer and forming an upper electrode layer.

Here, the step of forming the nanofin forming material layer is characterized by forming TiN and Al ₂ O ₃ alternately and repeatedly on the bottom and side surfaces of the second direction capacitor formation area through an ALD (Atomic Laver Deposition) process. do.

In the step of exposing the side of the nanofin forming material layer, the exposed insulating material layer in the first direction capacitor forming area is removed using a window wet etch process to create an open area for forming a dielectric layer and a core node. It is characterized by exposing the side of the nanofin forming material layer.

And in the step of forming a dielectric layer on the side of the exposed nanofin forming material layer, the dielectric layer is formed by depositing an HfO ₂ thin film on the exposed side of the nanofin forming material layer through an ALD (Atomic Layer Deposition) process. .

Then, the step of forming an upper electrode layer is performed, forming a contact hole in the center of the second direction capacitor formation area, filling the contact hole with the lower BCAT and connection contact metal layer, and forming the remaining upper spacer layer and lower insulating film. and further comprising the step of separating each nanofin by removing the exposed nanofin forming material layer.

And the separated nanofins become the lower electrodes of each capacitor and are driven independently.

Then, the steps of forming a multi-layered structure material layer, etching to a certain depth to form a first direction capacitor formation area, filling the first direction capacitor formation area with an insulating material layer, and forming an upper spacer layer on the entire upper surface are repeated. A step of defining a second direction capacitor formation area perpendicular to the first direction is performed to form a layer in which nanofin-structured capacitors are formed in a vertically stacked structure.

As described above, the sub-nano unit information storage memory device using nanofins and its manufacturing method according to the present invention have the following effects.

First, a new cell structure using sub-nanoscale information storage materials is designed to provide a memory device with ultra-high integration and high efficiency characteristics.

Second, scale-free thin film materials are applied to design sub-nanoscale capacitors, and the manufacturing process maintains similarity to the commercialization process, making it advantageous in terms of manufacturing cost and securing productivity and device characteristics.

Third, by implementing a multi-capacitor with a nanofin structure, nanoelectrodes with micro-level height and low resistance characteristics compared to nanowires can be manufactured without using the EUV process.

Fourth, a process of creating nanoscale fins through ALD deposition on the trench sidewall and manufacturing multi-capacitors with nanofin structures in a horizontally overlapping form rather than vertically stacked, forming a metal layer hundreds of nanometers thick and forming holes in the thick metal. By increasing the number of multi-capacitors, a higher level of memory capacity can be secured.

Fifth, it is advantageous to secure a higher level of memory capacity by vertically stacking multi-capacitors in the form of horizontal overlap.

Figure 1 is an INTEL 3D DRAM model configuration diagram
Figure 2 is a configuration diagram showing an example of a capacitor with a nanofin structure according to the present invention.
Figure 3 is a configuration diagram showing the manufacturing process concept of a capacitor with a nanofin structure according to the present invention.
Figure 4 is a basic structural diagram of a 1T-MC array of a sub-nano unit information storage memory device using nanopins according to the present invention.
5A and 5B are circuit configuration and operation waveform diagrams of a 1T-3C structure sub-nano unit information storage memory device.
Figures 6a and 6b are configuration diagrams showing the operating principles of Fe-RAM and DRAM using a capacitor with a nanofin structure according to the present invention.
7A to 7O are cross-sectional process diagrams of a sub-nano unit information storage memory device using nanofins according to the present invention.
8A to 8Q are cross-sectional process views of a sub-nano unit information storage memory device using nanofins in a multi-stage structure according to the present invention.

Hereinafter, a preferred embodiment of the sub-nano unit information storage memory device using nanofins and its manufacturing method according to the present invention will be described in detail as follows.

The characteristics and advantages of the sub-nano unit information storage memory device using nanofins and the manufacturing method thereof according to the present invention will become apparent through the detailed description of each embodiment below.

Figure 2 is a configuration diagram showing an example of a capacitor with a nanofin structure according to the present invention.

The terms used in this disclosure are general terms that are currently widely used as much as possible while considering the functions in this disclosure, but this may vary depending on the intention or precedent of a person working in the art, the emergence of new technology, etc. In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the relevant invention. Therefore, the terms used in this disclosure should be defined based on the meaning of the term and the overall content of this disclosure, rather than simply the name of the term.

When it is said that a part "includes" a certain element throughout the specification, this means that, unless specifically stated to the contrary, it does not exclude other elements but may further include other elements.

The sub-nano unit information storage memory device using nanofins and its manufacturing method according to the present invention are designed to have ultra-high integration and high efficiency characteristics by designing a new cell structure using sub-nano unit information storage materials.

To this end, the present invention designs a sub-nanoscale capacitor by applying scale-free thin film materials in order to be advantageous in terms of manufacturing cost and secure productivity and device characteristics, and maintains similarity to the commercialization process in the manufacturing process. Configuration may be included.

The present invention may include a configuration that implements a multi-capacitor with a nanofin structure so that a nanoelectrode with a micro-level height and low resistance characteristics compared to a nanowire can be manufactured without using an EUV process.

In order to secure a higher level of memory capacity by increasing the number of multi-capacitors without the process of forming a metal layer with a thickness of hundreds of nanometers and forming holes in the thick metal, the present invention creates nanoscale pins through ALD deposition on the trench sidewall. It may include manufacturing a multi-capacitor with a nanofin structure in a horizontally overlapping form rather than vertically stacked.

The present invention may include a configuration that is advantageous in securing a higher level of memory capacity by vertically stacking multi-capacitors in the form of horizontal overlap.

As shown in FIG. 2, the capacitor of the nanofin structure according to the present invention includes a lower electrode 100 of the nanofin structure having a height of a first size and a thickness of a second size smaller than the first size, and a lower electrode of the nanofin structure. A dielectric layer 300 formed on the side and bottom surfaces of the trench area, which is formed inside the electrode 100 in a form that is open in the upper direction and has a bottom surface at a height less than the height of the first size, and a lower electrode ( 100) and an upper electrode 200 formed to be buried in the trench area with the dielectric layer 300 interposed therebetween.

Here, the nanofin-structured capacitor has an overlapping structure that is repeated in the horizontal direction. A plurality of capacitors that form a pair using one lower electrode 100 as a common electrode may be driven independently.

In order to form a plurality of capacitors using one lower electrode 100 as a common electrode, a plurality of separate trench regions are formed inside the lower electrode 100 of the nano-fin structure, A dielectric layer 300 and an upper electrode 200 are formed in each trench area and connected to the drains of different cell transistors, and cells are selected by selective driving of the word line (W/L) and bit line (B/L). do.

A cell is selected by selective driving of the word line (W/L) and bit line (B/L), and any one lower electrode 100 having a horizontally repeated overlapping structure is selected to connect ground and +-V. When given, the dielectric layer 300 therebetween is polarized due to the voltage difference, and the cell selection transistor of other neighboring capacitors is closed, so the dielectric layer 300 is not affected.

At this time, the nanofins constituting the other unselected lower electrode 100 are in a floating state.

And in order to increase memory capacity, layers having an overlapping structure in which nanofin-structured capacitors are repeated in the horizontal direction are repeatedly stacked in the vertical direction.

And a layer having an overlapping structure in which nanofin-structured capacitors are repeated in the horizontal direction is formed on a substrate containing a Buried Channel Array Transistor (BCAT).

And the dielectric layer 300 may be a HfO ₂ thin film, but is not limited thereto.

The HfO ₂ thin film, which is a fluorite oxide film structure to which silicon is added, has ferroelectric (FE) characteristics.

The present invention uses HfO ₂ thin film as a dielectric layer so that it can be used in new 3D DRAM or non-volatile ferroelectric random access memory (FeRAM) and ferroelectric field effect transistor (FeFET).

The existing perovskite structure does not exhibit ferroelectricity at a thickness of 100 nm or less, so a high thickness of 100 nm or more is required, whereas HfO ₂ , a fluorite structure, has a relatively high bandgap energy (5.7ev) and a 10 nm level. Ferroelectric properties appear even at thin thickness. The implementation of such a thin film can be said to be an advantage in the integration of devices with 3D structures such as DRAM capacitors and stacked structures.

Figure 3 is a configuration diagram showing the manufacturing process concept of a capacitor with a nanofin structure according to the present invention.

Figure 3 is for explaining the manufacturing concept of the nanofin structure capacitor according to the present invention as shown in Figure 2, and the manufacturing process of the nanofin structure capacitor is not limited thereto.

The process defines a multi-capacitor formation area on the insulating material layer, repeatedly deposits Pt and Al ₂ O ₃ using an ALD (Atomic Layer Deposition) process to form nanofins, and performs trench etching for capacitor patterning.

Next, AFE (Antiferroelectric) films or FE (Ferroelectric) films are deposited using the ALD process, and a top electrode is created in the trench area to complete the capacitor.

As such, the core process of the nanofin structure capacitor according to the present invention is to create nanoscale fins through ALD deposition on the trench sidewall.

Through this process, multi-capacitors with nanofin structures are manufactured in a horizontally stacked form rather than vertically stacked, creating a higher level of capacity than current DRAM.

Figure 4 is a basic structural diagram of a 1T-MC array of a sub-nano unit information storage memory device using nanopins according to the present invention.

In order to construct a plurality of capacitors that form a pair using a lower electrode of a nanofin structure as a common electrode, a plurality of separate trench regions are formed inside the lower electrode of the nanofin structure, and each trench A structure in which a dielectric layer and an upper electrode are formed in an area, the upper electrodes are connected to the drains of different cell selection transistors, and cells are selected by selective driving of the word line (W/L) and bit line (B/L). It shows an example.

A layer with an overlapping structure in which nanofin-structured capacitors are repeated in the horizontal direction is formed on a substrate containing a buried channel array transistor (BCAT), and is used to select a word line (W/L) and a bit line (B/L) for cell selection. ) It shows the connection structure.

Figures 5a and 5b are circuit configuration and operation waveform diagrams of a sub-nano unit information storage memory device with a 1T-3C structure.

Figure 5a shows a structure in which the nanofin (PL) constituting the lower electrode has three nanofin electrodes, PL1, PL2, and PL3, and two first and second capacitors are made at each electrode.

And the upper electrodes of the first capacitor of PL1, the first capacitor of PL2, and the first capacitor of PL3 are connected to the cell selection transistors of the first word line (WL1) and the bit line (BL) to form a first cell, and PL1 The upper electrodes of the second capacitor of , the second capacitor of PL2, and the second capacitor of PL3 are connected to the cell selection transistors of the second word line (WL2) and the bit line (BL) to form a second cell.

A cell is selected by selectively driving the word line (WL1) (WL2) and the bit line (BL), and any one of the lower electrodes (PL1, PL2, PL3) having a horizontally repeated overlapping structure is selected to ground and When +-V is applied, the dielectric layer between them is polarized due to the voltage difference, and the cell selection transistor of other neighboring capacitors is closed, so the dielectric layer is not affected.

At this time, nanofins constituting other unselected lower electrodes are in a floating state.

Figures 6a and 6b are configuration diagrams showing the operating principles of Fe-RAM and DRAM using a capacitor with a nanofin structure according to the present invention.

Figure 6a shows the capacitor operating characteristics of the nanofin structure when constructing an Fe-RAM non-volatile memory using the ferroelectricity of the HfO ₂ thin film.

Figure 6b shows the capacitor operating characteristics of the nanofin structure when constructing a DRAM volatile memory using the antiferroelectricity of the HfO ₂ thin film.

The process of the sub-nano unit information storage memory device using nanopins according to the present invention will be described in detail as follows.

In the following description, the material deposition process is PVD (Physical Vapor Deposition) or APCVD (Atmosphere CVD), LPCVD (Low pressure CVD), PECVD (Plasma Enhanced CVD), HDPCVD (High pressure CVD), including Ebeam evaporation, Thermal Evaporation, Sputtering Deposition, etc. CVD (Chemical Vapor Deposition) or ALD (Atomic Laver Deposition) processes, including -Density Plasma CVD), MOCVD (Metal-Organic CVD), etc. may be selected and used, but are not limited thereto.

Detailed process conditions of the material deposition process can be controlled according to required device characteristics and materials used.

And the insulating material used may be SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , etc., but is not limited thereto.

Additionally, the etching process for capacitor patterning can optionally be dry etching, which removes specific areas using reactive gases, ions, etc., or wet etching, which involves etching through a chemical reaction using a solution.

Detailed process conditions of the etching process can be controlled depending on device requirements, materials used, etc.

Figures 7a to 7o are cross-sectional views of the process of a sub-nano unit information storage memory device using nanofins according to the present invention.

First, as shown in FIG. 7A, multi-layered material layers 11, 12, and 13 are formed on a substrate having a BCAT TR to define a nanofin-structured capacitor region.

The multilayer structure material layers 11, 12, and 13 may be formed by repeatedly depositing (SiO ₂ , Si ₃ N ₄ ) through a PECVD process, but are not limited thereto.

Then, as shown in FIG. 7B, the multi-layer structure material layers 11, 12, and 13 are etched to a certain depth to form a trench in the first direction to form a first direction capacitor for dielectric material deposition and upper electrode formation in the subsequent process. Define forming region 14.

And, as shown in FIG. 7C, the first direction capacitor formation area 14 is filled with an insulating material layer 15.

Here, the insulating material layer 15 may be an oxide film such as Al ₂ O ₃ , but is not limited thereto.

Next, as shown in FIG. 7D, an upper spacer layer 16 is formed on the upper entire surface filled with the insulating material layer 15.

The upper spacer layer 16 may use Si ₃ N ₄ , but is not limited thereto.

And, as shown in FIG. 7E, the multi-layer structure material layers 11 and 12 on which the upper spacer layer 16 is formed are etched to form a trench in a second direction perpendicular to the first direction to form a second direction capacitor formation region 17. ) is defined.

Next, as shown in FIG. 7f, the nanofin forming material layer 18 is formed through an ALD (Atomic Laver Deposition) process.

The nanofin forming material layer 18 may be formed by alternately and repeatedly stacking TiN and Al ₂ O ₃ on the bottom and side surfaces of the second direction capacitor forming region 17, and the materials and deposition methods used may vary. there is.

And as shown in FIG. 7G, the second direction capacitor formation area 17 where the nanofin formation material layer 18 is formed is filled with the insulating material layer 19.

Here, the insulating material layer 19 may be an oxide film such as Al ₂ O ₃ , but is not limited thereto.

Next, as shown in Figure 7h, a side etching process is performed to define an area for forming the dielectric layer and core node.

And, as shown in FIG. 7I, an open area 20 is defined to form a dielectric layer and a core node by removing the exposed insulating material layer of the first direction capacitor formation area 14 using a window wet etch process. Thus, the side surface of the nanofin forming material layer 18 is exposed.

Next, as shown in FIG. 7J, a dielectric layer 21 is formed by depositing an HfO ₂ thin film on the exposed side of the nanofin forming material layer 18 through an atomic layer deposition (ALD) process.

And, as shown in FIG. 7K, TiN is deposited in the open area 20 where the dielectric layer 21 is formed through an ALD (Atomic Layer Deposition) process to form the upper electrode layer 22.

Next, as shown in FIG. 7L, a contact hole 23 is formed in the center of the second direction capacitor formation area 17, and as shown in FIG. 7M, a contact metal layer 24 connected to the lower BCAT is formed in the contact hole 23. ).

As shown in Figure 7n, the remaining upper spacer layer 16 and lower insulating film 12 are removed, and the exposed nanofin forming material layer 18 is removed to separate each nanofin.

Next, as shown in FIG. 7O, the insulating material layer 25 such as an oxide film is filled to form a support material layer 25 that supports the nanofin-structured capacitor.

In the capacitor manufacturing process of the sub-nano unit information storage memory device using nanofins according to the present invention, side etching is performed using a window wet etch process as shown in FIG. 7I to form a nanofin forming material layer 18. The reason for exposing the side surface is that it is more advantageous to maintain the flatness of the top surface of the nanofin than using a top etching process.

Maintaining the flatness of the top surface of the nanofin through this process is advantageous for the subsequent vertical stacking process.

In order to increase memory capacity, the manufacturing process of a structure in which layers of nanofin-structured capacitors having an overlapping structure repeated in the horizontal direction are repeatedly stacked in the vertical direction is as follows.

Figures 8a to 8q are cross-sectional views of the process of a sub-nano unit information storage memory device using nanofins in a multi-stage structure according to the present invention.

First, as shown in FIG. 8A, multi-layered material layers 31, 32, and 33 are formed on a substrate having a BCAT TR to define a nanofin-structured capacitor region.

The multi-layer structure material layers 31, 32, and 33 may be formed by repeatedly depositing (SiO ₂ , Si ₃ N ₄ ) through a PECVD process, but are not limited thereto.

Then, as shown in FIG. 8B, the multi-layer structure material layers 31, 32, and 33 are etched to a certain depth to form a trench in the first direction to form a first direction capacitor for dielectric material deposition and upper electrode formation in the subsequent process. Define forming region 34.

And as shown in FIG. 8C, the first direction capacitor formation area 34 is filled with an insulating material layer 35.

Here, the insulating material layer 35 may be an oxide film such as Al ₂ O ₃ , but is not limited thereto.

Next, as shown in FIG. 8D, an upper spacer layer 36 is formed on the entire upper surface filled with the insulating material layer 35.

The upper spacer layer 36 may use Si ₃ N ₄ , but is not limited thereto.

And, as shown in FIG. 8E, the second capacitor layer 38 is formed by repeating the processes of FIGS. 8A to 8D on the first capacitor layer 37 on which the upper spacer layer 36 is formed.

Next, as shown in FIG. 8F, the stacked first and second capacitor layers are etched to form a trench in a second direction perpendicular to the first direction to form second direction capacitors in the first and second capacitor layers 37 and 38. Define forming region 39.

Next, as shown in FIG. 8g, a nanofin forming material layer 40 is formed in the second direction capacitor formation area 39 of the first and second capacitor layers 37 and 38 through an ALD (Atomic Laver Deposition) process. .

The nanofin forming material layer 40 may be formed by alternately and repeatedly stacking TiN and Al ₂ O ₃ on the bottom and side surfaces of the second direction capacitor forming region 39, and the materials and deposition methods used may vary. there is.

And, as shown in FIG. 8H, the second direction capacitor formation area 39 where the nanofin formation material layer 40 is formed is filled with the insulating material layer 41.

Here, the insulating material layer 41 may be an oxide film such as Al ₂ O ₃ , but is not limited thereto.

Next, as shown in FIG. 8I, a side etching process is performed to define an area for forming the dielectric layer and the core node.

And, as shown in FIG. 8J, an open area 42 is defined to form a dielectric layer and a core node by removing the exposed insulating material layer of the first direction capacitor formation area 34 using a window wet etch process. Thus, the side surfaces of the nanofin forming material layers of the first and second capacitor layers 37 and 38 are exposed.

Next, as shown in FIG. 8K, an HfO ₂ thin film is deposited on the side of the exposed nanofin forming material layer through an ALD (Atomic Layer Deposition) process to form a dielectric layer 43 on the first and second capacitor layers 37 and 38. forms.

And, as shown in FIG. 8L, the upper electrode layer 44 is formed by depositing TiN in the open area 42 of the first and second capacitor layers 37 and 38 where the dielectric layer 43 is formed through an atomic layer deposition (ALD) process. It's okay.

Next, as shown in FIG. 8M, the remaining upper spacer layer and lower insulating film of the first and second capacitor layers 37 and 38 are removed, and the exposed nanofin forming material layer 40 is removed as shown in FIG. 8N. Remove and separate each nanofin.

And, as shown in Figure 8o, the empty space is filled with an insulating material through the nano-fin separation process, and a contact hole 45 is formed in the center of the second direction capacitor formation area 39 as shown in Figure 8p, and as shown in Figure 8q. Likewise, the contact hole 45 is filled with the lower BCAT and the connecting contact metal layer 46.

The sub-nano unit information storage memory device using nanofins and its manufacturing method according to the present invention described above are designed to have ultra-high integration and high efficiency characteristics by designing a new cell structure using sub-nano unit information storage material, and ALD on the trench sidewall. Nano-scale fins are created through deposition, and multi-capacitors with nano-fin structures are manufactured in a horizontally overlapping form rather than vertically stacked, increasing the number of multi-capacitors without the process of forming a metal layer with a thickness of hundreds of nanometers and forming holes in thick metal. This was done to secure a higher level of memory capacity.

As described above, it will be understood that the present invention is implemented in a modified form without departing from the essential characteristics of the present invention.

Therefore, the specified embodiments should be considered from an illustrative rather than a limiting point of view, the scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the equivalent scope are intended to be included in the present invention. It will have to be interpreted.

100. Lower electrode
200. Upper electrode
300. Dielectric layer

Claims (20)

The capacitor of a sub-nano unit information storage memory device using nanopins,
a lower electrode having a nanofin structure having a first height and a second thickness smaller than the first size;
A dielectric layer formed on the side and bottom surfaces of the trench area formed inside the lower electrode of the nanofin structure, with the bottom surface at a height less than the height of the first size, in a form that is open in the upper direction;
A sub-nano unit information storage memory device using nanofins, comprising an upper electrode embedded in the trench area with a lower electrode and a dielectric layer interposed therebetween. The method of claim 1, wherein the lower electrode of any one nanofin structure includes:
A sub-nano unit information storage memory device using nanofins, characterized in that a plurality of trench regions are formed in a separate form on the inside to form a plurality of capacitors. The sub-nano unit information storage memory device using nanofins according to claim 2, wherein the upper electrode of each capacitor formed in each trench area is connected to the drain of a different cell selection transistor. The capacitor of claim 1, wherein the capacitor of the sub-nano unit information storage memory device using nanofins is,
A sub-nano unit information storage memory device using nanofins, characterized by having an overlapping structure that is repeated in the horizontal direction. The method of claim 4, to increase capacity,
A sub-nano unit information storage memory device using nanofins, characterized in that layers having an overlapping structure in which nanofin-structured capacitors are repeated in the horizontal direction are repeatedly stacked in the vertical direction. The sub-nano unit information using nanofins according to claim 4, wherein the layer having an overlapping structure in which nanofin-structured capacitors are repeated in the horizontal direction is formed on a substrate including a Buried Channel Array Transistor (BCAT). Storage memory device. The sub-nano unit information storage memory device according to claim 1, wherein the plurality of capacitors forming a pair with one lower electrode as a common electrode are each driven independently. The method of claim 7, wherein in order to configure a plurality of capacitors in a pair with one lower electrode as a common electrode,
A plurality of separate trench regions are formed inside the lower electrode of the nanofin structure,
A dielectric layer and an upper electrode are formed in each trench area, the upper electrodes are connected to the drain of different cell selection transistors, and the cell is selected by selective driving of the word line (W/L) and bit line (B/L). A sub-nano unit information storage memory device using nano pins. The method of claim 8, wherein a cell is selected by selective driving of a word line (W/L) and a bit line (B/L),
When one lower electrode having a horizontally repeated overlapping structure is selected and driven, the dielectric layer between them is polarized due to the voltage difference.
A sub-nano unit information storage memory device using nanofins, wherein the cell selection transistor is closed to other neighboring capacitors, so the dielectric layer is not affected. The sub-nano unit information storage memory device using nanofins according to claim 9, wherein the nanofins constituting the lower electrodes of other unselected cells are in a floating state when the selected cell is operating. The method of claim 1, wherein the dielectric layer is:
A sub-nano unit information storage memory device using nanofins, characterized in that AFE (Antiferroelectric) film or FE (Ferroelectric) film is deposited and formed through an ALD (Atomic Layer Deposition) process. The method of claim 1, wherein the dielectric layer is:
A sub-nano unit information storage memory device using nanofins, characterized in that it is an HfO ₂ thin film deposited and formed through an ALD (Atomic Layer Deposition) process. The method of claim 12, wherein the Fe-RAM non-volatile memory is constructed using the ferroelectricity of the HfO ₂ thin film, or
A sub-nano unit information storage memory device using nanofins, characterized in that DRAM volatile memory is constructed using the antiferroelectricity of the HfO ₂ thin film. forming a multi-layered material layer and etching it to a certain depth to define a first direction capacitor formation area;
Filling the first direction capacitor formation area with an insulating material layer and forming an upper spacer layer on the entire upper surface;
etching the multi-layer structure material layer on which the upper spacer layer is formed to define a second direction capacitor formation area perpendicular to the first direction;
forming a nanofin forming material layer in the second direction capacitor forming area;
filling the second direction capacitor formation area with an insulating material layer and removing the exposed insulating material layer in the first direction capacitor formation area to expose the side of the nanofin formation material layer;
A method of manufacturing a sub-nano unit information storage memory device using nanofins, comprising: forming a dielectric layer on a side of the exposed nanofin forming material layer and forming an upper electrode layer. The method of claim 14, wherein forming the nanofin forming material layer comprises:
A sub-nano unit information storage memory device using nanofins, which is formed by alternately and repeatedly stacking TiN and Al ₂ O ₃ on the bottom and sides of the second direction capacitor formation area through the ALD (Atomic Laver Deposition) process. Manufacturing method. The method of claim 14, wherein in exposing the side of the nanofin forming material layer,
A window wet etch process is used to remove the exposed insulating material layer in the first direction capacitor formation area to define an open area for forming the dielectric layer and core node, thereby exposing the side of the nanofin formation material layer. A method of manufacturing a sub-nano unit information storage memory device using nanofins. 15. The method of claim 14, wherein in forming a dielectric layer on a side of the exposed nanofin forming material layer,
A method of manufacturing a sub-nano unit information storage memory device using nanofins, characterized in that a dielectric layer is formed by depositing an HfO ₂ thin film on the side of the exposed nanofin forming material layer through an ALD (Atomic Layer Deposition) process. 15. The method of claim 14, wherein forming an upper electrode layer is performed,
Forming a contact hole in the center of the second direction capacitor formation area and filling the contact hole with the lower BCAT and connection contact metal layer;
A sub-nano unit information storage memory device using nanofins, further comprising the steps of removing the remaining upper spacer layer and lower insulating film and removing the exposed nanofin forming material layer to separate each nanofin. Manufacturing method. The method of claim 18, wherein the separated nanofins become lower electrodes of each capacitor and are driven independently. 15. The method of claim 14, wherein a multi-layer structure material layer is formed, etched to a certain depth to form a first direction capacitor formation region, filling the first direction capacitor formation region with an insulating material layer, and forming an upper spacer layer on the entire upper surface. repeat the steps,
A sub-nano unit information storage memory device using nanofins, characterized in that the step of defining a second direction capacitor formation area perpendicular to the first direction is performed to form a layer in which nanofin structure capacitors are formed in a vertically stacked structure. Manufacturing method.

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