KR20240057309A - Asymmetric nand gate circuit, clock gating cell and integrated circuit including the same - Google Patents

Abstract

An asymmetric NAND gate circuit, a clock gating cell, and an integrated circuit including the same are disclosed. The clock gating cell is an inverter circuit that inverts the clock signal to generate an inverted clock signal, receives the inverted clock signal, enable signal, and scan enable signal, and outputs a first internal signal through the first node. A first control stage, receiving a first internal signal, a clock signal, an enable signal, and a scan enable signal, and a second control stage outputting a second internal signal through a second node, and receiving the second internal signal. and an output driver that outputs an output clock signal, and the output driver provides a third internal signal to the first control stage and the second control stage through a third node.

Description

Asymmetric NAND gate circuit, clock gating cell, and integrated circuit including same {ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME}

The technical idea of the present disclosure relates to a clock gating cell, and more specifically, to a clock gating cell with low power and an integrated circuit including the same.

Integrated circuits that process digital signals can operate in synchronization with a clock. For example, an integrated circuit may include a digital circuit that generates an output signal by processing an input signal in response to a rising edge and/or falling edge of a clock, provided that no edge of the clock occurs. In this case, the operation of the digital circuit may be interrupted. Clock gating can refer to stopping or resuming the operation of a digital circuit by selectively providing a clock, and power consumed by the digital circuit can be reduced by clock gating.

The integrated circuit may include a clock gating circuit that selectively outputs a clock in response to a control signal, that is, a clock gating cell, and the clock gating cell interrupts and resumes the supply of the clock to prevent malfunction of the digital circuit receiving the clock. You may be required to perform.

The technical idea of the present disclosure provides a clock gating cell capable of high-speed operation with improved setup rise characteristics between an enable signal and a clock signal, and an integrated circuit including the same.

A clock gating cell according to an exemplary embodiment of the present disclosure includes an inverter circuit that inverts a clock signal to generate an inverted clock signal, receives an inverted clock signal, an enable signal, and a scan enable signal, and operates a first node. A first control stage that outputs a first internal signal through a first control stage, a second control stage that receives a first internal signal, a clock signal, an enable signal, and a scan enable signal, and outputs a second internal signal through a second node. A stage and an output driver that receives the second internal signal and outputs an output clock signal, wherein the output driver can provide the third internal signal to the first control stage and the second control stage through the third node. .

An asymmetric NAND gate circuit according to an exemplary embodiment of the present disclosure includes a first P-type transistor including a gate connected to a first node and a drain connected to a second node, a gate through which a clock signal is input, and connected to a second node. a second P-type transistor including a drain, first to third N-type transistors each including a drain connected to a second node and connected in parallel to each other, a gate through which a clock signal is input, and the first N-type transistor. It may include a fourth N-type transistor including a drain connected to a source, and a fifth N-type transistor including a gate connected to a first node and a drain connected to the source of the fourth N-type transistor.

An integrated circuit according to an exemplary embodiment of the present disclosure includes a first clock gating cell that receives a clock signal and outputs a first output clock signal according to a first enable signal, and at least one that receives the first output clock signal. It includes one flip-flop, and the first clock gating cell receives an inverter circuit that inverts the clock signal to generate an inverted clock signal, an inverted clock signal, a first enable signal, and a scan enable signal, A first control stage that outputs a first internal signal, a second control stage that receives the first internal signal, a clock signal, a first enable signal, and a scan enable signal, and outputs a second internal signal, and a second It includes an output driver that receives an internal signal and outputs a first output clock signal, and the output driver can provide a third internal signal to the first control stage and the second control stage.

A clock gating cell according to an exemplary embodiment of the present disclosure includes an asymmetric NAND gate circuit, and setup rise characteristics between an enable signal and a clock signal may be improved. Additionally, the clock gating cell according to the present disclosure may enable high-speed operation by improving delay time characteristics between a clock signal and an output clock signal.

The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the technical field to which the exemplary embodiments of the present disclosure belong from the following description. It can be clearly derived and understood by those who have it. That is, unintended effects resulting from implementing the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1 and 2 are block diagrams for explaining a clock gating cell according to an exemplary embodiment of the present disclosure.
Figure 3 is a circuit diagram for explaining a clock gating cell according to an exemplary embodiment of the present disclosure.
4A and 4B are circuit diagrams for explaining characteristics of a clock gating cell according to an exemplary embodiment of the present disclosure.
Figure 5 is a timing diagram for explaining the operation of a clock gating cell.
Figure 6 is a layout diagram for explaining a clock gating cell according to an exemplary embodiment of the present disclosure.
FIG. 7 is a circuit diagram illustrating a clock gating cell according to an exemplary embodiment of the present disclosure.
8 is a block diagram illustrating an integrated circuit including a clock gating cell according to an exemplary embodiment of the present disclosure.
Figure 9 is a flowchart showing a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 10 is a block diagram showing a computing system including a memory for storing a program according to an exemplary embodiment of the present disclosure.

In this specification, a logic high level '1' may correspond to a high voltage, for example the positive supply voltage (VDD) or a voltage close to the positive supply voltage and may be referred to as a high level or active state while , the logic low level '0' may correspond to a low voltage, for example, ground potential or a voltage close to ground potential, and may be referred to as a low level or inactive state. Additionally, in this specification, a ground node may refer to a node to which a ground potential (or negative supply voltage) is applied. In the specification, the transistors may have any structure that provides complementary transistors (e.g., n-channel transistor and p-channel transistor), and non-limiting examples include Planar Field Effect Transistor (FET). ), FinFET (Fin Field Effect Transistor), GAAFET (Gate All Around Field Effect Transistor), vertical FET (Vertical Field Effect Transistor; VFET), etc.

1 and 2 are block diagrams for explaining the clock gating cell 100 according to an exemplary embodiment of the present disclosure. The clock gating cell 100 may be included in an integrated circuit manufactured by a semiconductor process, and may also be referred to as a clock gating circuit or an integrated clock gating cell.

Referring to FIG. 1, the clock gating cell 100 may generate an output clock signal (ECK) to drive a plurality of load cells. The clock gating cell 100 may receive a clock signal (CK), an enable signal (E), and a scan enable signal (SE), and may generate an output clock signal (ECK). The output clock signal (ECK) may toggle like the clock signal (CK) or be maintained at a constant voltage level depending on the enable signal (E) and the scan enable signal (SE).

For example, the clock gating cell 100 may be in an enabled state in response to an activated enable signal (E) or an activated scan enable signal (SE), and in the enabled state, in response to a clock signal (CK). It is possible to generate an output clock signal (ECK) that oscillates accordingly. Additionally, the clock gating cell 100 may be in a disabled state in response to the disabled enable signal (E) and the disabled scan enable signal (SE), and in the disabled state, at a constant level, for example, logic An output clock signal (ECK) of '1' or logic '0' can be generated. In this specification, the clock gating cell 100 in the enabled state may be referred to as supplying the output clock signal (ECK), and the clock gating cell 100 in the disabled state may be referred to as supplying the output clock signal (ECK). It may be referred to as stopping. That is, in the detailed description below, the output clock signal (ECK) can be described as being generated when the output clock signal (ECK) is generated to toggle like the clock signal (CK), and the output clock signal (ECK) is constant. It can be explained that the output clock signal (ECK) is not generated when maintaining the voltage level.

In order to prevent malfunction of the digital circuit receiving the output clock signal (ECK), the clock gating cell 100 may be synchronized with the clock signal (CK) to stop or resume the supply of the output clock signal (ECK). In an exemplary embodiment, the clock gating cell 100 may stop or resume supply of the output clock signal (ECK) in response to a rising edge of the clock signal (CK), and may stop or resume supply of the output clock signal (ECK). An output clock signal (ECK) may be supplied to a digital circuit that operates in response to a rising edge, for example, a positive edge triggered flip-flop. Additionally, in an exemplary embodiment, the clock gating cell 100 may stop or resume supply of the output clock signal (ECK) in response to a falling edge of the clock signal (CK), and may supply the output clock signal (ECK). ), an output clock signal (ECK) may be supplied to a digital circuit that operates in response to the falling edge of, for example, a negative edge triggered flip-flop.

Referring to FIG. 2 , the clock gating cell 100 may include a first control stage 110, a second control stage 120, and an output driver 130. The clock gating cell 100 may further include an inverter circuit (INV) that inverts the clock signal (CK) and generates an inverted clock signal (nck). The first control stage 110 may function as a latch and may perform the function of eliminating glitches. The second control stage 120 may function as a NAND gate circuit with an asymmetric structure and may be referred to as an asymmetric NAND gate circuit.

The first control stage 110 provides information to the first node N1 based on the inverted clock signal (nck), scan enable signal (SE), enable signal (E), and third internal signal (IS3). The first internal signal IS1 can be generated. The first control stage 110 may include a feedback path for feeding back the first internal signal IS1.

When at least one of the scan enable signal (SE), the enable signal (E), and the third internal signal (IS3) is activated, the second control stage 120 generates the first internal signal (IS1) and the clock signal (CK). NAND operations can be performed on . The second control stage 120 may generate a second internal signal IS2 provided to the second node N2 as a result of performing the NAND operation.

The output driver 130 may generate an output clock signal (ECK) based on the second internal signal (IS2) and generate a third internal signal (IS3) provided to the third node (N3). For example, the output driver 130 may include a plurality of inverter circuits, and may invert the second internal signal IS2 and output it as the output clock signal ECK.

Figure 3 is a circuit diagram for explaining a clock gating cell according to an exemplary embodiment of the present disclosure. In Figure 3 and the following circuit diagram, the horizontal line (-) connected to one end of the transistor may represent a power supply voltage (e.g., VDD voltage), and the inverted triangle (▽) connected to one end of the transistor may represent a ground voltage (e.g. For example, it can represent GND or VSS voltage).

2 and 3, the first control stage 110 of the clock gating cell 100 includes first to fifth P-type transistors (P11 to P15), a first N-type transistor (N11), and a second N type transistor N12, and a first inverter circuit INV1.

The source voltage (VDD) of the first P-type transistor (P11) may be applied, and the drain of the first P-type transistor (P11) may be connected to the source of the second P-type transistor (P12). A scan enable signal (SE) may be received at the gate of the first P-type transistor (P11).

The drain of the second P-type transistor (P12) may be connected to the source of the third P-type transistor (P13). An enable signal (E) may be received at the gate of the second P-type transistor (P12).

The drain of the third P-type transistor (P13) may be connected to the drain of the fourth P-type transistor (P14). The gate of the third P-type transistor P13 may be connected to the third node N3 and the third internal signal IS3 may be received.

The power supply voltage (VDD) may be applied to the source of the fourth P-type transistor (P14). The gate of the fourth P-type transistor P14 may be connected to the first node N1 and the first internal signal IS1 may be received as feedback.

The source of the fifth P-type transistor (P15) may be connected to the drain of the third P-type transistor (P13) and the drain of the fourth P-type transistor (P14), and the drain of the fifth P-type transistor (P15) may be connected to an internal node. It can be connected to (N0). An inverted clock signal (nck) may be received at the gate of the fifth P-type transistor (P15).

A ground voltage may be applied to the source of the first N-type transistor N11 and the source of the second N-type transistor N12, and the drain of the first N-type transistor N11 and the source of the second N-type transistor N12 may be applied. The drain may be connected to an internal node (N0). An inverted clock signal (nck) may be received at the gate of the first N-type transistor (N11), and the gate of the second N-type transistor (N12) may be connected to the third node (N3) and a third internal signal (IS3) can be received.

The first inverter circuit INV1 may generate a first internal signal IS1 through the first node N1 by inverting a signal according to the voltage of the internal node N0. That is, the input terminal of the first inverter circuit INV1 may be connected to the internal node NO, and the output terminal of the first inverter circuit INV1 may be connected to the first node N1. In the first control stage 110, the first inverter circuit INV1 may provide a feedback path.

The second control stage 120 of the clock gating cell 100 may include a first P-type transistor (P21), a second P-type transistor (P22), and first to fifth N-type transistors (P21 to P25). You can. The second control stage 120 may be a NAND gate circuit with an asymmetric structure. In this case, the asymmetric structure means that the number of P-type transistors and the number of N-type transistors included in the NAND gate circuit do not match each other. You can.

A source voltage (VDD) may be applied to the source of the first P-type transistor (P21), and the drain of the first P-type transistor (P21) may be connected to the second node (N2). The gate of the first P-type transistor P21 may be connected to the first node N1 and the first internal signal IS1 may be received.

A source voltage (VDD) may be applied to the source of the second P-type transistor (P22), and the drain of the second P-type transistor (P22) may be connected to the second node (N2). A clock signal CK may be received at the gate of the second P-type transistor P22.

The first to third N-type transistors (N21 to N23) may be connected in parallel to each other. The source of each of the first to third N-type transistors (N21 to N23) may be connected to the drain of the fourth N-type transistor (N24), and the drain of each of the first to third N-type transistors (N21 to N23) may be connected to the drain of the fourth N-type transistor (N24). 2 Can be connected to node (N2). An enable signal E may be received at the gate of the first N-type transistor N21, and a scan enable signal SE may be received at the gate of the second N-type transistor N22. 3 The gate of the N-type transistor N23 may be connected to the third node N3 and the third internal signal IS3 may be received.

The source of the fourth N-type transistor N24 may be connected to the drain of the fifth N-type transistor N25. A clock signal CK may be received at the gate of the fourth N-type transistor N24.

A ground voltage may be applied to the source of the fifth N-type transistor N25. The gate of the fifth N-type transistor N25 may be connected to the first node N1 and the first internal signal IS1 may be received.

The output driver 130 of the clock gating cell 100 may include a second inverter circuit (INV2) and a third inverter circuit (INV3). The second inverter circuit INV2 may invert the second internal signal IS2 and output it as the output clock signal ECK. The third inverter circuit INV3 may invert the second internal signal IS2 and output it as the third internal signal IS3 through the third node N3. The third internal signal IS3 may be provided to each of the first control stage 110 and the second control stage 120.

In the second control stage 120 of the clock gating cell 100 of FIG. 3, the first N-type transistor N21 to which the enable signal E is input and the fourth N-type transistor to which the clock signal CK is input. (N24) may be connected close to each other, that is, the distance between the first N-type transistor (N21) and the fourth N-type transistor (N24) may be reduced and placed close together. Accordingly, the clock gating cell 100 may have improved setup characteristics between the enable signal (E) and the clock signal (CK), enabling high-speed operation.

FIGS. 4A and 4B are circuit diagrams for explaining characteristics of the clock gating cell 100 according to an exemplary embodiment of the present disclosure. Figure 5 is a timing diagram for explaining the operation of the clock gating cell 100.

Referring to FIG. 4A, it can be assumed that the enable signal E changes from a deactivated state to an activated state. When the clock signal is at a logic low level (e.g., 0), the inverted clock signal (nck) may be at a logic high level (e.g., 1), and the internal node (N0) and the first node (N1) may be precharged to a logic low level (0) and a logic high level (1), respectively.

When the clock signal (CK) rises from the logic low level (0) to the logic high level (1), and the enable signal is activated, the second node (N2) increases from the logic high level (1) to the logic low level (0). ), and the third node (N3) rises from the logic low level (0) to the logic high level (1), so the internal node (N0) and the first node (N1) are at the logic low level (0) and The logic high level (1) can be maintained.

In the clock gating cell 100 according to the present disclosure, the first N-type transistor N21 and the fourth N-type transistor N24 of the second control stage 120 are closely connected to each other, so that the enable signal E and the clock The stage of the setup path between the signals CK is simplified, and thus the setup characteristics (e.g., setup rise characteristics) between the enable signal E and the clock signal CK are improved, enabling high-speed operation. there is.

Referring to FIGS. 4A and 5, when the enable signal (E) and the scan enable signal (SE) are deactivated, that is, both are logic low level, the output clock is maintained even if the clock signal (CK) changes to logic high level. The signal (ECK) may not be generated. When at least one of the enable signal (E) and the scan enable signal (SE) is activated, for example, when the enable signal (E) transitions from a logic low level to a logic high level, the clock signal (CK) ) can be generated at the rising edge of the output clock signal (ECK).

At this time, the setup characteristics between the enable signal (E) and the clock signal (CK) are such that when the enable signal (E) is activated and the output clock signal (ECK) is output, the enable signal (E) is activated. It may be related to the time difference between the time when the rising edge of the clock signal (CK) corresponding to the output clock signal (ECK) is generated. In the clock gating cell of the comparative example with deteriorated rising characteristics, when the time when the enable signal (E) is activated is close to the time when the rising edge of the clock signal (CK) is generated, the output clock signal (ECK) is not generated, The output clock signal (ECK) may be generated on the next rising edge of the clock signal (CK). Accordingly, as the rising characteristic is improved, the time during which the output clock signal (ECK) is output from the time the enable signal (E) is activated can be reduced, and the clock gating cell 100 according to the present disclosure can be capable of high-speed operation. there is.

Referring to FIG. 4B, the second control stage 120 may perform NAND operation on the first internal signal IS1 and the clock signal CK. At this time, since the first N-type transistor (N21) and the second N-type transistor (N22) are connected to each other, when performing a scan test operation or general operation according to the scan enable signal (SE), the enable The timing of the signal (E) and the scan enable signal (SE) can be matched.

The second control stage 120 includes a first N-type transistor (N21), a second N-type transistor (N22), a fourth N-type transistor (N24), and a fifth N-type transistor (N25) from the second node (N2). can in turn have a 3-stack structure. In order to reduce the delay between the rising edge of the clock signal (CK) and the point at which the output clock signal (ECK) is generated, a first N-type transistor (N21), a second N-type transistor (N22), and a fourth N-type transistor ( N24) and the fifth N-type transistor (N25) can be configured as a plurality by increasing the number of fingers of each, and the first N-type transistor (N21), the second N-type transistor (N22), and the fourth N The number of fingers of each of the fifth N-type transistor N24 and N25 may be the same. For example, the clock gating cell 100 of FIG. 6 includes a first N-type transistor (N21), a second N-type transistor (N22), a fourth N-type transistor (N24), and a fifth N-type transistor (N25), respectively. The number of fingers may be 2. As an example of the clock gating cell 100, the layout of the clock gating cell 100 will be described later with reference to FIG. 6.

FIG. 6 is a layout diagram for explaining the clock gating cell 100 according to an exemplary embodiment of the present disclosure.

FIG. 6 is a plan view showing the clock gating cell 100 constituting one chip or one functional block on a plane consisting of the X and Y axes. The clock gating cell 100 of FIG. 6 may be implemented by the clock gating cell 100 of FIG. 3 .

In this specification, the Y-axis direction and the X-axis direction may be referred to as the first horizontal direction and the second horizontal direction, respectively, and the Z-axis direction may be referred to as the vertical direction. A plane consisting of the A component placed in the opposite direction may be referred to as being below another component.

An integrated circuit may include a plurality of standard cells. A standard cell is a unit of layout included in an integrated circuit, may be designed to perform a predefined function, and may also be referred to as a cell. An integrated circuit may include a number of various standard cells, and the standard cells may be arranged in alignment along a plurality of rows and a cell height may be defined in the Y-axis direction. .

A plurality of standard cells, including clock gating cell 100 of FIG. 6, can be used repeatedly in integrated circuit designs. Standard cells can be pre-designed according to manufacturing technology and stored in a standard cell library, and an integrated circuit can be designed by arranging and interconnecting standard cells stored in this standard cell library according to design rules.

Referring to FIG. 6 , the clock gating cell 100 may receive a supply voltage through the first power line PL1 and the second power line PL2. The first power line PL1 and the second power line PL2 may be disposed at the boundaries of each of the plurality of rows of the integrated circuit, and the first power line PL1 may apply the first supply voltage VDD to each standard cell. ) can be provided, and the second power line PL2 can provide a second supply voltage (VSS) to each standard cell. Each of the first supply voltage (VDD) and the second supply voltage (VSS) may be a power voltage or a ground voltage.

The first power line PL1 and the second power line PL2 may be formed as a conductive pattern extending in the X-axis direction and may be arranged alternately in the Y-axis direction. Although FIG. 6 shows that each of the first power line PL1 and the second power line PL2 is formed as a pattern of the first metal layer M1, the integrated circuit according to the present disclosure is not limited to this, and the first power line PL1 and PL2 are formed as patterns of the first metal layer M1. Each of the power line PL1 and the second power line PL2 may be formed as a pattern of an upper metal layer of the first metal layer M1, or may be formed inside a separation trench formed in the substrate.

The clock gating cell 100 may be defined by a cell boundary. The cell height of the clock gating cell 100 may be defined in the Y-axis direction based on the cell boundary.

A first power line PL1 and a diffusion break may be formed at the cell boundary of the clock gating cell 100. The diffusion break may electrically separate the active areas of the clock gating cell 100 and other standard cells from each other. Additionally, the clock gating cell 100 may include a diffusion break therein, and the first active region (RX1) and the second active region (RX2) may be divided by the diffusion break. . In FIG. 6, a single diffusion break is shown, but unlike this, a double diffusion break may be formed at the cell boundary. The diffusion break may include a silicon-containing insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbonitride film, or a combination thereof. For example, diffusion brakes include fluoride silicate glass (FSG), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), flowable oxide (FOX), and plasma (PE-TEOS). It may include enhanced tetra-ethyl-ortho-silicate), or TOSZ (tonen silazene).

The clock gating cell 100 may include a plurality of gate lines extending in the Y-axis direction and spaced apart from each other in the X-axis direction, and a first active region (RX1) and a second active region extending in the X-axis direction. (RX2) may be included. The active pattern formed in each of the first active region (RX1) and the second active region (RX2) may intersect with a gate line extending in the Y-axis direction to form a transistor. A P-type transistor may be formed in the first active area (RX1), and an N-type transistor may be formed in the second active area (RX2).

At least one fin extending in the X-axis direction, or a nanowire or nanosheet may be formed on the first active region RX1 and the second active region RX2. Accordingly, the gate line and active region may form a Fin Field Effect Transistor (FinFET), a Gate All Around Field Effect Transistor (GAAFET), or a Multi Bridge Channel (MBC) FET. . However, it will be understood that the description of the present specification can also be applied to clock gating cells including transistors of a different structure from FinFET.

In an exemplary embodiment, the first active region (RX1) and the second active region (RX2) are a semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. It may include a conductive region, for example, a well doped with impurities, or a structure doped with impurities. In an example embodiment, the gate line may include a work function metal containing layer and a gap fill metal film. For example, the work function metal-containing layer may include at least one metal of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, and gap fill. The metal film may be made of a W film or an Al film. In an exemplary embodiment, the gate lines may include a stacked structure of TiAlC/TiN/W, a stacked structure of TiN/TaN/TiAlC/TiN/W, or a stacked structure of TiN/TaN/TiN/TiAlC/TiN/W. there is.

A plurality of metal layers sequentially stacked in a vertical direction may be formed in the clock gating cell 100. For example, the second metal layer (M2) may be formed on the first metal layer (M1) disposed closest to the substrate. In an example embodiment, the first metal layer M1 may include patterns extending in the X-axis direction, and the second metal layer M2 may include patterns extending in the Y-axis direction. Unlike shown in FIG. 6, another metal layer may be further formed on the second metal layer (M2), and the direction of the pattern of the first metal layer (M1) and the direction of the pattern of the second metal layer (M2) are It can be transformed.

The patterns formed on each of the metal layers M1 and M2 may be made of metal, conductive metal nitride, metal silicide, or a combination thereof. In the drawings of this specification, only some layers may be shown for convenience of illustration, and the vias (V0, V1) are used to indicate the connection between the pattern and sub-pattern of the metal layers (M1, M2). , M2) can be displayed even though it is located below the pattern.

The clock gating cell 100 may include a plurality of first vias (V0) electrically connected between the pattern of the first metal layer (M1) and the lower pattern, and the pattern of the first metal layer (M1) and the lower pattern. It may include a plurality of second vias (V1) electrically connected between the patterns of the two metal layers (M2). For example, a plurality of first vias (V0) may connect the first metal layer (M1) and a gate line, or, for example, a plurality of first vias (V0) may connect the first metal layer (M1) and a contact on the first active area (RX1) or the second active area (RX2) may be connected. However, unlike shown in FIG. 6, the first metal layer M1 and the contact on the first active area RX1 or the second active area RX2 may be formed to be in direct contact, and the first metal layer M1 ) and the gate contact on the gate line may be in contact with each other.

The patterns of the first metal layer (M1) may be separated from each other by the M1 cut. When the pattern of the first metal layer M1 is separated by the M1 cut, the tip of the pattern may be formed to be concave. Although only the M1 cut is shown in FIG. 6, the clock gating cell 100 may further include a gate line cut to separate gate lines, a contact cut to separate contacts, etc.

The clock gating cell 100 may include a first input pin (IP1), a second input pin (IP2), and a third input pin (IP3). The clock gating cell 100 may receive a clock signal (CK) through a first input pin (IP1), an enable signal (E) through a second input pin (IP2), and a third The scan enable signal (SE) can be received through the input pin (IP3). In an exemplary embodiment, the first input pin (IP1) and the second input pin (IP2) may be formed as a pattern of the first metal layer (M1), and the third input pin (IP3) may be formed as a pattern of the second metal layer (M1). It can be formed as a pattern of M2).

The clock gating cell 100 may include an output pin (OP) that outputs an output clock signal (ECK). In an exemplary embodiment, the output pin OP may be formed as a pattern of the second metal layer M2.

In an exemplary embodiment, the first node N1 and the third node N3 of the clock gating cell 100 may be formed as a pattern of the first metal layer M1, and the second node N2 may be formed as a pattern of the first metal layer M1. It may be formed as a pattern of two metal layers (M2), and the internal node (N0) may be formed as a pattern of the first metal layer (M1).

The clock gating cell 100 may be a multiple height cell sequentially arranged in adjacent rows. For example, the clock gating cell 100 may be placed in the first row and the second row. In an exemplary embodiment, an inverter circuit (INV in FIG. 3) and a third inverter circuit (INV3 in FIG. 3) may be disposed in the first row of the clock gating cell 100, and the first row of the clock gating cell 100 In the second row, the first control stage (110 in FIG. 3) and the first inverter circuit (INV1 in FIG. 3) may be disposed. Additionally, in an exemplary embodiment, the second control stage (120 in FIG. 3) and the second inverter circuit (INV2) may be disposed across the first and second rows of the clock gating cell 100. In an exemplary embodiment, first to third inverter circuits (INV1 to INV3) are located on the right side of the diffusion brake disposed on the rightmost side among the diffusion brakes disposed inside the clock gating cell 100 and not on the cell boundary. can be placed.

In an exemplary embodiment, each of the first N-type transistor (N21), the second N-type transistor (N22), the fourth N-type transistor (N24), and the fifth N-type transistor (N25) of the clock gating cell 100 The number of fingers, that is, the number of gate lines included in each, may be 2. In an exemplary embodiment, the second inverter circuit (INV2) may be a 4-driver inverter circuit, that is, each of the P-type transistor and the N-type transistor constituting the second inverter circuit (INV2) includes four gate lines. can do.

FIG. 7 is a circuit diagram illustrating a clock gating cell according to an exemplary embodiment of the present disclosure. In the description of FIG. 7, overlapping descriptions of the same symbols as those in FIG. 3 will be omitted. The second control stage 120A of FIG. 7 may be the second control stage 120 of FIG. 2 .

2 and 7, the second control stage 120A of the clock gating cell 100 includes a first P-type transistor (P21'), a second P-type transistor (P22'), and first to fifth It may include N-type transistors (P21'~P25').

The source of the first P-type transistor (P21') may be applied with the power supply voltage (VDD), and the drain of the first P-type transistor (P21') may be connected to the second node (N2). The gate of the first P-type transistor P21' may receive a clock signal CK.

The source of the second P-type transistor P22' may be connected to the second node N2, and the drain of the second P-type transistor P22' may be connected to the fourth node N4. An inverted clock signal (nck) may be received at the gate of the second P-type transistor (P22'). The fourth node (N4) may be connected to the drain of the third P-type transistor (P13), the drain of the fourth P-type transistor (P14), and the source of the fifth P-type transistor (P15) of the first control stage 110. there is.

The source of the fifth N-type transistor N25' may be connected to the fourth node N4, and the drain of the fifth N-type transistor N25' may be connected to the second node N2. A clock signal CK may be received at the gate of the fifth N-type transistor N25'. The second P-type transistor (P22') and the fifth N-type transistor (N25') may operate as a transmission gate circuit that switches according to the clock signal (CK) and the inverted clock signal (nck).

The first to third N-type transistors (N21' to N23') may be connected in parallel to each other. The source of each of the first to third N-type transistors (N21' to N23') may be connected to the drain of the fourth N-type transistor (N24'), and the first to third N-type transistors (N21' to N23') may be connected to the drain of the fourth N-type transistor (N24'). Each drain may be connected to the fourth node N4. An enable signal (E) may be received at the gate of the first N-type transistor (N21'), and a scan enable signal (SE) may be received at the gate of the second N-type transistor (N22'). , the gate of the third N-type transistor N23' may be connected to the third node N3 and the third internal signal IS3 may be received.

A ground voltage may be applied to the source of the fourth N-type transistor N24'. The gate of the fourth N-type transistor N24' may be connected to the first node N1 and the first internal signal IS1 may be received.

In the second control stage 120A of the clock gating cell 100A of FIG. 7, the second node N2 is connected from the second P-type transistor P22' and the fifth N-type transistor N25' constituting the transmission gate circuit. ) is the distance (signal transmission distance) from the first N-type transistor (N21') through which the enable signal (E) is input from the second node (N2) to the second node (N2) (signal transmission distance) ) may be closer than Accordingly, the clock gating cell 100A may have a reduced delay time between the clock signal CK and the output clock signal ECK and may be capable of high-speed operation.

FIG. 8 is a block diagram illustrating an integrated circuit 10 including clock gating cells 100 and 100A according to an exemplary embodiment of the present disclosure. In some embodiments, the clock gating cell described above with reference to the figures may be included in an integrated circuit that processes digital signals. As shown in FIG. 8, the integrated circuit 10 includes first and second clock gating cells (CGC1, CGC2), a power controller (PC), first and second combination logic blocks (CL1, CL2), and a plurality of It may include flip-flops (PF1, PF2, NF1, NF2).

The power controller (PC) can control the power of the integrated circuit 10 and generate first and second enable signals E1 and E2. For example, the power controller (PC) includes at least one first positive edge triggered flip-flop (PF1), a first combination logic block (CL1), and at least one second positive edge triggered flip-flop (PF2). In order to reduce power consumption by the included digital circuit, a deactivated first enable signal E1 may be generated. In addition, the power controller (PC) includes at least one third positive edge triggered flip-flop (NF1), a second combination logic block (CL2), and at least one fourth positive edge triggered flip-flop (NF2). In order to reduce power consumption by the digital circuit, a deactivated second enable signal E2 may be generated.

The first clock gating cell (CGC1) can receive the clock signal (C_IN) and stop or resume supply of the first output clock signal (C_OUT1) based on the first enable signal (E1). For example, the first clock gating cell CGC1 may generate a first output clock signal C_OUT1 that is maintained at logic '0' in an inactive state. Accordingly, the first output clock signal (C_OUT1) is a positive edge triggered flip-flop, for example, at least one first positive edge triggered flip-flop (PF1) and at least one second positive edge triggered flip-flop ( It can be supplied to PF2).

Additionally, the second clock gating cell (CGC2) can receive the clock signal (C_IN) and stop or resume supply of the second output clock signal (C_OUT2) based on the second enable signal (E2). . For example, the second clock gating cell CGC2 may generate a second output clock signal C_OUT2 that is maintained at logic '0' in an inactive state. Accordingly, the second output clock signal (C_OUT2) is a positive edge triggered flip-flop, for example, at least one third positive edge triggered flip-flop (NF1) and at least one fourth positive edge triggered flip-flop ( Can be supplied to NF2).

Alternatively, in an example embodiment, the at least one third positive edge triggered flip-flop (NF1) and the at least one fourth positive edge triggered flip-flop (NF2) are negative edge triggered flip-flops rather than positive edge triggered flip-flops. It could be a flip-flop. For example, the second clock gating cell (CGC2) may generate a second output clock signal (C_OUT2) that is maintained at logic '1' in an inactive state. Accordingly, the second output clock signal (C_OUT2) may be supplied to the negative edge triggered flip-flop.

Each of the first clock gating cell (CGC1) and the second clock gating cell (CGC2) in FIG. 8 may be the clock gating cell (100, 100A) described in FIGS. 3 and 7. The first output clock signal (C_OUT1) output from the first clock gating cell (CGC1) and the second clock gating cell (CGC2) activated by the first enable signal (E1) and the second enable signal (E2), respectively. and the second output clock signal (C_OUT2) may have different characteristics.

A clock signal (C_IN), which is a global clock signal, may be transmitted through a buffer tree to each of the first clock gating cell (CGC1) and the second clock gating cell (CGC2), and the first clock gating cell (CGC1) and the second clock gating cell (CGC2) may be transmitted through the buffer tree. The first output clock signal (C_OUT1) or the second output clock signal (C_OUT2) may be transmitted from each of the gating cells (CGC2) to the positive edge triggered flip-flops (PF1, PF2, NF1, and NF2) through a buffer tree. .

FIG. 9 is a flow chart illustrating a method for manufacturing an integrated circuit 10 according to an exemplary embodiment of the present disclosure. Specifically, the flow chart of FIG. 10 illustrates a method for manufacturing an integrated circuit (IC) (e.g., 10 in FIG. 8) including the clock gating cell described above.

The standard cell library (or cell library) D10 may include information about standard cells, such as function information, characteristic information, layout information, etc., and may include information about clock gating cells. As described above with reference to the drawings, the clock gating cell defined by the standard cell library (D10) may be capable of high-speed operation, and may be the clock gating cell (100, 100A) described in FIGS. 2, 3, and 7. You can.

In step S10, a logical synthesis operation may be performed to generate a netlist from RTL data. For example, semiconductor design tools (e.g., logic synthesis tools) synthesize logic by referencing the standard cell library (D10) from RTL data written in Hardware Description Language (HDL), such as VHSIC Hardware Description Language (VHDL) and Verilog. By performing , a netlist including a bitstream or netlist can be created. The standard cell library D10 may include information about the performance of the clock gating cells 100 and 100A, and standard cells may be included in an integrated circuit (IC) by referring to such information during the logic synthesis process.

In step S20, a Place & Routing (P&R) operation that generates layout data D20 from the netlist may be performed. In the placement and routing step (S20), an operation of arranging standard cells, creating interconnections, and generating layout data (D20) may be performed.

For example, a semiconductor design tool (eg, P&R tool) may place a plurality of standard cells by referring to the standard cell library D10 from the netlist. For example, a semiconductor design tool can refer to the standard cell library D10 and place the layout of the clock gating cells 100 and 100A defined by the netlist.

In the act of creating interconnections, the interconnection electrically connects an output pin and an input pin of a standard cell and may include, for example, at least one via and at least one conductive pattern. there is. The layout data D20 may have a format such as GDSII, for example, and may include geometric information of standard cells and interconnections.

In step S30, Optical Proximity Correction (OPC) may be performed. OPC can refer to the process of forming a pattern of a desired shape by correcting distortion phenomena such as refraction caused by the characteristics of light in photolithography, which is included in the semiconductor process for manufacturing integrated circuits (ICs). , the pattern on the mask can be determined by applying OPC to the layout data 20. In an exemplary embodiment, the layout of the integrated circuit (IC) may be limitedly modified in step S30, and the limited modification of the integrated circuit (IC) in step S30 may be performed after optimizing the structure of the integrated circuit (IC). As a treatment, it may be referred to as design polishing.

In step S40, an operation of manufacturing a mask may be performed. For example, by applying OPC to the layout data D20, patterns on a mask may be defined to form patterns formed on a plurality of layers, and at least one mask (or , photomask) can be produced.

In step S50, an operation of fabricating an integrated circuit (IC) may be performed. For example, an integrated circuit (IC) may be manufactured by patterning a plurality of layers using at least one mask fabricated in step S40. As shown in FIG. 11, step S50 may include steps S51 and S52. In step S51, a front-end-of-line (FEOL) process may be performed. FEOL may refer to the process of forming individual elements, such as transistors, capacitors, resistors, etc., on a substrate during the manufacturing process of an integrated circuit (IC). For example, FEOL involves planarizing and cleaning the wafer, forming trenches, forming wells, forming gate lines, and forming sources and drains. It may include steps such as: In step S52, a back-end-of-line (BEOL) process may be performed. BEOL may refer to the process of interconnecting individual elements, such as transistors, capacitors, resistors, etc., during the manufacturing process of an integrated circuit (IC). For example, BEOL includes the steps of siliciding the gate, source, and drain regions, adding a dielectric, planarizing, forming holes, adding a metal layer, forming vias, and passivation ( It may include forming a passivation layer, etc. The integrated circuit (IC) can then be packaged in a semiconductor package and used as a component in a variety of applications. As described above, due to the good characteristics of the clock gating cell, the integrated circuit (IC) can have high performance and efficiency, and as a result, the performance and efficiency of applications including the integrated circuit (IC) can be improved.

FIG. 10 is a block diagram illustrating a computing system 1000 including a memory for storing a program according to an exemplary embodiment of the present disclosure. At least some of the steps included in the method for manufacturing an integrated circuit (e.g., the method of FIG. 9) according to an example embodiment of the present disclosure may be performed in the computing system 1000. The computing system 1000 may be a fixed computing system such as a desktop computer, workstation, server, etc., or it may be a portable computing system such as a laptop computer.

Referring to FIG. 10, the computing system 1000 includes a processor 1100, input/output devices 1200, a network interface 1300, random access memory (RAM) 1400, read only memory (ROM) 1500, and It may include a storage device 1600. The processor 1100, input/output devices 1200, network interface 1300, RAM 1400, ROM 1500, and storage device 1600 may be connected to the bus 1700 and communicate with each other through the bus 1700. Can communicate.

The processor 1100 may be referred to as a processing unit, for example, a microprocessor, an application processor (AP), a digital signal processor (DSP), or a graphic processing unit (GPU). Contain at least one core capable of running (e.g. Intel Architecture-32 (IA-32), 64-bit extensions IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.) You can. For example, the processor 1100 can access memory, that is, RAM 1400 or ROM 1500, through the bus 1700 and execute instructions stored in RAM 1400 or ROM 1500. .

The RAM 1400 may store a program 1420 or at least a portion thereof for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure, and the program 1420 may enable the processor 1100 to manufacture an integrated circuit. At least some of the steps included in the method (for example, the method of FIG. 9) may be performed. That is, the program 1420 may include a plurality of instructions executable by the processor 1100, and the plurality of instructions included in the program 1420 allow the processor 1100 to execute, for example, see FIG. 9. Thus, at least some of the steps included in the above-described flow chart can be performed.

The storage device 1600 may not lose stored data even if power supplied to the computing system 1000 is cut off. For example, the storage device 1600 may include a non-volatile memory device or a storage medium such as magnetic tape, optical disk, or magnetic disk. Additionally, the storage device 1600 may be removable from the computing system 1000. The storage device 1600 may store the program 1420 according to an exemplary embodiment of the present disclosure, and the program 1420 or At least part of it may be loaded into RAM 1400. Alternatively, the storage device 1600 may store a file written in a program language, and the program 1420 or at least a portion thereof generated from the file by a compiler or the like may be loaded into the RAM 1400. Additionally, as shown in FIG. 10, the storage device 1600 may store a database 1620, and the database 1620 may store information necessary for designing an integrated circuit, for example, the standard cell library (D10) of FIG. 9. ) may include.

The storage device 1600 may store data to be processed by the processor 1100 or data processed by the processor 1100. That is, the processor 1100 may generate data by processing data stored in the storage device 1600 according to the program 1420, and may store the generated data in the storage device 1600. For example, the storage device 1600 may store RTL data, netlist, and/or layout data D20 described in FIG. 9 .

Input/output devices 1200 may include input devices such as keyboards and pointing devices, and may include output devices such as display devices and printers. For example, the user may trigger execution of the program 1420 by the processor 1100 through the input/output devices 1200, or may input RTL data and/or netlist described in FIG. 9. , you can also check the layout data (D20) of FIG. 9.

Network interface 1300 may provide access to a network external to computing system 1000. For example, a network may include multiple computing systems and communication links, which may include wired links, optical links, wireless links, or any other type of links.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached patent claims.

Claims (20)

an inverter circuit that inverts the clock signal to generate an inverted clock signal;
a first control stage that receives the inverted clock signal, enable signal, and scan enable signal, and outputs a first internal signal through a first node;
a second control stage that receives the first internal signal, the clock signal, the enable signal, and the scan enable signal, and outputs a second internal signal through a second node; and
An output driver that receives the second internal signal and outputs an output clock signal,
The output driver is a clock gating cell, characterized in that it provides a third internal signal to the first control stage and the second control stage through a third node. According to claim 1,
The first control stage is,
A first P-type transistor including a gate through which the scan enable signal is input;
a second P-type transistor including a gate to which the enable signal is input and a source connected to the drain of the first P-type transistor;
a third P-type transistor including a gate connected to the third node and a source connected to the drain of the second P-type transistor;
a fourth P-type transistor including a source to which a power supply voltage is applied and a drain connected to the drain of the third P-type transistor;
A fifth P-type transistor including a gate to which the inverted clock signal is input, a source connected to the drain of the third P-type transistor, and a drain connected to an internal node;
a first N-type transistor including a gate into which the inverted clock signal is input and a drain connected to the internal node;
a second N-type transistor including a gate connected to the third node and a drain connected to the internal node; and
A clock gating cell comprising a first inverter circuit including an input terminal connected to the internal node. According to clause 2,
The gate of the fourth P-type transistor and the output terminal of the first inverter circuit are connected to the first node,
A clock gating cell, wherein the first inverter circuit provides a feedback path for the first control stage. According to claim 1,
The second control stage is,
a first P-type transistor including a gate connected to the first node and a drain connected to the second node;
a second P-type transistor including a gate through which the clock signal is input and a drain connected to the second node;
first to third N-type transistors each including a drain connected to the second node and connected in parallel to each other;
a fourth N-type transistor including a gate through which the clock signal is input and a drain connected to the source of the first N-type transistor; and
A clock gating cell including a fifth N-type transistor including a gate connected to the first node and a drain connected to the source of the fourth N-type transistor. According to clause 4,
The first N-type transistor of the second control stage includes a gate through which the enable signal is input.
The second N-type transistor of the second control stage includes a gate through which the scan enable signal is input,
A clock gating cell, wherein the third N-type transistor of the second control stage includes a gate connected to the third node. According to claim 1,
The output driver is,
a second inverter circuit whose input terminal is connected to the second node and outputs the output clock signal; and
A clock gating cell comprising a third inverter circuit having an input terminal connected to the second node and an output terminal connected to the third node. According to claim 1,
The second control stage is,
a first P-type transistor including a gate through which the clock signal is input and a drain connected to the second node;
a transmission gate circuit connected between the second node and the fourth node and switched by the clock signal and the inverted clock signal;
first to third N-type transistors each including a drain connected to the fourth node and connected in parallel to each other; and
A clock gating cell including a fourth N-type transistor including a gate connected to the first node and a drain connected to the source of the first N-type transistor. According to clause 7,
The transmission gate circuit is,
a second P-type transistor including a gate through which the inverted clock signal is input, a source connected to the second node, and a drain connected to the fourth node; and
A clock gating cell comprising a second P-type transistor including a gate through which the clock signal is input, a drain connected to the second node, and a source connected to the fourth node. According to clause 7,
The first N-type transistor includes a gate through which the enable signal is input.
The second N-type transistor includes a gate through which the scan enable signal is input,
A clock gating cell wherein the third N-type transistor includes a gate connected to the third node. According to clause 7,
A clock gating cell, characterized in that the fourth node is shared by the first control stage and the second control stage. A first P-type transistor including a gate connected to a first node and a drain connected to a second node;
a second P-type transistor including a gate through which a clock signal is input and a drain connected to the second node;
first to third N-type transistors each including a drain connected to the second node and connected in parallel to each other;
a fourth N-type transistor including a gate through which the clock signal is input and a drain connected to the source of the first N-type transistor; and
An asymmetric NAND gate circuit including a fifth N-type transistor including a gate connected to the first node and a drain connected to the source of the fourth N-type transistor. According to claim 11,
The first N-type transistor includes a gate through which an enable signal is input.
The second N-type transistor includes a gate through which a scan enable signal is input,
An asymmetric NAND gate circuit, wherein the third N-type transistor includes a gate connected to a third node. a first clock gating cell that receives a clock signal and outputs a first output clock signal according to a first enable signal; and
At least one flip-flop receiving the first output clock signal,
The first clock gating cell is,
an inverter circuit that inverts the clock signal to generate an inverted clock signal;
a first control stage that receives the inverted clock signal, the first enable signal, and the scan enable signal and outputs a first internal signal;
a second control stage that receives the first internal signal, the clock signal, the first enable signal, and the scan enable signal and outputs a second internal signal; and
An output driver that receives the second internal signal and outputs the first output clock signal,
and the output driver provides a third internal signal to the first control stage and the second control stage. According to claim 13,
a second clock gating cell that receives the clock signal and outputs a second output clock signal according to a second enable signal; and
The integrated circuit further comprising at least one flip-flop receiving the second output clock signal. According to claim 14,
The second clock gating cell includes an inverter circuit, a first control stage, a second control stage, and an output driver,
The second control stage is an integrated circuit, characterized in that the NAND gate circuit of an asymmetric structure. According to claim 13,
The first control stage is,
A first P-type transistor including a gate through which the scan enable signal is input;
a second P-type transistor including a gate into which the first enable signal is input and a source connected to the drain of the first P-type transistor;
a third P-type transistor including a gate into which the third internal signal is input and a source connected to the drain of the second P-type transistor;
a fourth P-type transistor including a source to which a power supply voltage is applied and a drain connected to the drain of the third P-type transistor;
A fifth P-type transistor including a gate to which the inverted clock signal is input, a source connected to the drain of the third P-type transistor, and a drain connected to an internal node;
a first N-type transistor including a gate into which the inverted clock signal is input and a drain connected to the internal node;
a second N-type transistor including a gate through which the third internal signal is input and a drain connected to the internal node; and
An integrated circuit comprising a first inverter circuit including an input terminal connected to the internal node. According to claim 16,
The gate of the fourth P-type transistor is connected to the output terminal of the first inverter circuit, and the first internal signal is output through the output terminal of the first inverter circuit. According to claim 13,
The second control stage is,
A first P-type transistor including a gate to which the first internal signal is input and a source to which a power voltage is applied;
a second P-type transistor including a gate to which the clock signal is input and a source to which a power voltage is applied;
First to third N-type transistors each including a drain connected to the drain of the first P-type transistor and the drain of the second P-type transistor, and connected in parallel to each other;
a fourth N-type transistor including a gate through which the clock signal is input and a drain connected to the source of the first N-type transistor; and
An integrated circuit including a fifth N-type transistor including a gate through which the first internal signal is input and a drain connected to the source of the fourth N-type transistor.
The third N-type transistor of the second control stage includes a gate through which the third internal signal is input. According to claim 13,
The output driver is,
a second inverter circuit that receives the second internal signal and outputs the first output clock signal; and
An integrated circuit comprising a third inverter circuit that receives the second internal signal and outputs the third internal signal. According to claim 13,
The second control stage is,
A first P-type transistor including a gate to which the clock signal is input and a source to which a power voltage is applied;
First to third N-type transistors connected in parallel with each other;
a fourth N-type transistor including a gate to which the first internal signal is input and a source to which a ground voltage is applied; and
An integrated circuit including a transmission gate circuit connected between the drain of the first P-type transistor and the drain of the first N-type transistor and switched by the clock signal and the inverted clock signal.

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