KR20240052400A - Mechanical non-volatile memory device and mechanical memory - Google Patents

Abstract

The present invention discloses mechanical non-volatile memory devices and mechanical memory. A mechanical non-volatile memory device includes a column decoder connected to a plurality of bit lines; A row decoder connected to a plurality of word lines; and a plurality of mechanical memory cells selected by the plurality of bit lines and the plurality of word lines, wherein an electrical signal is applied to the plurality of mechanical memory cells to addressed memory cells, and the non-addressed memory cells are applied to the plurality of mechanical memory cells. It is characterized in that the electrical state is formed by grounding. According to the present invention, it is possible to address and configure a mechanical non-volatile memory array reliably and stably. In addition, the operation of the mechanical memory is stably controlled, allowing it to be universally applied to various mechanical memories such as electrostatic drive, electrothermal drive, 3-electrode, and 4-electrode.

Description

Mechanical non-volatile memory device and mechanical memory {MECHANICAL NON-VOLATILE MEMORY DEVICE AND MECHANICAL MEMORY}

The present invention relates to a mechanical non-volatile memory device and a mechanical memory, and in particular, to maintain the gate electrodes of unaddressed word lines in a grounded state rather than a floating state, thereby enabling reliable and stable addressing and configuration of a memory array. Pertains to mechanical non-volatile memory devices and mechanical memory.

Generally, an FPGA is a semiconductor circuit that contains designable logic elements and programmable internal circuitry.

However, among FPGA circuits, reconfigurable interconnects based on SRAM had the problem of high standby power due to leakage current of SRAM.

In addition, there was a limit to low integration due to additional components such as pass transistors and buffers as well as SRAM.

To overcome these problems and limitations, mechanical non-volatile memory, which has advantages such as low power and low signal delay, has recently attracted attention as a next-generation memory semiconductor technology.

The operating principle of a general mechanical non-volatile memory (NEMS) is as follows.

Figure 1 is a perspective view of an off state (a) and an on state (b) of a three-electrode mechanical non-volatile memory to explain the operating principle of a general mechanical non-volatile memory.

As shown in FIG. 1(b), when a voltage is applied to the gate electrode of a three-electrode mechanical non-volatile memory, electrostatic force (FE) is generated between the gate electrode and the source electrode.

If the electrostatic force is greater than the mechanical restoring force of the beam-shaped source electrode, one lower surface of the source electrode contacts the upper surface of the drain electrode.

At this time, if the contact surface adhesive force between one lower surface of the source electrode and the upper surface of the drain electrode is designed to be greater than the mechanical restoring force of the source electrode, it is possible to implement operation as a non-volatile device.

Mechanical non-volatile memory (NEMS) with this operating principle has a high on/off ratio, subthreshold swing, fast operation speed due to low contact resistance, non-volatility, and stability in harsh external environments. It has advantages such as:

In addition, because standby power is close to '0', standby power can be reduced by about 90 to 94%, and the semiconductor manufacturing process can be completed in the back end of line (BEOL) without using SRAM and buffer. By using Monolithic 3D (M3D) integration, a new technology, the integration can be improved by up to two times.

Figure 2 is a partial circuit diagram of a plurality of memory cells according to a conventional mechanical memory array programming method.

FIG. 3 is a configuration diagram of some of the plurality of memory cells shown in FIG. 2, and the plurality of memory cells are divided into a plurality of row lines and a plurality of column lines.

For convenience of understanding, a cross-sectional view of the source electrode (S), gate electrode (G), and drain electrode (D) of the plurality of partitioned memory cells is shown.

FIG. 4 is a graph showing the change in drain-source current (I _DS ) compared to the change in gate-source voltage (V _GS ) applied to each of the plurality of row lines among the plurality of memory cells shown in FIG. 3 .

As shown in Figure 2, in the case of the conventional mechanical memory array programming method, only the WL (horizontal wire) of the memory to be programmed is grounded, and an input signal is applied to the BL (vertical wire).

However, in this case, the WL of the memory that is not programmed is in an electrically unstable floating state.

As a result, the source electrode of the corresponding memory cells of the memory that is not programmed is floated, and an input signal is applied to the gate electrode.

Accordingly, due to the characteristics of mechanical non-volatile memory, the operation of which is determined by the voltage difference between the gate electrode and the source electrode, when the source electrode is in a floating state, that is, the source electrode of a memory cell that is not configured is electrically unstable. , there is a possibility that unintended memory cells are actually programmed.

This condition ultimately results in a problem in which the operation of the entire memory array cannot be controlled stably and reliably.

In addition, as shown in FIG. 3, in the case of the conventional mechanical memory array programming method, the V _hold +V _select voltage is applied to the source electrode (S) only to the memory cells to be programmed, and the -V _select voltage is applied to the gate electrode (G). A voltage is applied and a V _hold +2V _select voltage difference is formed between the source electrode (S) and the gate electrode (G).

However, in this case, as shown in FIG. 4, the remaining memory cells do not operate because they are all below the memory operating voltage, and since the V _hold voltage is always applied to the source electrode (S), the memory state is maintained as is.

As a result, the V _hold voltage must always be applied to the source electrode (S) of the memory element, and when the voltage is cut off, all states of the memory are initialized.

Accordingly, the problem of inappropriate programming for non-volatile memory arises.

As such, the mechanical memory array programming method according to the prior art fails to apply an electrically stable and reliable voltage to the word line and bit line of the memory array, making it difficult to address and configure the memory array stably and reliably ( There was a limit to configuration.

Korean Patent No. 10-0945403

The purpose of the present invention is to provide a mechanical non-volatile memory that can reliably control the operation of the mechanical memory by activating only the gate electrode of the word line being addressed and maintaining the remaining gate electrodes in a grounded state rather than a floating state. The goal is to provide devices and mechanical memory.

To achieve the above object, a mechanical non-volatile memory device according to a first embodiment of the present invention includes a column decoder connected to a plurality of bit lines; A row decoder connected to a plurality of word lines; and a plurality of mechanical memory cells selected by the plurality of bit lines and the plurality of word lines, wherein an electrical signal is applied to the plurality of mechanical memory cells to addressed memory cells, and the non-addressed memory cells are applied to the plurality of mechanical memory cells. It is characterized in that the electrical state is formed by grounding.

A mechanical memory according to a second embodiment of the present invention for achieving the above object includes two pairs of vertical wires; a pair of horizontal wires wired in a direction perpendicular to the two pairs of vertical wires; a power line wired in a direction parallel to the pair of horizontal wires; a first drain electrode connected to the power line and supplied with power; a second drain electrode connected to a ground line among the two pairs of vertical wires; first and second AND gates whose input terminals are connected to first and second bit lines of the two pairs of vertical wires, respectively, and to word lines of the pair of horizontal wires; a first gate electrode to which the output terminal of the first AND gate is connected; a second gate electrode to which the output terminal of the second AND gate is connected; and a source electrode that outputs a program operation result or an erase operation result depending on whether an input signal is applied to the first and second gate electrodes. When the word line is activated, the input signal is input, When the word line is inactivated, the electrical state of the first and second gate electrodes is grounded.

Details of other embodiments are included in “Specific Details for Carrying Out the Invention” and the accompanying “Drawings.”

The advantages and/or features of the present invention and methods for achieving them will become clear by referring to the various embodiments described in detail below along with the accompanying drawings.

However, the present invention is not limited to the configuration of each embodiment disclosed below, but may also be implemented in various different forms. However, each embodiment disclosed in this specification is intended to ensure that the disclosure of the present invention is complete. It is provided to fully inform those skilled in the art of the present invention of the scope of the present invention, and it should be noted that the present invention is only defined by the scope of each claim in the claims.

According to the present invention, it is possible to address and configure a mechanical non-volatile memory array reliably and stably.

In addition, the operation of the mechanical memory is stably controlled, allowing it to be universally applied to various mechanical memories such as electrostatic drive, electrothermal drive, 3-electrode, and 4-electrode.

Figure 1 is a perspective view of an off state (a) and an on state (b) of a three-electrode mechanical non-volatile memory to explain the operating principle of a general mechanical non-volatile memory.
Figure 2 is a partial circuit diagram of a plurality of memory cells according to a conventional mechanical memory array programming method.
FIG. 3 is a configuration diagram of some of the plurality of memory cells shown in FIG. 2.
FIG. 4 is a graph showing the change in drain-source current (I _DS ) compared to the change in gate-source voltage (V _GS ) applied to each of the plurality of row lines among the plurality of memory cells shown in FIG. 3 .
Figure 5 is a configuration diagram for explaining the operation of a mechanical non-volatile memory device according to the first embodiment of the present invention.
Figure 6 is a configuration diagram for explaining the operation of a mechanical memory according to a second embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

Before explaining the present invention in detail, the terms or words used in this specification should not be construed as unconditionally limited to their ordinary or dictionary meanings, and the inventor of the present invention should not use the terms and conditions to explain his invention in the best way. The concepts of various terms can be appropriately defined and used.

Furthermore, it should be noted that these terms and words should be interpreted with meanings and concepts consistent with the technical idea of the present invention.

That is, the terms used in this specification are only used to describe preferred embodiments of the present invention, and are not used with the intention of specifically limiting the content of the present invention.

It should be noted that these terms are defined in consideration of various possibilities of the present invention.

Additionally, in this specification, singular expressions may include plural expressions unless the context clearly indicates a different meaning.

Additionally, it should be noted that even if similarly expressed in plural, it may have a singular meaning.

Throughout this specification, when a component is described as “including” another component, it does not exclude any other component, but rather includes any other component, unless specifically stated to the contrary. It could mean that you can do it.

Furthermore, when a component is described as being “installed within or connected to” another component, this component may be installed in direct connection or contact with the other component.

In addition, they may be installed at a certain distance, and in the case where they are installed at a certain distance, there may be a third component or means for fixing or connecting the component to another component. .

Meanwhile, it should be noted that the description of the third component or means may be omitted.

On the other hand, when a component is described as being “directly connected” or “directly connected” to another component, it should be understood that no third component or means is present.

In addition, in this specification, terms such as "one side", "other side", "one side", "the other side", "first", "second", etc. refer to one component with respect to another component. It is used to clearly distinguish from elements.

However, it should be noted that the meaning of the corresponding component is not limited by such a term.

In addition, in this specification, terms related to position such as “top”, “bottom”, “left”, “right”, etc., if used, should be understood as indicating the relative position of the corresponding component in the corresponding drawing.

Additionally, unless the absolute location is specified, these location-related terms should not be understood as referring to the absolute location.

Moreover, in the specification of the present invention, terms such as “… unit”, “… unit”, “module”, “device”, etc., when used, mean a unit capable of processing one or more functions or operations.

It should be noted that this can be implemented by hardware or software, or a combination of hardware and software.

In the drawings attached to this specification, the size, position, connection relationship, etc. of each component constituting the present invention is exaggerated, reduced, or omitted in order to convey the idea of the present invention sufficiently clearly or for convenience of explanation. It may be described, and therefore its proportions or scale may not be exact.

In addition, hereinafter, in describing the present invention, detailed descriptions of configurations that are judged to unnecessarily obscure the gist of the present invention, for example, known technologies including prior art, may be omitted.

Figure 5 is a configuration diagram for explaining the operation of a mechanical non-volatile memory device according to the first embodiment of the present invention, including a column decoder 100, a row decoder 200, and a plurality of memories. It includes a cell 300, a plurality of pads 400, and a plurality of scan registers 500, and the plurality of pads 400 include a scan in pad 410 and a write enable pad. (Write Enable Pad) 420, and Scan Out pad (Scan Out pad) 430.

Figure 6 is a configuration diagram for explaining the operation of a mechanical memory according to a second embodiment of the present invention, including two pairs of vertical wires 600, a pair of horizontal wires 700, a second power line 800, It includes a mechanical memory 900, first and second AND gates (AND1, AND2), and one transistor (T1), and the mechanical memory 900 includes first and second drain electrodes 910 and 920, and a first and second gate electrodes 930 and 940 and a source electrode 950.

The operation of the mechanical non-volatile memory device according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 5 as follows.

The present invention reliably and stably addresses and configures an operating memory array in order to overcome the problems and limitations of the mechanical memory array programming method according to the prior art.

In other words, an electrical signal is applied only to the memory cells that are being addressed (e.g., source = Ground, gate = 1 or 0), and the electrical state of each electrode is set to ground so that the remaining memory cells that are not being addressed do not operate. Form (e.g., source = Ground, gate = Ground).

The hardware configuration and operation of the mechanical non-volatile memory device according to the first embodiment of the present invention are as follows.

First, the hardware configuration includes a column decoder 100, a row decoder 200, a plurality of memory cells 300, a plurality of pads 400, a plurality of scan registers 500, and a plurality of pads 400. includes a scan in pad 410, a write enable pad 420, and a scan out pad 430.

The plurality of scan registers 500 are located between wires connecting the scan in pad 410 and the scan out pad 430, and input column numbers, data bits, row numbers, and word numbers.

The operation of the first embodiment of the present invention uses the column decoder 100 and the row decoder 200 to address and configure the mechanical memory 900.

That is, as shown in FIG. 5, the column decoder 100 and the row decoder 200 select the mechanical memory cell to be configured according to the column number and row number.

When the row decoder 200 selects a word line in a cell according to the input of a word number, as shown in the enlarged view in FIG. 5, 10 mechanical memories 900 within the selected word line store 10 data bits. (data bit) It is configured according to input.

Additionally, by utilizing a plurality of scan registers 500, data input settings can be made with only three inputs: the scan in pad 410, the write enable pad 420, and the scan out pad 430.

As shown in Figure 1 (b), when voltage is applied to the gate electrode, which is the first electrode of the three-electrode mechanical non-volatile memory, electrostatic force (FE) is generated between the gate electrode and the source electrode, which is the second electrode. However, when more than the operating voltage (pull-in voltage) is applied, a pull-in phenomenon occurs, as shown in (b) of FIG. 1.

If the electrostatic force is greater than the mechanical restoring force of the beam-shaped source electrode having a cantilever or cantilever structure, the lower surface of one side of the source electrode that can move up and down is the upper surface of the drain electrode, which is the third electrode. Contact.

That is, a drain electrode is placed below one side of the source electrode at a predetermined distance apart with a predetermined air gap in between, and the lower surface of one side of the source electrode can be adhered to the upper surface of the drain electrode by an electrostatic driving method. there is.

At this time, if the contact surface adhesive force between one lower surface of the source electrode and the upper surface of the drain electrode is designed to be greater than the mechanical restoring force of the source electrode, it is possible to implement operation as a non-volatile device.

That is, even if the voltage applied between the source electrode and the gate electrode is removed, the adhesive state of the contact surface between one lower surface of the source electrode and the upper surface of the drain electrode is maintained, as shown in FIG. 1 (b).

In this way, the phenomenon of maintaining the sticky state can be defined as an electrostatic drive program, and the program operation of the non-volatile memory device can be achieved.

Next, the operation of the mechanical memory according to the second embodiment of the present invention will be described in detail with reference to FIG. 6 as follows.

In Figure 6, for convenience of understanding, the fifth bit line (M5 Bit), the fifth ground line (M5 Gnd), and the fifth bit line bar (M5) are shown. ) and two pairs of vertical wires 610, 620 including the fifth ground line (M5 Gnd), and a pair of horizontal wires including the fourth word line (M4 Word) and the fourth power line (M4 Vdd) By showing only 700, it is set that the mechanical memory cell in the mechanical non-volatile memory device includes one mechanical memory 900.

However, an actual mechanical memory cell has a plurality of bit lines, word lines, power lines, and ground lines to form a plurality of cells.

The hardware configuration and operation of the mechanical memory according to the second embodiment of the present invention are as follows.

First, the hardware configuration includes two pairs of vertical wires 600, a pair of horizontal wires 700, a second power line 800, a mechanical memory 900, and first and second AND gates (AND1, AND2). , includes one transistor (T1).

The mechanical memory 900 includes first and second drain electrodes 910 and 920, first and second gate electrodes 930 and 940, and source electrode 950.

In this embodiment, for convenience of understanding, two pairs of vertical wires 600 are connected to a pair of the fifth bit line (M5 Bit) and the fifth ground line (M5 Gnd) and the fifth bit line bar (M5 ) and a fifth ground line (M5 Gnd), a pair of horizontal wires 700 are illustrated as a fourth word line (M4 Word) and a fourth power line (M4 Vdd), and the first drain The connection line will be explained by taking an example as a second power line.

The input terminal of the first AND gate AND1 is connected to the fifth bit line (M5 Bit) and the fourth word line (M4 Word), and the output terminal is connected to the first gate electrode 930.

The second AND gate (AND2) has an input terminal connected to the fifth bit line bar (M5). ) and the fourth word line (M4 Word), and the output terminal is connected to the second gate electrode 940.

Additionally, the middle electrode of one transistor T1 is connected to the fourth word line (M4 Word), one electrode is connected to the source electrode 950 of the mechanical memory 900, and the other electrode is grounded.

The operation of the second embodiment of the present invention is to program by inputting a signal to the gate electrode of the mechanical memory 900 through AND operation with the bit line when the word line is activated (word line = 1), and the word line is When not activated (word line = 0), the gate electrode of the mechanical memory 900 is always grounded and the logic value of the memory is maintained as is.

That is, as shown in FIG. 6, when the fourth word line (M4 Word) is activated at a high level, the result of the AND operation with the fifth bit line (M5 Bit) is transmitted to the mechanical memory through the first AND gate (AND1). It is programmed by inputting it into the first gate electrode 930 of 900.

In addition, the fifth bit line bar (M5) is formed through the second AND gate (AND2). ) and the result of the AND operation are input to the second gate electrode 940 of the mechanical memory 900 and erased.

At this time, one transistor (T1) whose middle electrode is connected to the fourth word line (M4 Word) is turned on, making the source electrode 950 in a ground state, and the first gate electrode 930 or the second A voltage difference is generated with the gate electrode 940, and programming or erasing can be performed through electrostatic force.

On the other hand, when the fourth word line (M4 Word) is deactivated at the low level, as shown in FIG. 6, '0' is the result of the AND operation with the fifth bit line (M5 Bit) through the first AND gate (AND1). ' is input to the first gate electrode 930 of the mechanical memory 900 to always be in a ground state.

In addition, the fifth bit line bar (M5) is formed through the second AND gate (AND2). '0', which is the result of the AND operation with ), is input to the second gate electrode 940 of the mechanical memory 900 to always be in a ground state.

Accordingly, the logical value of the corresponding mechanical memory 900 is maintained as is.

Through this, the present invention activates only the gate electrode of the word line being addressed among the mechanical non-volatile memory, and maintains the remaining gate electrodes in a grounded state rather than a floating state, thereby improving the operation of the memory in consideration of the operating characteristics of the mechanical non-volatile memory. It can be controlled stably and reliably.

As such, the present invention is a mechanical non-volatile memory that activates only the gate electrode of the addressed word line and maintains the remaining gate electrodes in a grounded state rather than a floating state, thereby reliably controlling the operation of the mechanical memory. Provides memory devices and mechanical memory.

Through this, the present invention enables reliable and stable addressing and configuration of a mechanical non-volatile memory array.

In addition, the operation of the mechanical memory is stably controlled, allowing it to be universally applied to various mechanical memories such as electrostatic drive, electrothermal drive, 3-electrode, and 4-electrode.

Above, various preferred embodiments of the present invention have been described by giving some examples, but the description of the various embodiments described in the "Detailed Contents for Carrying out the Invention" section is merely illustrative and the present invention Those skilled in the art will understand from the above description that the present invention can be implemented with various modifications or equivalent implementations of the present invention.

In addition, since the present invention can be implemented in various other forms, the present invention is not limited by the above description, and the above description is intended to make the disclosure of the present invention complete and is commonly used in the technical field to which the present invention pertains. It is provided only to fully inform those with knowledge of the scope of the present invention, and it should be noted that the present invention is only defined by each claim in the claims.

100: column decoder
200: Raw decoder
300: a plurality of memory cells
400: plural pads
500: Multiple scan registers
600: Two pairs of vertical wires
700: A pair of horizontal wires
800: second power line
900: mechanical memory

Claims (12)

A column decoder connected to a plurality of bit lines;
A row decoder connected to a plurality of word lines; and
a plurality of mechanical memory cells selected by the plurality of bit lines and the plurality of word lines;
Including,
The plurality of mechanical memory cells are characterized in that an electrical signal is applied to the addressed memory cells, and the electrical state of the unaddressed memory cells is ground.
Mechanical non-volatile memory device.
According to claim 1,
It is connected to the column decoder and a column number and data bit are input,
Characterized in that it further includes a plurality of scan registers connected to the row decoder and receiving row numbers and word numbers.
Mechanical non-volatile memory device.
According to claim 2,
Each of the plurality of mechanical memory cells,
Characterized in that a plurality of mechanical memories are configured according to the data bit input within the word line selected according to the input of the word number.
Mechanical non-volatile memory device.
According to claim 3,
The plurality of mechanical memories,
a first electrode to which voltage is applied;
a second electrode having one side movable up and down, positioned spaced apart in a beam shape on top of the first electrode, and generating electrostatic force between the second electrode and the first electrode; and
a third electrode disposed on the lower side of the second electrode with an air gap in between, and having its upper surface adhered to the lower surface of the second electrode by the electrostatic force;
Characterized by including
Mechanical non-volatile memory device.
According to claim 4,
The plurality of mechanical memories,
When the electrostatic force is greater than the mechanical restoring force of the second electrode, the adhesive state of the second electrode and the third electrode is maintained even when the voltage applied to the first electrode is removed, thereby operating the program operation of the non-volatile memory device. Characterized by being
Mechanical non-volatile memory device.
Two pairs of longitudinal wires;
a pair of horizontal wires wired in a direction perpendicular to the two pairs of vertical wires;
a power line wired in a direction parallel to the pair of horizontal wires;
a first drain electrode connected to the power line and supplied with power;
a second drain electrode connected to a ground line among the two pairs of vertical wires;
first and second AND gates whose input terminals are connected to first and second bit lines of the two pairs of vertical wires, respectively, and to word lines of the pair of horizontal wires;
a first gate electrode to which the output terminal of the first AND gate is connected;
a second gate electrode to which the output terminal of the second AND gate is connected; and
a source electrode that outputs a program operation result or an erase operation result depending on whether an input signal is applied to the first and second gate electrodes;
Including,
When the word line is activated, the input signal is input, and when the word line is inactivated, the electrical state of the first and second gate electrodes is grounded.
Mechanical memory.
According to claim 6,
The source electrode is,
The middle electrode is connected to the word line, and is grounded through conduction of one electrode and the other electrode of the transistor, which is turned on or off depending on whether the word line is activated.
Mechanical memory.
According to claim 6,
The first and second bit lines are,
Characterized by the logical values being mutually opposite.
Mechanical memory.
According to claim 6,
The two pairs of vertical wires are,
a pair of the first bit line and the ground line; and
a pair of the second bit line and the ground line;
Characterized by including
Mechanical memory.
According to claim 6,
The pair of horizontal wires is,
Characterized in that it includes the word line and the power line.
Mechanical memory.
According to claim 6,
The first and second gate electrodes are,
When the word line is activated,
Receive the result of the AND operation between the word line and the first bit line through the output terminal of the first AND gate,
Receive the result of the AND operation between the word line and the second bit line through the output terminal of the second AND gate,
Characterized in that the source electrode outputs the program operation result.
Mechanical memory.
According to claim 6,
The first and second gate electrodes are,
When the word line is deactivated,
Receive '0', which is the result of the AND operation between the word line and the first bit line, through the output terminal of the first AND gate,
Receive '0', which is the result of the AND operation between the word line and the second bit line, through the output terminal of the second AND gate,
Characterized in that the electrical state is formed by grounding
Mechanical memory.

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