KR20240052153A - Semiconductor package - Google Patents

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Publication number
KR20240052153A
KR20240052153A KR1020220131669A KR20220131669A KR20240052153A KR 20240052153 A KR20240052153 A KR 20240052153A KR 1020220131669 A KR1020220131669 A KR 1020220131669A KR 20220131669 A KR20220131669 A KR 20220131669A KR 20240052153 A KR20240052153 A KR 20240052153A
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South Korea
Prior art keywords
semiconductor chip
disposed
redistribution structure
heat dissipation
encapsulant
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KR1020220131669A
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Korean (ko)
Inventor
이상웅
Original Assignee
삼성전자주식회사
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Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020220131669A priority Critical patent/KR20240052153A/en
Priority to US18/204,970 priority patent/US20240128195A1/en
Priority to JP2023128295A priority patent/JP2024058577A/en
Publication of KR20240052153A publication Critical patent/KR20240052153A/en

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    • H01L2924/014—Solder alloys

Abstract

본 발명의 일 실시 예에 따른 반도체 패키지는, 적어도 하나의 제1 재배선층과 적어도 하나의 제1 절연층이 교대로 적층된 제1 재배선 구조물과, 제1 재배선 구조물의 일면 상에 배치된 제1 반도체 칩과, 제1 재배선 구조물과 제1 반도체 칩의 사이에 배치된 봉합재와, 제1 재배선 구조물과 제1 반도체 칩을 전기적으로 연결하고 봉합재를 관통하는 제1 도전성 포스트들과, 적어도 일부분이 제1 도전성 포스트들이 관통하는 방향에 수직인 방향으로 제1 반도체 칩에 중첩되도록 배치되는 방열 부재와, 적어도 일부분이 제1 재배선 구조물과 방열 부재의 사이에 배치되고 봉합재에 의해 봉합되는 제2 반도체 칩을 포함하고, 제1 반도체 칩은 제1 도전성 포스트들이 관통하는 방향으로 제1 도전성 포스트들에 중첩되고 제2 반도체 칩에 중첩되지 않도록 배치될 수 있다.A semiconductor package according to an embodiment of the present invention includes a first redistribution structure in which at least one first redistribution layer and at least one first insulating layer are alternately stacked, and disposed on one surface of the first redistribution structure. An encapsulant disposed between the first semiconductor chip, the first redistribution structure and the first semiconductor chip, and first conductive posts that electrically connect the first redistribution structure and the first semiconductor chip and penetrate the encapsulant. and a heat dissipation member, at least a portion of which is disposed to overlap the first semiconductor chip in a direction perpendicular to the direction through which the first conductive posts penetrate, and at least a portion of the member is disposed between the first redistribution structure and the heat dissipation member and is attached to the encapsulant. It may include a second semiconductor chip sealed by a second semiconductor chip, and the first semiconductor chip may be disposed to overlap the first conductive posts in a direction through which the first conductive posts pass and not to overlap the second semiconductor chip.

Figure P1020220131669
Figure P1020220131669

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}Semiconductor package {SEMICONDUCTOR PACKAGE}

본 발명은 반도체 패키지에 관한 것이다.The present invention relates to semiconductor packages.

일반적으로, 반도체 칩은 WLP(Wafer Level Package)나 PLP(Panel Level Package)와 같은 반도체 패키지로 구현될 수 있으며, 반도체 패키지는 기기의 전자부품으로서 사용될 수 있다.Generally, a semiconductor chip may be implemented as a semiconductor package such as a wafer level package (WLP) or a panel level package (PLP), and the semiconductor package may be used as an electronic component of a device.

반도체 패키지는 반도체 칩을 기기나 인쇄회로기판에 전기적으로 연결시키기 위한 재배선층(Redistribution Layer)을 포함할 수 있다. 재배선층은 일반적인 인쇄회로기판의 배선층의 배선보다 더 미세하게 구현된 재배선이 수평적으로 연장된 구조를 가질 수 있다.A semiconductor package may include a redistribution layer to electrically connect the semiconductor chip to a device or printed circuit board. The redistribution layer may have a structure in which redistribution that is more finely implemented than that of a typical printed circuit board wiring layer extends horizontally.

재배선층은 전기적 연결 경로를 수직적으로 연장하기 위해 범프(bump)에 전기적으로 연결될 수 있고, UBM(Under Bump Metallurgy)은 재배선층과 범프 사이의 전기적 연결을 효율을 향상시킬 수 있다.The redistribution layer can be electrically connected to a bump to vertically extend the electrical connection path, and UBM (Under Bump Metallurgy) can improve the efficiency of the electrical connection between the redistribution layer and the bump.

반도체 칩이 제공할 수 있는 시스템은 점차 복잡해지고 반도체 칩의 성능은 점차 높아지고 있으므로, 반도체 패키지의 집적도는 점차 높게 요구될 수 있고, 반도체 패키지의 단위 성능 대비 크기는 더 작게 요구될 수 있다. 그러나, 반도체 패키지의 집적도가 높아지거나 단위 성능 대비 크기가 작아질수록, 반도체 패키지의 방열성능 확보 난이도는 높아질 수 있다.As the systems that semiconductor chips can provide are becoming increasingly complex and the performance of semiconductor chips is gradually increasing, the integration degree of the semiconductor package may be required to be increasingly higher, and the size of the semiconductor package may be required to be smaller compared to the unit performance. However, as the degree of integration of the semiconductor package increases or the size relative to unit performance decreases, the difficulty in securing the heat dissipation performance of the semiconductor package may increase.

본 발명은 방열성능을 확보하기 유리한 반도체 패키지를 제공한다.The present invention provides a semiconductor package that is advantageous in securing heat dissipation performance.

본 발명의 일 실시 예에 따른 반도체 패키지는, 적어도 하나의 제1 재배선층과 적어도 하나의 제1 절연층이 교대로 적층된 제1 재배선 구조물; 상기 제1 재배선 구조물의 일면 상에 배치된 제1 반도체 칩; 상기 제1 재배선 구조물과 상기 제1 반도체 칩의 사이에 배치된 봉합재; 상기 제1 재배선 구조물과 상기 제1 반도체 칩을 전기적으로 연결하고 상기 봉합재를 관통하는 제1 도전성 포스트들; 적어도 일부분이 상기 제1 도전성 포스트들이 관통하는 방향에 수직인 방향으로 상기 제1 반도체 칩에 중첩되도록 배치되는 방열 부재; 및 적어도 일부분이 상기 제1 재배선 구조물과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제2 반도체 칩; 을 포함하고, 상기 제1 반도체 칩은 상기 제1 도전성 포스트들이 관통하는 방향으로 상기 제1 도전성 포스트들에 중첩되고 상기 제2 반도체 칩에 중첩되지 않도록 배치될 수 있다.A semiconductor package according to an embodiment of the present invention includes a first redistribution structure in which at least one first redistribution layer and at least one first insulating layer are alternately stacked; a first semiconductor chip disposed on one surface of the first redistribution structure; an encapsulant disposed between the first redistribution structure and the first semiconductor chip; first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip and penetrating the encapsulant; a heat dissipation member disposed so that at least a portion thereof overlaps the first semiconductor chip in a direction perpendicular to the direction through which the first conductive posts pass; and a second semiconductor chip, at least a portion of which is disposed between the first redistribution structure and the heat dissipation member and sealed by the encapsulant. It may be arranged so that the first semiconductor chip overlaps the first conductive posts in a direction through which the first conductive posts pass and does not overlap the second semiconductor chip.

본 발명의 일 실시 예에 따른 반도체 패키지는, 적어도 하나의 제1 재배선층과 적어도 하나의 제1 절연층이 교대로 적층된 제1 재배선 구조물; 상기 제1 재배선 구조물의 일면 상에 배치된 제1 반도체 칩; 상기 제1 재배선 구조물과 상기 제1 반도체 칩의 사이에 배치된 봉합재; 상기 제1 재배선 구조물과 상기 제1 반도체 칩을 전기적으로 연결하고 상기 봉합재를 관통하는 제1 도전성 포스트들; 적어도 일부분이 상기 제1 도전성 포스트들이 관통하는 방향에 수직인 방향으로 상기 제1 반도체 칩에 중첩되도록 배치되는 방열 부재; 적어도 일부분이 상기 제1 재배선 구조물과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제2 반도체 칩; 및 상기 제2 반도체 칩과 상기 방열 부재의 사이에 배치되고 적어도 하나의 제2 재배선층과 적어도 하나의 제2 절연층이 교대로 적층된 제2 재배선 구조물; 을 포함할 수 있다.A semiconductor package according to an embodiment of the present invention includes a first redistribution structure in which at least one first redistribution layer and at least one first insulating layer are alternately stacked; a first semiconductor chip disposed on one surface of the first redistribution structure; an encapsulant disposed between the first redistribution structure and the first semiconductor chip; first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip and penetrating the encapsulant; a heat dissipation member disposed so that at least a portion thereof overlaps the first semiconductor chip in a direction perpendicular to the direction through which the first conductive posts pass; a second semiconductor chip, at least a portion of which is disposed between the first redistribution structure and the heat dissipation member and sealed by the encapsulant; and a second redistribution structure disposed between the second semiconductor chip and the heat dissipation member and including at least one second redistribution layer and at least one second insulating layer alternately stacked. may include.

본 발명의 일 실시 예에 따른 반도체 패키지는, 적어도 하나의 제1 재배선층과 적어도 하나의 제1 절연층이 교대로 적층된 제1 재배선 구조물; 상기 제1 재배선 구조물의 일면 상에 배치된 제1 반도체 칩; 상기 제1 재배선 구조물과 상기 제1 반도체 칩의 사이에 배치된 봉합재; 상기 제1 재배선 구조물과 상기 제1 반도체 칩을 전기적으로 연결하고 상기 봉합재를 관통하는 제1 도전성 포스트들; 적어도 일부분이 상기 제1 도전성 포스트들이 관통하는 방향에 수직인 방향으로 상기 제1 반도체 칩에 중첩되도록 배치되는 방열 부재; 적어도 일부분이 상기 제1 재배선 구조물과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제2 반도체 칩; 상기 제2 반도체 칩과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제3 반도체 칩; 및 상기 제1 재배선 구조물의 타면 상에 배치되고 상기 제1 및 제2 반도체 칩 중 적어도 하나에 전기적으로 연결되는 제1 범프들; 을 포함하고, 상기 제1 및 제2 반도체 칩은 상기 제1 재배선 구조물을 통해 서로 전기적으로 연결되고, 상기 제1 도전성 포스트들은 상기 봉합재의 중심에서부터 제1 방향으로 치우쳐져 배치되고, 상기 제2 및 제3 반도체 칩은 상기 봉합재의 중심에서부터 상기 제1 방향과 다른 제2 방향으로 치우쳐져 배치될 수 있다.A semiconductor package according to an embodiment of the present invention includes a first redistribution structure in which at least one first redistribution layer and at least one first insulating layer are alternately stacked; a first semiconductor chip disposed on one surface of the first redistribution structure; an encapsulant disposed between the first redistribution structure and the first semiconductor chip; first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip and penetrating the encapsulant; a heat dissipation member disposed so that at least a portion thereof overlaps the first semiconductor chip in a direction perpendicular to the direction through which the first conductive posts pass; a second semiconductor chip, at least a portion of which is disposed between the first redistribution structure and the heat dissipation member and sealed by the encapsulant; a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member and sealed by the encapsulant; and first bumps disposed on the other side of the first redistribution structure and electrically connected to at least one of the first and second semiconductor chips; Includes, wherein the first and second semiconductor chips are electrically connected to each other through the first redistribution structure, the first conductive posts are arranged to be deviated from the center of the encapsulant in a first direction, and the second And the third semiconductor chip may be disposed deviated from the center of the encapsulant in a second direction different from the first direction.

본 발명의 일 실시 예에 따른 반도체 패키지는, 방열성능을 확보하기 유리할 수 있다.The semiconductor package according to an embodiment of the present invention may be advantageous in securing heat dissipation performance.

도 1a 내지 도 1d는 본 발명의 일 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.
도 2a 내지 도 2c는 본 발명의 일 실시 예에 따른 반도체 패키지를 나타낸 평면도이다.
도 3a 내지 도 3f는 본 발명의 일 실시 예에 따른 반도체 패키지의 제조 과정을 예시한 단면도이다.
도 4a 내지 도 4e는 본 발명의 일 실시 예에 따른 반도체 패키지의 제조 과정을 예시한 단면도이다.1A to 1D are cross-sectional views showing a semiconductor package according to an embodiment of the present invention.
2A to 2C are plan views showing a semiconductor package according to an embodiment of the present invention.
3A to 3F are cross-sectional views illustrating the manufacturing process of a semiconductor package according to an embodiment of the present invention.
4A to 4E are cross-sectional views illustrating the manufacturing process of a semiconductor package according to an embodiment of the present invention.

후술하는 본 발명에 대한 상세한 설명은, 본 발명이 실시될 수 있는 특정 실시예를 예시로서 도시하는 첨부 도면을 참조한다. 이들 실시예는 당업자가 본 발명을 실시할 수 있기에 충분하도록 상세히 설명된다. 본 발명의 다양한 실시예는 서로 다르지만 상호 배타적일 필요는 없음이 이해되어야 한다. 예를 들어, 여기에 기재되어 있는 특정 형상, 구조 및 특성은 일 실시예에 관련하여 본 발명의 정신 및 범위를 벗어나지 않으면서 다른 실시예로 구현될 수 있다. 또한, 각각의 개시된 실시예 내의 개별 구성요소의 위치 또는 배치는 본 발명의 정신 및 범위를 벗어나지 않으면서 변경될 수 있음이 이해되어야 한다. 따라서, 후술하는 상세한 설명은 한정적인 의미로서 취하려는 것이 아니며, 본 발명의 범위는, 그 청구항들이 주장하는 것과 균등한 모든 범위와 더불어 첨부된 청구항에 의해서만 한정된다. 도면에서 유사한 참조부호는 여러 측면에 걸쳐서 동일하거나 유사한 기능을 지칭한다.The detailed description of the present invention described below refers to the accompanying drawings, which show by way of example specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different from one another but are not necessarily mutually exclusive. For example, specific shapes, structures and characteristics described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the invention. Additionally, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the detailed description set forth below is not intended to be taken in a limiting sense, and the scope of the present invention is limited only by the appended claims, together with all equivalents to what those claims assert. Similar reference numbers in the drawings refer to identical or similar functions across various aspects.

이하에서는, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있도록 하기 위하여, 본 발명의 실시예들에 관하여 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings in order to enable those skilled in the art to easily practice the present invention.

도 1a는 본 발명의 일 실시 예에 따른 반도체 패키지를 XZ평면으로 절단함에 따른 단면을 나타내고, 도 2a는 도 1a의 반도체 패키지를 도 1a의 좌우측 I1을 따라 XY평면으로 절단함에 따른 단면을 나타낸다.FIG. 1A shows a cross section of a semiconductor package according to an embodiment of the present invention when cut along the

도 1a 및 도 2a를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지(300a)는, 제1 재배선 구조물(110), 제1 반도체 칩(250), 봉합재(160), 제1 도전성 포스트들(155P), 방열 부재(281) 및 제2 반도체 칩(120)을 포함할 수 있다. 반도체 패키지(300a)는 2개 이상의 반도체 칩을 포함하는 시스템 인 패키지(System in Package, SIP)일 수 있다.1A and 2A, the semiconductor package 300a according to an embodiment of the present invention includes a first redistribution structure 110, a first semiconductor chip 250, an encapsulant 160, and a first conductive device. It may include posts 155P, a heat dissipation member 281, and a second semiconductor chip 120. The semiconductor package 300a may be a system in package (SIP) including two or more semiconductor chips.

제1 재배선 구조물(110)은 적어도 하나의 제1 재배선층(112)과 적어도 하나의 제1 절연층(111)이 교대로 적층된 구조를 가질 수 있다. 제1 재배선 구조물(110)은 적어도 하나의 제1 재배선층(112)에서부터 제1 재배선 구조물(110)의 적층 방향(예: z방향)으로 연장되는 제1 비아들(113)을 더 포함할 수 있다. 제1 비아들(113)은 적어도 하나의 제1 절연층(111)을 관통할 수 있다.The first redistribution structure 110 may have a structure in which at least one first redistribution layer 112 and at least one first insulating layer 111 are alternately stacked. The first redistribution structure 110 further includes first vias 113 extending from at least one first redistribution layer 112 in the stacking direction (e.g., z-direction) of the first redistribution structure 110. can do. The first vias 113 may penetrate at least one first insulating layer 111.

적어도 하나의 제1 절연층(111)은 절연 물질을 포함하며, 예컨대, 에폭시 수지와 같은 열경화성 수지 또는 폴리이미드와 같은 열가소성 수지를 포함할 수 있다. 예를 들어, 적어도 하나의 제1 절연층(111)은 PID(Photo Imeagable Dielectric) 수지와 같은 감광성 절연 물질을 포함할 수 있다. 또는, 적어도 하나의 절연층(111)은 무기필러와 혼합된 수지, 예컨대, ABF(Ajinomoto Build-up Film)를 포함할 수도 있다. 또는, 적어도 하나의 제1 절연층(111)은 프리프레그(prepreg), FR-4(Flame Retardant), 또는 BT(Bismaleimide Triazine)을 포함할 수도 있다. 적어도 하나의 제1 절연층(111)은 서로 동일하거나 다른 물질을 포함할 수 있고, 각 층을 이루는 물질 및 공정 등에 따라, 사이의 경계가 구분되지 않을 수도 있다.At least one first insulating layer 111 includes an insulating material and may include, for example, a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. For example, at least one first insulating layer 111 may include a photosensitive insulating material such as PID (Photo Imeagable Dielectric) resin. Alternatively, at least one insulating layer 111 may include a resin mixed with an inorganic filler, for example, Ajinomoto Build-up Film (ABF). Alternatively, at least one first insulating layer 111 may include prepreg, flame retardant (FR-4), or bismaleimide triazine (BT). At least one first insulating layer 111 may include the same or different materials, and depending on the materials and processes forming each layer, the boundary between them may not be distinct.

제1 재배선층들(112) 및 제1 비아들(113)은 제1 전기적 경로들(115)을 형성할 수 있다. 제1 재배선층들(112)은 XY평면 상에서 라인 형태로 배치될 수 있으며, 제1 비아들(113)은 하부 또는 상부를 향하며 폭이 좁아지도록 경사진 측면을 갖는 원통 형상을 가질 수 있다. 제1 비아들(113)은 내부가 도전성 물질로 완전히 충전된 필드(filled) 비아 구조로 도시되었으나, 이에 한정되지는 않는다. 예를 들어, 제1 비아들(113)은 비아 홀의 내벽을 따라 금속 물질이 형성된 컨포멀(conformal) 비아 형태를 가질 수도 있다.The first redistribution layers 112 and the first vias 113 may form first electrical paths 115 . The first redistribution layers 112 may be arranged in a line shape on the The first vias 113 are shown as filled via structures whose interiors are completely filled with a conductive material, but the structure is not limited thereto. For example, the first vias 113 may have a conformal via shape in which a metal material is formed along the inner wall of the via hole.

제1 재배선층들(112) 및 제1 비아들(113)은 도전성 물질을 포함할 수 있으며, 예를 들어, 구리(Cu), 알루미늄(Al), 은(Ag), 주석(Sn), 금(Au), 니켈(Ni), 납(Pb), 티타늄(Ti), 또는 이들의 합금을 포함할 수 있다.The first redistribution layers 112 and the first vias 113 may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), or gold. (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

제1 반도체 칩(250)은 제1 재배선 구조물(110)의 일면(110T) 상에 배치될 수 있고, 적어도 하나의 제1 재배선층(112)에 전기적으로 연결될 수 있다. 예를 들어, 제1 반도체 칩(250)은 제1 반도체 칩(251)의 하면에 배치된 접속 패드들(254)을 포함할 수 있고, 접속 패드들(254)을 통해 적어도 하나의 제1 재배선층(112)에 전기적으로 연결될 수 있다. 예를 들어, 접속 패드들(254)은 텅스텐(W), 알루미늄(Al), 구리(Cu) 등과 같은 도전성 물질을 포함할 수 있고, 베어(bare) 칩의 패드, 예를 들어, 알루미늄(Al) 패드일 수 있으나, 실시예들에 따라서, 패키지드(packaged) 칩의 패드, 예를 들어, 구리(Cu) 패드일 수도 있다.The first semiconductor chip 250 may be disposed on one surface 110T of the first redistribution structure 110 and may be electrically connected to at least one first redistribution layer 112. For example, the first semiconductor chip 250 may include connection pads 254 disposed on the lower surface of the first semiconductor chip 251, and connect at least one first material through the connection pads 254. It may be electrically connected to the wiring layer 112. For example, the connection pads 254 may include a conductive material such as tungsten (W), aluminum (Al), copper (Cu), etc., and may be made of a pad of a bare chip, for example, aluminum (Al). ) It may be a pad, but depending on embodiments, it may also be a pad of a packaged chip, for example, a copper (Cu) pad.

예를 들어, 제1 반도체 칩(251)은 실리콘(Si), 게르마늄(Ge), 갈륨비소(GaAs) 등의 반도체 재료를 함유하는 몸체부와, 상기 몸체부의 하부에 배치되며 집적 회로(Integrated Circuit, IC)를 포함하는 소자층을 포함할 수 있다. 제1 반도체 칩(251)은 로직 반도체 칩 및/또는 메모리 반도체 칩을 포함할 수 있다. 상기 로직 반도체 칩은 마이크로 프로세서(micro-processor)일 수 있고, 예를 들어 중앙 처리 장치(Central Processing Unit, CPU), 그래픽 프로세서(Graphic Processing Unit, GPU), 필드 프로그램어블 게이트 어레이(Field Programmable Gate Array, FPGA), 어플리케이션 프로세서(AP), 디지털 신호 프로세서, 암호화 프로세서, 컨트롤러(controller), 또는 주문형 반도체(application specific integrated circuit, ASIC)일 수 있다. 상기 메모리 반도체 칩은 DRAM(dynamic random access memory), SRAM(static random access memory) 등과 같은 휘발성 메모리, 또는 플래시 메모리 등과 같은 비휘발성 메모리일 수 있다.For example, the first semiconductor chip 251 includes a body containing semiconductor materials such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs), and is disposed below the body and is an integrated circuit. , IC) may be included. The first semiconductor chip 251 may include a logic semiconductor chip and/or a memory semiconductor chip. The logic semiconductor chip may be a microprocessor, for example, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or a Field Programmable Gate Array. , FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a controller, or an application specific integrated circuit (ASIC). The memory semiconductor chip may be volatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), or non-volatile memory such as flash memory.

봉합재(160)는 제1 재배선 구조물(110)과 제1 반도체 칩(250)의 사이에 배치될 수 있다. 예를 들어, 봉합재(160)는 EMC(Epoxy Molding Compound)와 같은 몰딩 재료를 함유할 수 있다. 그러나, 봉합재(160)에 함유될 수 있는 재료는 몰딩 재료로 한정되지는 않으며, 몰딩 재료와 유사한 보호 특성이나 높은 연성을 가질 수 있는 절연 재료를 함유할 수도 있다. 예를 들어, 상기 절연 재료는 에폭시 수지와 같은 열경화성 수지나 폴리이미드와 같은 열가소성 수지일 수 있고, 제1 절연층(111)의 절연 재료에 무기필러 및/또는 유리섬유가 적절히 첨가된 절연 재료일 수도 있다.The encapsulant 160 may be disposed between the first redistribution structure 110 and the first semiconductor chip 250. For example, the encapsulant 160 may contain a molding material such as EMC (Epoxy Molding Compound). However, materials that may be contained in the encapsulant 160 are not limited to molding materials, and may also contain insulating materials that may have similar protective properties or high ductility as the molding materials. For example, the insulating material may be a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, and may be an insulating material in which an inorganic filler and/or glass fiber is appropriately added to the insulating material of the first insulating layer 111. It may be possible.

제1 도전성 포스트들(155P)은 제1 재배선 구조물(110)과 제1 반도체 칩(250)을 전기적으로 연결하고 봉합재(160)를 관통할 수 있다. 예를 들어, 제1 도전성 포스트들(155P)은 봉합재(160)보다 먼저 형성될 수 있고, 봉합재(160)보다 먼저 임시적으로 형성된 포토 레지스트(photo resist)의 관통 구멍들 내에 금속 재료(예: 구리)를 도금하는 공정이나 도전성 패이스트(paste)를 채우는 공정에 의해 형성될 수 있다.The first conductive posts 155P may electrically connect the first redistribution structure 110 and the first semiconductor chip 250 and penetrate the encapsulant 160 . For example, the first conductive posts 155P may be formed before the encapsulant 160, and a metal material (e.g., : It can be formed by a process of plating copper) or a process of filling conductive paste.

제2 반도체 칩(120)의 적어도 일부분은 제1 재배선 구조물(110)과 방열 부재(281)의 사이에 배치되고 봉합재(160)에 의해 봉합될 수 있다. 제2 반도체 칩(120)은 제1 반도체 칩(250)과 유사한 방식으로 구현될 수 있다. 예를 들어, 제2 반도체 칩(120)은 실리콘(Si), 게르마늄(Ge), 갈륨비소(GaAs) 등의 반도체 재료를 함유하는 몸체부(121)와, 몸체부의 하부에 배치되며 집적 회로(Integrated Circuit, IC)를 포함하는 소자층(122)을 포함할 수 있다.At least a portion of the second semiconductor chip 120 may be disposed between the first redistribution structure 110 and the heat dissipation member 281 and sealed by the encapsulant 160 . The second semiconductor chip 120 may be implemented in a similar manner to the first semiconductor chip 250. For example, the second semiconductor chip 120 includes a body portion 121 containing semiconductor materials such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs), and is disposed on the lower part of the body portion and includes an integrated circuit ( It may include a device layer 122 including an integrated circuit (IC).

예를 들어, 제2 반도체 칩(120)은 로직 반도체 칩일 수 있고, 제1 반도체 칩(251)은 메모리 반도체 칩일 수 있다. 제1 및 제2 반도체 칩(250)은 제1 재배선 구조물(110)의 제1 재배선층(112)을 통해 서로 전기적으로 연결될 수 있다.For example, the second semiconductor chip 120 may be a logic semiconductor chip, and the first semiconductor chip 251 may be a memory semiconductor chip. The first and second semiconductor chips 250 may be electrically connected to each other through the first redistribution layer 112 of the first redistribution structure 110.

예를 들어, 제2 반도체 칩(120)은 제2 반도체 칩(120)의 하면에 배치된 접속 패드들(124)을 포함할 수 있고, 접속 패드들(124)과 범프들(145A)을 통해 플립-칩 본딩(flip-chip bonding) 방식으로 제1 재배선 구조물(110)의 상면 상에 실장될 수 있다. 이에 따라, 제2 반도체 칩(120)은 적어도 하나의 제1 재배선층(112)에 전기적으로 연결될 수 있다. 예를 들어, 범프들(145A)은 주석(Sn) 또는 주석(Sn)을 포함하는 합금(Sn-Ag-Cu)을 함유하는 솔더(solder)를 포함할 수 있고, 비도전성 필름층(146A)에 의해 둘러싸일 수 있다. 비도전성 필름층(146A)은 언더필층으로 지칭될 수도 있고, 비도전성 폴리머를 포함할 수 있으며, 비도전성 페이스트(non conductive paste, NCP)를 포함할 수 있다.For example, the second semiconductor chip 120 may include connection pads 124 disposed on the lower surface of the second semiconductor chip 120, and through the connection pads 124 and the bumps 145A. It may be mounted on the top surface of the first redistribution structure 110 using a flip-chip bonding method. Accordingly, the second semiconductor chip 120 may be electrically connected to at least one first redistribution layer 112. For example, the bumps 145A may include solder containing tin (Sn) or an alloy containing tin (Sn) (Sn-Ag-Cu), and the non-conductive film layer 146A can be surrounded by The non-conductive film layer 146A may be referred to as an underfill layer, may include a non-conductive polymer, and may include a non-conductive paste (NCP).

방열 부재(281)의 적어도 일부분은 제1 도전성 포스트들(155P)이 관통하는 방향(예: Z방향)에 수직인 방향(예: X방향)으로 제1 반도체 칩(250)에 중첩되도록 배치될 수 있다. 예를 들어, 방열 부재(281)는 히트 슬러그(heat slug)로 구성될 수 있고, 공기보다 열전도율이 큰 물질(예: 금(Au), 은(Ag), 구리(Cu), 철(Fe), 그라파이트(Graphite), 그라핀(Graphene))을 포함할 수 있다. 일 예로, 방열 부재(281)에 함유될 수 있는 구리는 대략 401W/mk의 열전도율을, 공기는 대략 0.025W/mk의 열전도율을 가질 수 있다. 따라서, 방열 부재(281)는 내부의 열을 외부로 효율적으로 발산시킬 수 있다. 설계에 따라, 방열 부재(281)는 부피 대비 공기와의 접촉 면적이 많은 형태를 가짐으로써 열을 외부로 효율적으로 발산시킬 수 있다.At least a portion of the heat dissipation member 281 may be disposed to overlap the first semiconductor chip 250 in a direction (e.g., X direction) perpendicular to the direction (e.g., Z direction) through which the first conductive posts 155P pass. You can. For example, the heat dissipation member 281 may be composed of a heat slug, and may be made of a material with higher thermal conductivity than air (e.g., gold (Au), silver (Ag), copper (Cu), iron (Fe) , graphite, and graphene). As an example, copper that may be contained in the heat dissipation member 281 may have a thermal conductivity of approximately 401 W/mk, and air may have a thermal conductivity of approximately 0.025 W/mk. Accordingly, the heat dissipation member 281 can efficiently dissipate internal heat to the outside. Depending on the design, the heat dissipation member 281 can efficiently dissipate heat to the outside by having a shape that has a large contact area with air relative to its volume.

예를 들어, 방열 부재(281)는 열전달물질층(282)의 상면에 접촉 및 배치될 수 있다. 열전달물질층(282)은 공기보다 높고 방열 부재(281)보다 낮은 열전도율(예: 2W/mk 내지 3W/mk)을 가지도록 구성될 수 있다. 따라서, 열전달물질층(282)은 제2 및 제3 반도체 칩(120, 130)에서 발생된 열을 방열 부재(281)로 효율적으로 전달할 수 있다. 예를 들어, 열전달물질층(282)은 접착성 폴리머(polymer)를 함유함으로써 방열 부재(281)에 대한 접착성을 향상시킬 수 있고, 접착성 폴리머 내에 분산된 금속 입자를 함유함으로써 높아진 열전도율을 가질 수 있다. 열전달물질층(282)의 열전도율은 금속 입자의 밀도에 기반하여 결정될 수 있다.For example, the heat dissipation member 281 may be in contact with and disposed on the upper surface of the heat transfer material layer 282. The heat transfer material layer 282 may be configured to have a thermal conductivity higher than that of air and lower than that of the heat dissipation member 281 (eg, 2 W/mk to 3 W/mk). Accordingly, the heat transfer material layer 282 can efficiently transfer heat generated by the second and third semiconductor chips 120 and 130 to the heat dissipation member 281. For example, the heat transfer material layer 282 may improve adhesion to the heat dissipation member 281 by containing an adhesive polymer, and may have increased thermal conductivity by containing metal particles dispersed in the adhesive polymer. You can. The thermal conductivity of the heat transfer material layer 282 may be determined based on the density of metal particles.

방열 부재(281)의 적어도 일부분이 수평방향(예: X방향)으로 제1 반도체 칩(250)에 중첩되도록 배치될 수 있으므로, 제1 반도체 칩(250)에서 발생된 열도 흡수할 수 있고, 흡수한 열을 외부로 발산할 수 있다. 또한, 반도체 패키지(300a)에 방열 부재(281)가 추가되는 것은 반도체 패키지(300a)의 총 높이에 실질적으로 영향을 주지 않을 수 있다. 따라서, 본 발명의 일 실시 예에 따른 반도체 패키지(300a)는 방열 부재(281)의 방열성능을 효율적으로 사용할 수 있고, 반도체 패키지(300a)의 전반적인 집적도도 확보할 수 있다.Since at least a portion of the heat dissipation member 281 may be arranged to overlap the first semiconductor chip 250 in the horizontal direction (e.g., X direction), heat generated in the first semiconductor chip 250 can also be absorbed. Heat can be dissipated to the outside. Additionally, adding the heat dissipation member 281 to the semiconductor package 300a may not substantially affect the total height of the semiconductor package 300a. Therefore, the semiconductor package 300a according to an embodiment of the present invention can efficiently use the heat dissipation performance of the heat dissipation member 281, and can also secure the overall integration of the semiconductor package 300a.

제1 반도체 칩(250)은 제1 도전성 포스트들(155P)이 관통하는 방향(예: Z방향)으로 제1 도전성 포스트들(155P)에 중첩되고 제2 반도체 칩(120)에 중첩되지 않도록 배치될 수 있다.The first semiconductor chip 250 is arranged so as to overlap the first conductive posts 155P in a direction through which the first conductive posts 155P pass (e.g., Z direction) and not to overlap the second semiconductor chip 120. It can be.

따라서, 제1 반도체 칩(250)과 제1 재배선 구조물(110) 사이의 전기적 연결 경로는 수평방향 경로를 포함하지 않을 수 있으므로, 제1 반도체 칩(250)과 봉합재(160) 사이의 추가적인 재배선 구조물이 필수적이지 않도록 할 수 있다. 따라서, 본 발명의 일 실시 예에 따른 반도체 패키지(300a)는 방열 부재(281)의 방열성능을 효율적으로 사용할 수 있을 뿐만 아니라, 반도체 패키지(300a)의 총 높이를 줄이기 유리할 수 있고, 설계 자유도도 더 높일 수 있다.Accordingly, the electrical connection path between the first semiconductor chip 250 and the first redistribution structure 110 may not include a horizontal path, so an additional path between the first semiconductor chip 250 and the encapsulant 160 This can ensure that rewiring structures are not essential. Therefore, the semiconductor package 300a according to an embodiment of the present invention can not only efficiently use the heat dissipation performance of the heat dissipation member 281, but can also be advantageous in reducing the total height of the semiconductor package 300a, and also provides design freedom. It can be raised higher.

도 1b는 본 발명의 일 실시 예에 따른 반도체 패키지를 XZ평면으로 절단함에 따른 단면을 나타내고, 도 2b는 도 1b의 반도체 패키지를 도 1b의 좌우측 I2을 따라 XY평면으로 절단함에 따른 단면을 나타낸다.FIG. 1B shows a cross section of the semiconductor package according to an embodiment of the present invention when cut in the

도 1b 및 도 2b를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지(300b)는, 제2 반도체 칩(120)과 방열 부재(281)의 사이에 배치되고 적어도 하나의 제2 재배선층(182)과 적어도 하나의 제2 절연층(181)이 교대로 적층된 제2 재배선 구조물(185)을 더 포함할 수 있다. 반도체 패키지(300b)는 패키지 온 패키지(Package on Package, POP) 구조일 수 있다.1B and 2B, the semiconductor package 300b according to an embodiment of the present invention is disposed between the second semiconductor chip 120 and the heat dissipation member 281 and includes at least one second redistribution layer ( 182) and at least one second insulating layer 181 may be alternately stacked to form a second redistribution structure 185. The semiconductor package 300b may have a package on package (POP) structure.

제2 재배선 구조물(185)은 제1 재배선 구조물(110)과 유사한 방식으로 구현될 수 있으며, 제2 비아들(183)을 포함할 수 있다. 적어도 하나의 제2 재배선층(182)과 제2 비아들(183)의 조합 구조는 전기적 연결 경로일 수 있다. 예를 들어, 적어도 하나의 제2 재배선층(182)의 적층 수(예: 1개)는 적어도 하나의 제1 재배선층(112)의 적층 수(예: 2개)보다 적을 수 있다.The second redistribution structure 185 may be implemented in a similar manner to the first redistribution structure 110 and may include second vias 183. A combination structure of at least one second redistribution layer 182 and second vias 183 may be an electrical connection path. For example, the number of stacks (eg, 1) of at least one second redistribution layer 182 may be less than the number of stacks (eg, 2) of at least one first redistribution layer 112 .

제2 재배선 구조물(185)은 제1 반도체 칩(250)과 제1 재배선 구조물(110) 사이의 전기적 연결 경로에 수평방향 경로를 제공할 수 있다. 따라서, 제1 도전성 포스트들(155P)은 더 압축적(예: 간격 좁아지는 것)으로 배열될 수 있으므로, 본 발명의 일 실시 예에 따른 반도체 패키지(300b)의 총 수평적 면적은 효율적으로 줄어들 수 있다.The second redistribution structure 185 may provide a horizontal path in the electrical connection path between the first semiconductor chip 250 and the first redistribution structure 110. Accordingly, the first conductive posts 155P can be arranged more compactly (e.g., the spacing is narrowed), so the total horizontal area of the semiconductor package 300b according to an embodiment of the present invention is efficiently reduced. You can.

예를 들어, 제1 반도체 칩(250)의 일부분(예: 우측 부분)은 제1 도전성 포스트들(155P)이 관통하는 방향(예: Z방향)으로 제2 반도체 칩(120)의 일부분(예: 좌측 부분)에 중첩될 수 있다. 이는 제2 재배선 구조물(185)이 전기적 연결 경로에 수평방향 경로를 제공함에 따른 구조일 수 있다.For example, a portion (e.g., right portion) of the first semiconductor chip 250 is a portion (e.g., right portion) of the second semiconductor chip 120 in the direction through which the first conductive posts 155P pass (e.g., Z direction). : left part) can be overlapped. This may be a structure in which the second redistribution structure 185 provides a horizontal path to the electrical connection path.

또한, 방열 부재(281)는 제2 재배선 구조물(185)의 상면 상에 부품으로서 배치될 수 있으므로, 방열 부재(281)의 반도체 패키지(300b)에 대한 구조적 호환성을 높일 수 있다. 상기 호환성이 높아질 경우, 방열 부재(281)의 설계 자유도(예: 크기 최적화 용이성, 무게 제한 범위)는 더 높아질 수 있고, 반도체 패키지(300b)의 전반적인 집적도도 더 높아질 수 있다.Additionally, the heat dissipation member 281 may be disposed as a component on the upper surface of the second redistribution structure 185, thereby improving structural compatibility of the heat dissipation member 281 with the semiconductor package 300b. If the compatibility is increased, the design freedom (e.g., ease of size optimization, weight limit range) of the heat dissipation member 281 can be further increased, and the overall integration degree of the semiconductor package 300b can also be increased.

예를 들어, 방열 부재(281)에서 제2 반도체 칩(120)을 마주보는 면(예: 하면)의 크기는 제1 반도체 칩(250)에서 제1 도전성 포스트들(155P)을 마주보는 면(예: 하면)의 크기보다 작을 수 있다. 이는 방열 부재(281)의 설계 자유도가 더 높아짐에 따른 구조일 수 있다.For example, the size of the surface (e.g., lower surface) of the heat dissipation member 281 facing the second semiconductor chip 120 is the size of the surface facing the first conductive posts 155P of the first semiconductor chip 250 ( For example, it may be smaller than the size of the lower surface). This may be a structure in which the design freedom of the heat dissipation member 281 is increased.

도 1a 내지 도 1c를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지(300a, 300b, 300c)는, 제2 반도체 칩(120)과 방열 부재(281)의 사이에 배치되고 봉합재(160)에 의해 봉합되는 제3 반도체 칩(130)을 더 포함할 수 있다.1A to 1C, the semiconductor package 300a, 300b, and 300c according to an embodiment of the present invention is disposed between the second semiconductor chip 120 and the heat dissipation member 281 and has an encapsulant 160. ) may further include a third semiconductor chip 130 sealed.

제3 반도체 칩(130)은 제1 및 제2 반도체 칩(250, 120)과 유사한 방식으로 구현될 수 있다. 예를 들어, 제3 반도체 칩(130)은 몸체부(121)와 유사한 방식으로 구현된 몸체부(131)와, 소자층(122)과 유사한 방식으로 구현된 소자층(132)을 포함할 수 있고, 접속 패드(124)와 유사한 방식으로 구현된 접속 패드(134)를 포함할 수 있고, 범프들(145A)과 유사한 방식으로 구현된 범프들(145B)을 통해 제2 반도체 칩(120)의 상면 상에 실장될 수 있다. 범프들(145B)은 비도전성 필름층(146A)과 유사한 방식으로 구현된 비도전성 필름층(146B)에 의해 둘러싸일 수 있다.The third semiconductor chip 130 may be implemented in a similar manner to the first and second semiconductor chips 250 and 120. For example, the third semiconductor chip 130 may include a body portion 131 implemented in a similar manner to the body portion 121 and a device layer 132 implemented in a similar manner to the device layer 122. and may include a connection pad 134 implemented in a manner similar to the connection pad 124, and may be connected to the second semiconductor chip 120 through bumps 145B implemented in a manner similar to the bumps 145A. It can be mounted on the top surface. The bumps 145B may be surrounded by a non-conductive film layer 146B implemented in a similar manner to the non-conductive film layer 146A.

예를 들어, 제2 반도체 칩(120)은 관통 비아들(125), 중간 유전층(126) 및 접속 패드들(127)을 더 포함할 수 있다. 접속 패드들(127)과 중간 유전층(126)은 제2 반도체 칩(120)의 상면에 배치될 수 있으며, 범프들(145B)은 접속 패드들(127)과 접속 패드들(134)의 사이에 접촉 및 배치될 수 있다. 관통 비아들(125)은 몸체부(121)를 관통할 수 있고, 소자층(122)과 접속 패드들(127)의 사이에 전기적으로 연결될 수 있다. 관통 비아들(125)은 도전성 물질로 이루어질 수 있으며, 예를 들어, 텅스텐(W), 알루미늄(Al), 및 구리(Cu) 중 적어도 하나를 포함할 수 있다.For example, the second semiconductor chip 120 may further include through vias 125, an intermediate dielectric layer 126, and connection pads 127. The connection pads 127 and the intermediate dielectric layer 126 may be disposed on the upper surface of the second semiconductor chip 120, and the bumps 145B may be between the connection pads 127 and the connection pads 134. Can be touched and placed. The through vias 125 may penetrate the body portion 121 and may be electrically connected between the device layer 122 and the connection pads 127 . The through vias 125 may be made of a conductive material, and may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu).

제2 및 제3 반도체 칩들(120, 130)의 조합 구조(3차원 집적회로 구조)의 수평적 크기는 1개의 반도체 칩의 수평적 크기와 유사할 수 있다. 제2 및 제3 반도체 칩들(120, 130)의 소자층들(122, 132)의 총 부피(회로 성능에 대응)와 총 발열은 1개의 반도체 칩의 소자층의 부피와 발열의 약 2배일 수 있다. 따라서, 1개의 반도체 칩과 비교하여, 제2 및 제3 반도체 칩들(120, 130)의 조합 구조의 제1 재배선 구조물(110)에 대한 전기적 연결 경로의 밀집도는 더 높을 수 있고, 제2 및 제3 반도체 칩들(120, 130)의 주변에 방열 부재를 배치하는 공간을 마련하기 더 어려울 수 있다.The horizontal size of the combination structure (3D integrated circuit structure) of the second and third semiconductor chips 120 and 130 may be similar to the horizontal size of one semiconductor chip. The total volume (corresponding to circuit performance) and total heat generation of the device layers 122 and 132 of the second and third semiconductor chips 120 and 130 may be about twice the volume and heat generation of the device layers of one semiconductor chip. there is. Therefore, compared to one semiconductor chip, the density of the electrical connection path for the first redistribution structure 110 of the combination structure of the second and third semiconductor chips 120 and 130 may be higher, and the second and third semiconductor chips 120 and 130 may have a higher density. It may be more difficult to provide a space to place a heat dissipation member around the third semiconductor chips 120 and 130.

방열 부재(281)와 인접 구조들 간의 배치관계에 따라, 방열 부재(281)는 제2 및 제3 반도체 칩들(120, 130)이 서로 수직으로 결합된 구조의 전기적 연결 경로의 높은 밀집도에 별 영향을 받지 않을 수 있으므로, 본 발명의 일 실시 예에 따른 반도체 패키지(300a, 300b, 300c)는 단위 부피 대비 높은 회로 성능을 가지면서도 효율적인 방열성능도 얻을 수 있다.Depending on the arrangement relationship between the heat dissipation member 281 and adjacent structures, the heat dissipation member 281 has little effect on the high density of the electrical connection path of the structure in which the second and third semiconductor chips 120 and 130 are vertically coupled to each other. Since the semiconductor packages 300a, 300b, and 300c according to an embodiment of the present invention may have high circuit performance relative to unit volume, efficient heat dissipation performance can also be obtained.

도 1a 및 도 1b를 참조하면, 제3 반도체 칩(130)은 봉합재(160)가 제3 반도체 칩(130)과 방열 부재(281)의 사이를 가로막지 않게 방열 부재(281)를 향하여 노출될 수 있다. 따라서, 제3 반도체 칩(130)은 열전달물질층(282)이나 제2 재배선 구조물(185)에 접촉할 수 있고, 제2 및 제3 반도체 칩들(120, 130)에서 발생된 열은 방열 부재(281)로 더 효율적으로 전달될 수 있다.1A and 1B, the third semiconductor chip 130 is exposed toward the heat dissipation member 281 so that the encapsulant 160 does not block the space between the third semiconductor chip 130 and the heat dissipation member 281. It can be. Accordingly, the third semiconductor chip 130 may contact the heat transfer material layer 282 or the second redistribution structure 185, and the heat generated from the second and third semiconductor chips 120 and 130 may be transmitted through the heat dissipation member. It can be delivered more efficiently with (281).

도 1c는 본 발명의 일 실시 예에 따른 반도체 패키지를 XZ평면으로 절단함에 따른 단면을 나타내고, 도 2c는 도 1c의 반도체 패키지를 도 1c의 좌우측 I3을 따라 XY평면으로 절단함에 따른 단면을 나타낸다.FIG. 1C shows a cross section of the semiconductor package according to an embodiment of the present invention when cut in the XZ plane, and FIG. 2C shows a cross section of the semiconductor package of FIG. 1C cut in the

도 1c 및 도 2c를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지(300c)는, 제2 반도체 칩(120)과 방열 부재(281)의 사이에 배치되고 제2 반도체 칩(120)과 방열 부재(281)가 서로 마주보는 방향(예: Z방향)으로 연장되고 방열 부재(281)에 전기적으로 연결되는 제2 도전성 포스트들(285)을 더 포함할 수 있다.1C and 2C, the semiconductor package 300c according to an embodiment of the present invention is disposed between the second semiconductor chip 120 and the heat dissipation member 281 and is connected to the second semiconductor chip 120 and the heat dissipation member 281. The heat dissipation member 281 may further include second conductive posts 285 extending in a direction facing each other (eg, Z direction) and electrically connected to the heat dissipation member 281.

제2 도전성 포스트들(285)은 제1 도전성 포스트들(155P)과 유사한 방식으로 구현될 수 있다. 따라서, 제2 도전성 포스트들(285)의 추가 여부는 반도체 패키지(300c)의 전반적인 공정 복잡도에 별 영향을 주지 않을 수 있다.The second conductive posts 285 may be implemented in a similar manner to the first conductive posts 155P. Accordingly, whether or not the second conductive posts 285 are added may not have much effect on the overall process complexity of the semiconductor package 300c.

제2 도전성 포스트들(285)은 열전달물질층(282)과 제3 반도체 칩(130) 사이를 연결시킬 수 있으며, 제2 및 제3 반도체 칩(120, 130)에서 생성된 열이 방열 부재(281)로 전달되는 경로로 사용될 수 있다. 따라서, 제3 반도체 칩(130)이 열전달물질층(282)이나 제2 재배선 구조물(185)에 접촉하지 않더라도, 방열 부재(281)는 제2 및 제3 반도체 칩(120, 130)에서 생성된 열을 효율적으로 흡수할 수 있다.The second conductive posts 285 may connect the heat transfer material layer 282 and the third semiconductor chip 130, and the heat generated from the second and third semiconductor chips 120 and 130 may be transmitted to the heat dissipation member ( 281) can be used as a route. Therefore, even if the third semiconductor chip 130 does not contact the heat transfer material layer 282 or the second redistribution structure 185, the heat dissipation member 281 is created in the second and third semiconductor chips 120 and 130. It can absorb heat efficiently.

예를 들어, 제3 반도체 칩(130)은 제3 반도체 칩(130)의 상면에 배치된 중간 유전층(136)을 포함할 수 있고, 제2 도전성 포스트들(285)은 중간 유전층(136)의 상면에서부터 상측으로 연장될 수 있다. 예를 들어, 제2 도전성 포스트들(285)은 몰드층(139)에 의해 둘러싸일 수 있다. 몰드층(139)은 봉합재(160)가 포함할 수 있는 몰딩 재료(예: EMC)와 동일한 재료를 함유하거나 상기 몰딩 재료의 특성에 가까운 특성을 가지는 절연 재료를 함유할 수 있다.For example, the third semiconductor chip 130 may include a middle dielectric layer 136 disposed on the upper surface of the third semiconductor chip 130, and the second conductive posts 285 may be formed on the middle dielectric layer 136. It may extend from the top to the top. For example, the second conductive posts 285 may be surrounded by the mold layer 139 . The mold layer 139 may contain the same material as the molding material (eg, EMC) that the encapsulant 160 may include, or may contain an insulating material with properties close to those of the molding material.

도 1a 내지 도 1d를 참조하면, 제1 도전성 포스트들(155P)은 봉합재(160)의 중심에서부터 제1 방향(예: -X방향)으로 치우쳐져 배치되고, 제2 및 제3 반도체 칩(120, 130)은 봉합재(160)의 중심에서부터 제1 방향과 다른 제2 방향(예: +X방향)으로 치우쳐져 배치될 수 있다. 이에 따라, 방열 부재(281)의 배치 공간과 제1 반도체 칩(250)의 배치 공간은 서로 효율적으로 분할될 수 있다.Referring to FIGS. 1A to 1D, the first conductive posts 155P are disposed deviated from the center of the encapsulant 160 in a first direction (e.g., -X direction), and the second and third semiconductor chips ( 120 and 130 may be disposed deviated from the center of the sealant 160 in a second direction (eg, +X direction) different from the first direction. Accordingly, the arrangement space of the heat dissipation member 281 and the arrangement space of the first semiconductor chip 250 can be efficiently divided into each other.

도 1a 내지 도 1d를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지(300a, 300b, 300c, 300d)는, 제1 재배선 구조물(110)의 타면(110B) 상에 배치되고 제1 및 제2 반도체 칩(250, 120) 중 적어도 하나에 전기적으로 연결되는 제1 범프들(118)을 더 포함할 수 있다. 예를 들어, 제1 범프들(118)은 볼 또는 기둥 형태를 가질 수 있으며, 주석(Sn) 또는 주석(Sn)을 포함하는 합금(Sn-Ag-Cu)을 함유하는 솔더(solder)를 포함할 수 있다. 제1 범프들(118)은 다른 금속 재료에 비해 비교적 낮은 용융점을 가질 수 있으므로, 열압착 본딩(Thermal Compression Bonding, TCB) 공정이나 리플로우(reflow) 공정에 의해 반도체 패키지(100a, 100b, 100c, 100d)의 UBM 구조들(119)에 연결 및 고착될 수 있다.1A to 1D, semiconductor packages 300a, 300b, 300c, and 300d according to an embodiment of the present invention are disposed on the other surface 110B of the first redistribution structure 110 and have first and It may further include first bumps 118 electrically connected to at least one of the second semiconductor chips 250 and 120. For example, the first bumps 118 may have a ball or pillar shape and include solder containing tin (Sn) or an alloy containing tin (Sn) (Sn-Ag-Cu). can do. Since the first bumps 118 may have a relatively low melting point compared to other metal materials, the semiconductor packages 100a, 100b, 100c, It can be connected and fixed to the UBM structures 119 (100d).

UBM(Under Bump Metallurgy) 구조들(119)은 제1 재배선 구조물(110)의 타면(110B)에 배치될 수 있고, UBM 구조들(164)은 봉합재(160) 또는 제2 재배선 구조물(185)의 상면에 배치될 수 있다. UBM 구조들(117)은 제1 재배선 구조물(110)의 상면(110T)에 배치될 수 있고, SAP(Semi Additive Process)에 의해 형성될 수 있다.UBM (Under Bump Metallurgy) structures 119 may be disposed on the other surface 110B of the first redistribution structure 110, and the UBM structures 164 may be formed on the encapsulant 160 or the second redistribution structure ( 185) can be placed on the upper surface. The UBM structures 117 may be disposed on the top surface 110T of the first redistribution structure 110 and may be formed by a semi-additive process (SAP).

도 1a 내지 도 1d를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지(300a, 300b, 300c, 300d)는, 제1 도전성 포스트들(155P)과 제1 반도체 칩(250)의 사이에 전기적으로 연결되고 제1 도전성 포스트들(155P)이 관통하는 방향(예: Z방향)으로 제1 도전성 포스트들(155P)에 중첩되는 제2 범프들(145C)을 더 포함할 수 있다. 제2 범프들(145C)은 제1 범프들(118)과 유사한 방식으로 구현될 수 있다.1A to 1D, the semiconductor packages 300a, 300b, 300c, and 300d according to an embodiment of the present invention have electrical connections between the first conductive posts 155P and the first semiconductor chip 250. It may further include second bumps 145C that are connected to and overlap the first conductive posts 155P in a direction through which the first conductive posts 155P pass (eg, Z direction). The second bumps 145C may be implemented in a similar manner to the first bumps 118.

도 1a를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지(300a)는 제1 재배선 구조물(110)의 타면(110B)에 배치된 임피던스 요소(170)를 더 포함할 수 있다. 임피던스 요소(170)는 임피던스(커패시턴스, 인덕턴스, 저항)를 제1 내지 제3 반도체 칩(250, 120, 130)으로 제공할 수 있다. 이에 따라, 제1 내지 제3 반도체 칩(250, 120, 130)의 신호의 신뢰성(예: signal integrity, power integrity)은 향상될 수 있다.Referring to FIG. 1A , the semiconductor package 300a according to an embodiment of the present invention may further include an impedance element 170 disposed on the other surface 110B of the first redistribution structure 110. The impedance element 170 may provide impedance (capacitance, inductance, resistance) to the first to third semiconductor chips 250, 120, and 130. Accordingly, the reliability (eg, signal integrity, power integrity) of the signals of the first to third semiconductor chips 250, 120, and 130 can be improved.

예를 들어, 임피던스 요소(170)는 MLCC(Multi-layer Ceramic Capacitor)나 코일 부품일 수 있고, 임피던스 본체(171)와 외부전극들(172)을 포함할 수 있다. 임피던스 요소(170)는 임피던스 본체(171)에서 생성된 임피던스를 외부전극들(172)을 통해 제1 재배선 구조물(110)에 제공할 수 있다.For example, the impedance element 170 may be a multi-layer ceramic capacitor (MLCC) or a coil component, and may include an impedance body 171 and external electrodes 172. The impedance element 170 may provide the impedance generated by the impedance body 171 to the first redistribution structure 110 through the external electrodes 172.

도 1d를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지(300d)는 추가적인 중간 유전층(133)과 추가적인 접속 패드들(134)을 더 포함할 수 있고, 중간 유전층(126)은 서로 적층된 중간 유전층들(126a, 126b)을 포함할 수 있다.Referring to FIG. 1D, the semiconductor package 300d according to an embodiment of the present invention may further include an additional middle dielectric layer 133 and additional connection pads 134, and the middle dielectric layer 126 is stacked with each other. It may include intermediate dielectric layers 126a and 126b.

접속 패드들(127)과 추가적인 접속 패드들(134)은 중간 유전층(126)과 추가적인 중간 유전층(133)에 각각 매립될 수 있으므로, 봉합재(160)로 노출되지 않을 수 있다. 이 구조는 하이브리드 본딩(hybrid bonding)이라고 표현될 수 있다. 예를 들어, 중간 유전층(126)과 추가적인 중간 유전층(133)은 실리콘 산화물(SiO) 실리콘 질화물(SiN), 및 실리콘 탄질화물(SiCN) 중 적어도 하나를 함유할 수 있다.The connection pads 127 and the additional connection pads 134 may be embedded in the middle dielectric layer 126 and the additional middle dielectric layer 133, respectively, and thus may not be exposed by the encapsulant 160. This structure can be expressed as hybrid bonding. For example, middle dielectric layer 126 and additional middle dielectric layer 133 may contain at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN).

예를 들어, 제2 반도체 칩(120)과 제3 반도체 칩(130)이 결합되기 전, 중간 유전층(126)과 추가적인 중간 유전층(133)은 제2 반도체 칩(120)과 제3 반도체 칩(130)에 각각 배치될 수 있다. 이후, 중간 유전층(126)과 추가적인 중간 유전층(133)의 접합에 따라, 제2 반도체 칩(120)과 제3 반도체 칩(130)은 서로 접합될 수 있다. 이때, 접속 패드들(127)과 추가적인 접속 패드들(134)은 경계면(127T, 134B)을 통해 서로 접합될 수 있다.For example, before the second semiconductor chip 120 and the third semiconductor chip 130 are combined, the intermediate dielectric layer 126 and the additional intermediate dielectric layer 133 are connected to the second semiconductor chip 120 and the third semiconductor chip ( 130), respectively. Thereafter, by bonding the middle dielectric layer 126 and the additional middle dielectric layer 133, the second semiconductor chip 120 and the third semiconductor chip 130 may be bonded to each other. At this time, the connection pads 127 and the additional connection pads 134 may be bonded to each other through the boundary surfaces 127T and 134B.

예를 들어, 중간 유전층들(126a, 126b)은 경계면(126T, 133B)를 통해 서로 접합될 수 있다. 관통 비아들(125)의 상면과 경계면(126T, 133B)은 일 평면을 이룰 수 있다. 추가적인 접속 패드들(134)은 소자층(132)의 배선 패턴(WP)에 연결될 수 있다.For example, intermediate dielectric layers 126a and 126b may be bonded to each other through interfaces 126T and 133B. The top surfaces of the through vias 125 and the boundary surfaces 126T and 133B may form one plane. Additional connection pads 134 may be connected to the wiring pattern WP of the device layer 132.

도 3a를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제1 단계(300ab-1)는, 캐리어 기판(510)의 상면 상에 제1 재배선 구조물(110)을 형성하고, 제1 재배선 구조물(110)의 일면(110T) 상에 제1 도전성 포스트들(155P)을 형성하는 것을 포함할 수 있다.Referring to FIG. 3A, in the first step 300ab-1 of the semiconductor package manufacturing method according to an embodiment of the present invention, a first redistribution structure 110 is formed on the upper surface of the carrier substrate 510, This may include forming first conductive posts 155P on one surface 110T of the first redistribution structure 110.

예를 들어, 캐리어 기판(510)은 DCF(Detachable Copper Foil) 캐리어 기판일 수 있다. 예를 들어, 제1 재배선층들(112)과 제1 비아들(113)과 제1 도전성 포스트들(155P)을 형성하는 과정은 포토 레지스트(Photo Resist)와 같은 노광 및 현상이 가능한 재료를 함유하는 구조를 이용할 수 있다.For example, the carrier substrate 510 may be a Detachable Copper Foil (DCF) carrier substrate. For example, the process of forming the first redistribution layers 112, the first vias 113, and the first conductive posts 155P involves using a material that can be exposed and developed, such as photo resist. You can use the structure that does.

도 3b를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제2 단계(300ab-2)는, 제2 및 제3 반도체 칩(120, 130)의 조합 구조를 제1 재배선 구조물(110)의 일면(110T) 상에 배치하는 것을 포함할 수 있다. 또는, 제2 및 제3 반도체 칩(120, 130)은 서로 분리된 상태에서 순차적으로 배치될 수 있다.Referring to FIG. 3B, in the second step 300ab-2 of the semiconductor package manufacturing method according to an embodiment of the present invention, the combined structure of the second and third semiconductor chips 120 and 130 is formed into a first redistribution structure. It may include placement on one side (110T) of (110). Alternatively, the second and third semiconductor chips 120 and 130 may be sequentially arranged while being separated from each other.

도 3c를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제3 단계(300ab-3)는, 제1 재배선 구조물(110)의 일면(110T) 상에서 제1 도전성 포스트들(155P)과 제2 및 제3 반도체 칩(120, 130)이 차지하지 않는 공간에 봉합재(160)를 채울 수 있다. 예를 들어, 봉합재(160)의 상면은 제3 반도체 칩(130)의 상면이 상측으로 노출되도록 연마될 수 있다.Referring to FIG. 3C, in the third step 300ab-3 of the semiconductor package manufacturing method according to an embodiment of the present invention, first conductive posts 155P are formed on one surface 110T of the first redistribution structure 110. ) and the space not occupied by the second and third semiconductor chips 120 and 130 can be filled with the encapsulant 160. For example, the top surface of the encapsulant 160 may be polished so that the top surface of the third semiconductor chip 130 is exposed upward.

도 3d를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제4 단계(300ab-4)는, 캐리어 기판(510)을 제1 재배선 구조물(110)의 타면(110B)으로부터 분리하고 제1 재배선 구조물(110)의 타면(110B)에 UBM 구조들(119)과 제1 범프들(118)을 형성하는 것을 포함할 수 있다.Referring to FIG. 3D, in the fourth step 300ab-4 of the semiconductor package manufacturing method according to an embodiment of the present invention, the carrier substrate 510 is separated from the other surface 110B of the first redistribution structure 110. and forming UBM structures 119 and first bumps 118 on the other surface 110B of the first redistribution structure 110.

도 3e를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제5 단계(300ab-5)는, 봉합재(160)의 상면에 제2 재배선 구조물(185)을 형성하는 것을 포함할 수 있다. 도 1a에서와 같이, 제2 재배선 구조물(185)은 설계에 따라 생략될 수 있다.Referring to FIG. 3E, the fifth step (300ab-5) of the semiconductor package manufacturing method according to an embodiment of the present invention includes forming a second redistribution structure 185 on the upper surface of the encapsulant 160. can do. As in FIG. 1A, the second redistribution structure 185 may be omitted depending on the design.

도 3f를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제6 단계(300ab-6)는, 제1 반도체 칩(250)과 방열 부재(281)을 제2 재배선 구조물(185)의 상면(또는 봉합재(160)의 상면)에 배치하는 것을 포함할 수 있다.Referring to FIG. 3F, the sixth step (300ab-6) of the semiconductor package manufacturing method according to an embodiment of the present invention is to connect the first semiconductor chip 250 and the heat dissipation member 281 to the second redistribution structure 185. ) may include placing on the upper surface (or the upper surface of the sealant 160).

도 4a를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제1 단계(300bc-1)는, 캐리어 기판(510)의 상면 상에 제1 재배선 구조물(110)을 형성하고, 제1 재배선 구조물(110)의 일면(110T) 상에 제1 도전성 포스트들(155P)을 형성하고 제2 및 제3 반도체 칩(120, 130)을 배치하는 것을 포함할 수 있다. 제2 도전성 포스트들(285)은 제3 반도체 칩(130)이 배치되기 전에 형성될 수 있고, 설계에 따라 제3 반도체 칩(130)이 배치된 이후에 형성될 수도 있다.Referring to FIG. 4A, in the first step 300bc-1 of the semiconductor package manufacturing method according to an embodiment of the present invention, a first redistribution structure 110 is formed on the upper surface of the carrier substrate 510, This may include forming first conductive posts 155P on one surface 110T of the first redistribution structure 110 and disposing the second and third semiconductor chips 120 and 130. The second conductive posts 285 may be formed before the third semiconductor chip 130 is disposed, or may be formed after the third semiconductor chip 130 is disposed, depending on the design.

도 4b를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제2 단계(300bc-2)는, 제1 재배선 구조물(110)의 일면(110T) 상에서 제1 도전성 포스트들(155P)과 제2 및 제3 반도체 칩(120, 130)이 차지하지 않는 공간에 봉합재(160)를 채울 수 있다.Referring to FIG. 4B, in the second step 300bc-2 of the semiconductor package manufacturing method according to an embodiment of the present invention, first conductive posts 155P are formed on one surface 110T of the first redistribution structure 110. ) and the space not occupied by the second and third semiconductor chips 120 and 130 can be filled with the encapsulant 160.

도 4c를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제3 단계(300bc-3)는, 봉합재(160)의 상면에 제2 재배선 구조물(185)을 형성하는 것을 포함할 수 있다. 도 1c에서와 같이, 제2 재배선 구조물(185)은 설계에 따라 생략될 수 있다.Referring to FIG. 4C, the third step (300bc-3) of the semiconductor package manufacturing method according to an embodiment of the present invention includes forming a second redistribution structure 185 on the upper surface of the encapsulant 160. can do. As in FIG. 1C, the second redistribution structure 185 may be omitted depending on the design.

도 4d를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제4 단계(300bc-4)는, 제1 반도체 칩(250)과 방열 부재(281)을 제2 재배선 구조물(185)의 상면(또는 봉합재(160)의 상면)에 배치하는 것을 포함할 수 있다.Referring to FIG. 4D, in the fourth step (300bc-4) of the semiconductor package manufacturing method according to an embodiment of the present invention, the first semiconductor chip 250 and the heat dissipation member 281 are connected to the second redistribution structure 185. ) may include placing on the upper surface (or the upper surface of the sealant 160).

도 4e를 참조하면, 본 발명의 일 실시 예에 따른 반도체 패키지 제조 방법의 제5 단계(300bc-5)는, 캐리어 기판(510)을 제1 재배선 구조물(110)의 타면(110B)으로부터 분리하고 제1 재배선 구조물(110)의 타면(110B)에 UBM 구조들(119)과 제1 범프들(118)을 형성하는 것을 포함할 수 있다.Referring to FIG. 4E, in the fifth step (300bc-5) of the semiconductor package manufacturing method according to an embodiment of the present invention, the carrier substrate 510 is separated from the other surface 110B of the first redistribution structure 110. and forming UBM structures 119 and first bumps 118 on the other surface 110B of the first redistribution structure 110.

도 3a 내지 도 4e는 1개의 반도체 패키지를 형성하는 것을 도시하나, 설계에 따라, 복수의 반도체 패키지는 서로 수평적으로 연결된 상태로 일괄적으로 형성될 수 있고, 상기 복수의 반도체 패키지는 수직절단에 의해 서로 분리될 수 있다. 한편, 도 1a 내지 도 2c의 반도체 패키지는 도 3a 내지 도 4e의 반도체 패키지 제조 방법에 의해 제한 해석되지 않는다.3A to 4E show the formation of one semiconductor package, but depending on the design, a plurality of semiconductor packages may be formed in a state of being horizontally connected to each other, and the plurality of semiconductor packages may be cut vertically. can be separated from each other. Meanwhile, the semiconductor package of FIGS. 1A to 2C is not limited by the semiconductor package manufacturing method of FIGS. 3A to 4E.

본 발명은 상술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니며 첨부된 청구범위에 의해 한정하고자 한다. 따라서, 청구범위에 기재된 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 당 기술분야의 통상의 지식을 가진 자에 의해 다양한 형태의 치환, 변형 및 변경이 가능할 것이며, 이 또한 본 발명의 범위에 속한다고 할 것이다.The present invention is not limited by the above-described embodiments and attached drawings, but is intended to be limited by the appended claims. Accordingly, various forms of substitution, modification, and change may be made by those skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and this also falls within the scope of the present invention. something to do.

110: 제1 재배선 구조물
111: 제1 절연층
112: 제1 재배선층
118: 제1 범프
120: 제2 반도체 칩
130: 제3 반도체 칩
145C: 제2 범프
155P: 제1 도전성 포스트들
160: 봉합재
181: 제2 절연층
182: 제2 재배선층
185: 제2 재배선 구조물
250: 제1 반도체 칩
281: 방열 부재
285: 제2 도전성 포스트들
300a, 300b, 300c, 300d: 반도체 패키지110: First redistribution structure
111: first insulating layer
112: first redistribution layer
118: first bump
120: Second semiconductor chip
130: Third semiconductor chip
145C: 2nd bump
155P: First conductive posts
160: suture material
181: second insulating layer
182: second redistribution layer
185: Second redistribution structure
250: first semiconductor chip
281: Heat dissipation member
285: Second conductive posts
300a, 300b, 300c, 300d: semiconductor package

Claims (10)

적어도 하나의 제1 재배선층과 적어도 하나의 제1 절연층이 교대로 적층된 제1 재배선 구조물;
상기 제1 재배선 구조물의 일면 상에 배치된 제1 반도체 칩;
상기 제1 재배선 구조물과 상기 제1 반도체 칩의 사이에 배치된 봉합재;
상기 제1 재배선 구조물과 상기 제1 반도체 칩을 전기적으로 연결하고 상기 봉합재를 관통하는 제1 도전성 포스트들;
적어도 일부분이 상기 제1 도전성 포스트들이 관통하는 방향에 수직인 방향으로 상기 제1 반도체 칩에 중첩되도록 배치되는 방열 부재; 및
적어도 일부분이 상기 제1 재배선 구조물과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제2 반도체 칩; 을 포함하고,
상기 제1 반도체 칩은 상기 제1 도전성 포스트들이 관통하는 방향으로 상기 제1 도전성 포스트들에 중첩되고 상기 제2 반도체 칩에 중첩되지 않도록 배치되는 반도체 패키지.
a first redistribution structure in which at least one first redistribution layer and at least one first insulating layer are alternately stacked;
a first semiconductor chip disposed on one surface of the first redistribution structure;
an encapsulant disposed between the first redistribution structure and the first semiconductor chip;
first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip and penetrating the encapsulant;
a heat dissipation member disposed so that at least a portion thereof overlaps the first semiconductor chip in a direction perpendicular to the direction through which the first conductive posts pass; and
a second semiconductor chip, at least a portion of which is disposed between the first redistribution structure and the heat dissipation member and sealed by the encapsulant; Including,
A semiconductor package wherein the first semiconductor chip overlaps the first conductive posts in a direction through which the first conductive posts pass and is not overlapped with the second semiconductor chip.
 적어도 하나의 제1 재배선층과 적어도 하나의 제1 절연층이 교대로 적층된 제1 재배선 구조물;
상기 제1 재배선 구조물의 일면 상에 배치된 제1 반도체 칩;
상기 제1 재배선 구조물과 상기 제1 반도체 칩의 사이에 배치된 봉합재;
상기 제1 재배선 구조물과 상기 제1 반도체 칩을 전기적으로 연결하고 상기 봉합재를 관통하는 제1 도전성 포스트들;
적어도 일부분이 상기 제1 도전성 포스트들이 관통하는 방향에 수직인 방향으로 상기 제1 반도체 칩에 중첩되도록 배치되는 방열 부재;
적어도 일부분이 상기 제1 재배선 구조물과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제2 반도체 칩; 및
상기 제2 반도체 칩과 상기 방열 부재의 사이에 배치되고 적어도 하나의 제2 재배선층과 적어도 하나의 제2 절연층이 교대로 적층된 제2 재배선 구조물; 을 포함하는 반도체 패키지.
a first redistribution structure in which at least one first redistribution layer and at least one first insulating layer are alternately stacked;
a first semiconductor chip disposed on one surface of the first redistribution structure;
an encapsulant disposed between the first redistribution structure and the first semiconductor chip;
first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip and penetrating the encapsulant;
a heat dissipation member disposed so that at least a portion thereof overlaps the first semiconductor chip in a direction perpendicular to the direction through which the first conductive posts pass;
a second semiconductor chip, at least a portion of which is disposed between the first redistribution structure and the heat dissipation member and sealed by the encapsulant; and
a second redistribution structure disposed between the second semiconductor chip and the heat dissipation member and including at least one second redistribution layer and at least one second insulating layer alternately stacked; A semiconductor package containing a.
 적어도 하나의 제1 재배선층과 적어도 하나의 제1 절연층이 교대로 적층된 제1 재배선 구조물;
상기 제1 재배선 구조물의 일면 상에 배치된 제1 반도체 칩;
상기 제1 재배선 구조물과 상기 제1 반도체 칩의 사이에 배치된 봉합재;
상기 제1 재배선 구조물과 상기 제1 반도체 칩을 전기적으로 연결하고 상기 봉합재를 관통하는 제1 도전성 포스트들;
적어도 일부분이 상기 제1 도전성 포스트들이 관통하는 방향에 수직인 방향으로 상기 제1 반도체 칩에 중첩되도록 배치되는 방열 부재;
적어도 일부분이 상기 제1 재배선 구조물과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제2 반도체 칩;
상기 제2 반도체 칩과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제3 반도체 칩; 및
상기 제1 재배선 구조물의 타면 상에 배치되고 상기 제1 및 제2 반도체 칩 중 적어도 하나에 전기적으로 연결되는 제1 범프들; 을 포함하고,
상기 제1 및 제2 반도체 칩은 상기 제1 재배선 구조물을 통해 서로 전기적으로 연결되고,
상기 제1 도전성 포스트들은 상기 봉합재의 중심에서부터 제1 방향으로 치우쳐져 배치되고,
상기 제2 및 제3 반도체 칩은 상기 봉합재의 중심에서부터 상기 제1 방향과 다른 제2 방향으로 치우쳐져 배치되는 반도체 패키지.
a first redistribution structure in which at least one first redistribution layer and at least one first insulating layer are alternately stacked;
a first semiconductor chip disposed on one surface of the first redistribution structure;
an encapsulant disposed between the first redistribution structure and the first semiconductor chip;
first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip and penetrating the encapsulant;
a heat dissipation member disposed so that at least a portion thereof overlaps the first semiconductor chip in a direction perpendicular to the direction through which the first conductive posts pass;
a second semiconductor chip, at least a portion of which is disposed between the first redistribution structure and the heat dissipation member and sealed by the encapsulant;
a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member and sealed by the encapsulant; and
first bumps disposed on the other side of the first redistribution structure and electrically connected to at least one of the first and second semiconductor chips; Including,
The first and second semiconductor chips are electrically connected to each other through the first redistribution structure,
The first conductive posts are arranged deviated from the center of the encapsulant in a first direction,
A semiconductor package wherein the second and third semiconductor chips are disposed deviated from the center of the encapsulant in a second direction different from the first direction.
 제1항 또는 제2항에 있어서,
상기 제2 반도체 칩과 상기 방열 부재의 사이에 배치되고 상기 봉합재에 의해 봉합되는 제3 반도체 칩을 더 포함하는 반도체 패키지.
According to claim 1 or 2,
A semiconductor package further comprising a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member and sealed by the encapsulant.
 제4항에 있어서,
상기 제3 반도체 칩은 상기 봉합재가 상기 제3 반도체 칩과 상기 방열 부재의 사이를 가로막지 않게 상기 방열 부재를 향하여 노출되는 반도체 패키지.
According to paragraph 4,
The third semiconductor chip is exposed toward the heat dissipation member so that the encapsulant does not block the space between the third semiconductor chip and the heat dissipation member.
 제1항 또는 제2항에 있어서,
상기 제1 도전성 포스트들은 상기 봉합재의 중심에서부터 제1 방향으로 치우쳐져 배치되고,
상기 제2 반도체 칩은 상기 봉합재의 중심에서부터 상기 제1 방향과 다른 제2 방향으로 치우쳐져 배치되는 반도체 패키지.
According to claim 1 or 2,
The first conductive posts are arranged deviated from the center of the encapsulant in a first direction,
The second semiconductor chip is disposed deviated from the center of the encapsulant in a second direction different from the first direction.
 제1항 또는 제2항에 있어서,
상기 제1 재배선 구조물의 타면 상에 배치되고 상기 제1 및 제2 반도체 칩 중 적어도 하나에 전기적으로 연결되는 제1 범프들을 더 포함하고,
상기 제1 및 제2 반도체 칩은 상기 제1 재배선 구조물을 통해 서로 전기적으로 연결되는 반도체 패키지.
According to claim 1 or 2,
Further comprising first bumps disposed on the other side of the first redistribution structure and electrically connected to at least one of the first and second semiconductor chips,
The first and second semiconductor chips are electrically connected to each other through the first redistribution structure.
 제1항 내지 제3항 중 어느 한 항에 있어서,
상기 제1 도전성 포스트들과 상기 제1 반도체 칩의 사이에 전기적으로 연결되고 상기 제1 도전성 포스트들이 관통하는 방향으로 상기 제1 도전성 포스트들에 중첩되는 제2 범프들을 더 포함하는 반도체 패키지.
According to any one of claims 1 to 3,
A semiconductor package electrically connected between the first conductive posts and the first semiconductor chip and further comprising second bumps overlapping the first conductive posts in a direction through which the first conductive posts pass.
 제1항 내지 제3항 중 어느 한 항에 있어서,
상기 제2 반도체 칩과 상기 방열 부재의 사이에 배치되고 상기 제2 반도체 칩과 상기 방열 부재가 서로 마주보는 방향으로 연장되고 상기 방열 부재에 전기적으로 연결되는 제2 도전성 포스트들을 더 포함하는 반도체 패키지.
According to any one of claims 1 to 3,
A semiconductor package further comprising second conductive posts disposed between the second semiconductor chip and the heat dissipation member, extending in a direction in which the second semiconductor chip and the heat dissipation member face each other, and electrically connected to the heat dissipation member.
 제2항 또는 제3항에 있어서,
상기 제1 반도체 칩의 일부분은 상기 제1 도전성 포스트들이 관통하는 방향으로 상기 제2 반도체 칩에 중첩되고,
상기 방열 부재에서 상기 제2 반도체 칩을 마주보는 면의 크기는 상기 제1 반도체 칩에서 상기 제1 도전성 포스트들을 마주보는 면의 크기보다 작은 반도체 패키지.According to paragraph 2 or 3,
A portion of the first semiconductor chip overlaps the second semiconductor chip in a direction through which the first conductive posts pass,
A semiconductor package in which a size of a surface of the heat dissipation member facing the second semiconductor chip is smaller than a size of a surface of the first semiconductor chip facing the first conductive posts.
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