KR20240051003A - Display device and method for manufacturing the same - Google Patents

Abstract

A display device according to an embodiment includes a substrate including a sub-display area including a transparent area and a main display area other than the sub-display area, a thin film transistor layer disposed on the main display area of the substrate and the sub-display area, A light emitting device layer disposed on the thin film transistor layer, a thin film encapsulation disposed on the light emitting device layer, a first through hole and a second through hole disposed on the transmission area and passing through the transmission area and overlapping each other, A first planar layer is disposed below the substrate, is disposed in the main display area and the transmission area, and fills the second through hole, and is disposed on the thin film encapsulation layer, and is disposed in the main display area and the transmission area. and a second planarizing layer that fills the first through hole, and the first and second planarizing layers contact each other in the transmission area.

Description

Display device and method for manufacturing the same}

The present invention relates to a display device and a manufacturing method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions. A display device may include a display panel including a plurality of pixels connected to scan lines, data lines, and power lines to display an image. In addition, the display device includes an image sensor to capture an image of the front, a proximity sensor to detect whether the user is close to the front of the display device, and a sensor to detect the illuminance of the front of the display device. It may include various optical devices, such as an illuminance sensor for recognizing the user's iris and an iris sensor for recognizing the user's iris. The optical device may be placed in a hole disposed in the front of the display device that does not overlap the display panel.

As display devices are applied to various electronic devices, display devices with various designs are required. For example, in the case of smartphones, there is a demand for a display device that can expand the display area by eliminating a hole disposed on the front of the display device. In this case, the optical device that was placed in the hole located in front of the display device may be placed overlapping the display panel. However, when optical devices are arranged to overlap the display panel, they are obscured by the pixels, scan lines, data lines, and power lines of the display panel, so light incident on the optical device may be reduced. Because of this, the functionality of the optical device may deteriorate.

The problem to be solved by the present invention is to provide a display device and a manufacturing method thereof that can prevent light incident on the optical device from being reduced and improve the encapsulation characteristics of the display device even when the optical device is disposed overlapping the display panel. It is done.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment to solve the above problem includes a substrate including a sub-display area including a transparent area and a main display area other than the sub-display area, and a main display area of the substrate and the sub-display area. A thin film transistor layer disposed, a light emitting device layer disposed on the thin film transistor layer, a thin film encapsulation disposed on the light emitting device layer, and first through holes disposed on the transmission area and passing through the transmission area and overlapping each other. and a second through hole, disposed below the substrate, disposed in the main display area and the transmission area, and filling the second through hole, and disposed on the thin film encapsulation layer, the main display area. and a second planarizing layer disposed in the transmission area and filling the first through hole, wherein the first planarization layer and the second planarization layer may be in contact with each other in the transmission area.

The first through hole may penetrate the thin film transistor layer disposed in the sub-display area and a portion of the substrate, and the second through hole may penetrate a remaining portion of the substrate.

The substrate includes a first substrate disposed on the first planarization layer, a first barrier layer disposed on the first substrate, a second substrate disposed on the first barrier layer, and a first substrate disposed on the second substrate. and a second barrier layer, wherein the first through hole penetrates the first barrier layer, the second substrate, and the second barrier layer, and the second through hole may penetrate the first substrate. .

The first planarization layer may include a protrusion that protrudes toward the second planarization layer through the second through hole, and the width of the protrusion may gradually decrease as it becomes adjacent to the second planarization layer.

The width of the second through hole may gradually increase from the top surface of the first substrate to the bottom surface of the first substrate.

It may further include at least one optical device overlapping the transmission area, and the at least one optical device may overlap the first through hole and the second through hole.

The thin film transistor layer, the light emitting device layer, and the thin film encapsulation layer may not overlap with the transmission area.

The light emitting device layer includes a pixel electrode disposed on the thin film transistor layer, a light emitting layer disposed on the pixel electrode, and a common electrode disposed on the light emitting layer, and the thin film encapsulation layer is disposed on the common electrode. The light emitting device layer can be sealed.

It may further include an inorganic insulating layer disposed on the thin film transistor layer and covering an edge of the pixel electrode, and a bank structure disposed on the inorganic insulating layer and including openings exposing the pixel electrode.

The bank structure includes a first bank layer disposed on the inorganic insulating layer, and a second bank layer disposed on the first bank layer and including a tip protruding from a side wall of the opening than the first bank layer. can do.

The light emitting layer and the common electrode may contact a sidewall of the first bank layer below the tip of the second bank layer.

The bank structure may further include a third bank layer disposed on the second bank layer.

It may further include an organic pattern disposed on the third bank layer surrounding the opening and including the same material as the light-emitting layer, and an electrode pattern disposed on the organic pattern and including the same material as the common electrode. there is.

The thin film encapsulation layer includes a first encapsulation layer, a second encapsulation layer disposed on the first encapsulation layer, and a third encapsulation layer disposed on the second encapsulation layer. 3 The encapsulation layers may be in contact with each other in the area surrounding the opening.

The first encapsulation layer and the third encapsulation layer may contact each other in an area surrounding the transparent area.

Additionally, a display device according to an embodiment may include a substrate, a thin film transistor layer disposed on the substrate, a light emitting device layer disposed on the thin film transistor layer, a thin film encapsulation layer disposed on the light emitting device layer, the substrate, and the light emitting device layer. A first through hole and a second through hole that penetrate the thin film transistor layer and overlap each other, a first planar layer disposed under the substrate and filling the second through hole, and disposed on the thin film encapsulation layer, 1. It includes a second planarization layer that fills a through hole and is in contact with the first planarization layer, and the thin film transistor layer, the light emitting device layer, and the thin film encapsulation layer do not overlap with the first through hole and the second through hole. can do.

The light emitting device layer includes a pixel electrode disposed on the thin film transistor layer, a light emitting layer disposed on the pixel electrode, and a common electrode disposed on the light emitting layer, and the thin film encapsulation layer is disposed on the common electrode. The light emitting device layer can be sealed.

It may further include an inorganic insulating layer disposed on the thin film transistor layer and covering an edge of the pixel electrode, and a bank structure disposed on the inorganic insulating layer and including openings exposing the pixel electrode.

The thin film encapsulation layer may include a first encapsulation layer, a second encapsulation layer disposed on the first encapsulation layer and filling the opening, and a third encapsulation layer disposed on the second encapsulation layer.

The top surface of the second encapsulation layer may protrude in a direction toward the first flattening layer rather than the top surface of the first encapsulation layer.

The top surface of the second encapsulation layer may be aligned with the top surface of the first encapsulation layer.

The top surface of the first encapsulation layer may protrude in a direction toward the first flattening layer rather than the top surface of the second encapsulation layer.

The upper surface of the second flattening layer may be aligned with the uppermost surface of the third encapsulating layer.

In addition, a method of manufacturing a display device according to an embodiment includes forming a substrate on a mother substrate, forming a thin film transistor layer on the substrate, forming a pixel electrode on the thin film transistor layer and a sacrificial layer on the pixel electrode. forming, sequentially stacking an inorganic insulating material layer, a first bank material layer, and a second bank material layer on the pixel electrode, forming a third bank layer on the second bank material layer, and 3. Performing a first etching process using the bank layer as an etch mask to form an opening overlapping the pixel electrode and a first through hole exposing the substrate, using the third bank layer as an etch mask. Performing a second etching process to form a first bank layer and a second bank layer having a tip protruding from the first bank layer, forming a light emitting layer and a common electrode on the pixel electrode, the common electrode sequentially forming a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer on the third encapsulation layer, forming a hard mask layer on the third encapsulation layer, and performing a third etching process through the first through hole. Etching the exposed portion of the substrate, forming a first flat layer on the substrate and the third encapsulation layer, removing the mother substrate and performing a fourth etching process to etch the remainder of the substrate. It may include forming a second through hole overlapping the first through hole, and forming a second flat layer on the lower surface of the substrate.

The method further includes removing the sacrificial layer after the first etching process, and the first etching process may be a dry etching process.

The second etching process is a wet etching process, and the first bank material layer may have an etching rate faster than the second bank material layer.

The light emitting layer and the common electrode may be disconnected at the opening by the tip of the second bank layer.

The hard mask layer may be formed in an area other than the area where the first through hole is formed, and may be removed after the third etching process is performed.

The substrate is formed by sequentially forming a first substrate, a first barrier layer, a second substrate, and a second barrier layer on the mother substrate, and the first through hole is formed by forming the second through hole in the first etching process. The barrier layer is etched and the second substrate and the first barrier layer are etched in the third etching process, and the second through hole is formed by etching the first substrate in the fourth etching process. can be formed.

The first planarization layer may be formed on the encapsulation layer and may fill the first through hole, and the second planarization layer may be formed on the lower surface of the first substrate and may be formed to fill the second through hole. .

Specific details of other embodiments are included in the detailed description and drawings.

A display device according to an embodiment may improve the transmittance of light incident on the optical devices by forming a transmission area including through holes in a sub-display area that overlaps the optical devices.

Additionally, the thin film encapsulation layer independently encapsulates each light emitting area, thereby improving the encapsulation characteristics of the light emitting devices.

Effects according to the embodiments are not limited to the content exemplified above, and further various effects are included in the present specification.

1 is a perspective view showing a display device according to an embodiment.
Figure 2 is an exploded perspective view showing a display device according to an embodiment.
FIG. 3 is a plan view showing a display panel, a display circuit board, a display driving circuit, and a touch driving circuit according to an embodiment.
FIG. 4 is a plan view showing a display panel, a display circuit board, a display driving circuit, and a touch driving circuit according to another embodiment.
Figure 5 is a plan view showing a partial area of a display panel according to an embodiment.
Figure 6 is a cross-sectional view taken along line II' of Figure 5.
FIG. 7 is an enlarged view of a partial area of FIG. 6.
8 to 22 are cross-sectional views sequentially showing the manufacturing process of a display device according to an embodiment.
Figure 23 is a cross-sectional view showing a display device according to another embodiment.
Figure 24 is a cross-sectional view showing a display device according to another embodiment.
Figure 25 is a cross-sectional view showing a display device according to another embodiment.
Figure 26 is a cross-sectional view showing a display device according to another embodiment.
Figure 27 is a cross-sectional view showing a display device according to another embodiment.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is placed directly on top of or in between. Similarly, the terms “Below,” “Left,” and “Right” refer to all elements that are directly adjacent to other elements or have intervening layers or other materials. Includes. Like reference numerals refer to like elements throughout the specification.

Although first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be a second component within the technical spirit of the present invention.

Hereinafter, embodiments will be described with reference to the attached drawings.

1 is a perspective view showing a display device according to an embodiment. Figure 2 is an exploded perspective view showing a display device according to an embodiment.

Referring to FIGS. 1 and 2 , the display device 10 according to an embodiment may be used in a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notebook, or an electronic device. It can be applied to portable electronic devices such as books, PMP (portable multimedia player), navigation, UMPC (Ultra Mobile PC), etc. Alternatively, the display device 10 according to one embodiment may be applied as a display unit of a television, laptop, monitor, billboard, or Internet of Things (IOT). Alternatively, the display device 10 according to one embodiment may be mounted on a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). It can be applied. Alternatively, the display device 10 according to one embodiment may be a dashboard of a car, a center fascia of a car, a Center Information Display (CID) placed on the dashboard of a car, or a room mirror display instead of a side mirror of a car. It can be applied to a display placed on the back of the front seat (room mirror display), or as entertainment for the back seat of a car.

In this specification, the first direction (X-axis direction) may be the short side direction of the display device 10, for example, the horizontal direction of the display device 10. The second direction (Y-axis direction) may be the long side direction of the display device 10, for example, the vertical direction of the display device 10. The third direction (Z-axis direction) may be the thickness direction of the display device 10.

The display device 10 may have a planar shape similar to a square. For example, the display device 10 may have a planar shape similar to a square having a short side in the first direction (X-axis direction) and a long side in the second direction (Y-axis direction) as shown in FIG. 1 . The corner where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) meet may be rounded to have a predetermined curvature or may be formed at a right angle. The planar shape of the display device 10 is not limited to a square, and may be similar to other polygons, circles, or ovals.

The display device 10 can be formed flat. Alternatively, the display device 10 may be formed so that two sides facing each other are bent. For example, the display device 10 may be formed to be bent on the left and right sides. Alternatively, the display device 10 may be formed so that all of the top, bottom, left, and right sides are curved.

The display device 10 according to one embodiment includes a cover window 100, a display panel 300, a display circuit board 310, a display driving circuit 320, a bracket 600, and a main circuit board 700. , optical devices 740, 750, 760, 770, and a lower cover 900.

The cover window 100 may be disposed on the upper part of the display panel 300 to cover the front surface of the display panel 300 . Because of this, the cover window 100 can function to protect the front of the display panel 300.

The display panel 300 may be disposed below the cover window 100 . The display panel 300 may include a display area (DA) including a main display area (MDA) and a sub display area (SDA). The main display area (MDA) may occupy most of the display area (DA). The sub display area SDA may be disposed on one side of the main display area MDA, for example, above the main display area MDA as shown in FIG. 2, but is not limited to this.

The main display area (MDA) does not include a transmission area that transmits light, and may only include a pixel area that includes pixels for displaying an image. In comparison, the sub-display area SDA may include both a transmission area that transmits light and a pixel area that includes pixels for displaying an image. Therefore, the light transmittance of the sub display area SDA may be higher than the light transmittance of the main display area MDA.

The sub-display area SDA may overlap the optical devices 740, 750, 760, and 770 in the third direction (Z-axis direction). Therefore, the light passing through the sub-display area SDA can be incident on the optical devices 740, 750, 760, and 770, so that each of the optical devices 740, 750, 760, and 770 is connected to the display panel 300. Even though it is arranged to overlap, light incident from the front of the display device 10 can be detected.

The display panel 300 may be a light emitting display panel including a light emitting element. For example, the display panel 300 includes an organic light emitting display panel using an organic light emitting diode including an organic light emitting layer, a micro light emitting diode display panel using a micro LED, and a quantum dot light emitting layer. It may be a quantum dot light emitting display panel using a quantum dot light emitting diode, or an inorganic light emitting display panel using an inorganic light emitting device including an inorganic semiconductor. Hereinafter, the description will focus on the fact that the display panel 300 is an organic light emitting display panel.

A display circuit board 310 and a display driving circuit 320 may be attached to one side of the display panel 300. The display circuit board 310 is a flexible printed circuit board that can be bent, a rigid printed circuit board that is hard and does not bend easily, or a rigid printed circuit board and a flexible printed circuit board. It can be a composite printed circuit board that contains all of them.

The display driving circuit 320 may receive control signals and power voltages through the display circuit board 310 and generate and output signals and voltages for driving the display panel 300 . The display driving circuit 320 may be formed as an integrated circuit (IC) and attached to the display panel 300 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic method. It is not limited. For example, the display driving circuit 320 may be attached to the display circuit board 310 .

A touch driving circuit 330 may be disposed on the display circuit board 310. The touch driving circuit 330 may be formed as an integrated circuit and attached to the upper surface of the display circuit board 310. The touch driving circuit 330 may be electrically connected to touch electrodes of the touch sensor layer of the display panel 300 through the display circuit board 310 . The touch driving circuit 330 may output a touch driving signal to the touch electrodes and detect the voltage charged in the capacitance of the touch electrodes.

The touch driving circuit 330 generates touch data according to changes in the electrical signal detected at each of the touch electrodes and transmits it to the main processor 710, and the main processor 710 analyzes the touch data to determine the touch that occurred. Coordinates can be calculated. Touch may include contact touch and proximity touch. Contact touch refers to direct contact of an object such as a person's finger or a pen to a cover window disposed on the sensor electrode layer. A close touch refers to an object, such as a person's finger or a pen, being placed close to the cover window, such as hovering.

Additionally, a power supply unit for supplying display driving voltages for driving the display driving circuit 320 may be additionally disposed on the display circuit board 310 .

A bracket 600 may be disposed below the display panel 300. The bracket 600 may include plastic, metal, or both plastic and metal. The bracket 600 includes a first camera hole (CMH1) into which the first camera sensor 720 is inserted, a battery hole (BH) into which the battery is placed, and a cable hole through which the cable 314 connected to the display circuit board 310 passes. (CAH) and a light transmission hole (SH) in which the optical devices 740, 750, 760, and 770 are disposed may be formed. Alternatively, the bracket 600 may not include the light transmission hole SH but may be formed not to overlap the sub-display area SDA of the display panel 300 .

A main circuit board 700 and a battery 790 may be placed below the bracket 600. The main circuit board 700 may be a printed circuit board or a flexible printed circuit board.

The main circuit board 700 may include a main processor 710, a first camera sensor 720, a main connector 730, and optical devices 740, 750, 760, and 770. The optical devices 740, 750, 760, and 770 may include a proximity sensor 740, an illumination sensor 750, an iris sensor 760, and a second camera sensor 770.

The first camera sensor 720 is disposed on both the upper and lower surfaces of the main circuit board 700, the main processor 710 is disposed on the upper surface of the main circuit board 700, and the main connector 730 is disposed on the main circuit board 700. It may be placed on the lower surface of (700). The proximity sensor 740, the illuminance sensor 750, the iris sensor 760, and the second camera sensor 770 may be disposed on the top of the main circuit board 700.

The main processor 710 can control all functions of the display device 10. For example, the main processor 710 may output digital video data to the display driving circuit 320 through the display circuit board 310 so that the display panel 300 displays an image. Additionally, the main processor 710 may receive touch data from the touch driving circuit 330, determine the user's touch coordinates, and then execute the application indicated by the icon displayed at the user's touch coordinates. In addition, the main processor 710 converts the first image data input from the first camera sensor 720 into digital video data and outputs it to the display driving circuit 320 through the display circuit board 310, thereby converting the first image data input from the first camera sensor 720 into digital video data. An image captured by the sensor 720 may be displayed on the display panel 300. In addition, the main processor 710 controls the display device 10 according to sensor signals input from the proximity sensor 740, the illuminance sensor 750, the iris sensor 760, and the second camera sensor 770. You can.

The main processor 710 may determine whether an object is located close to the front of the display device 10 according to the proximity sensor signal input from the proximity sensor 740. When an object is located close to the front of the display device 10 in a call mode in which the user uses the display device 10 to make a call with the other party, the main processor 710 coordinates the touch even if a touch is executed by the user. The application indicated by the icon displayed may not be executed.

The main processor 710 may determine the brightness of the front of the display device 10 according to the illuminance sensor signal input from the illuminance sensor 750. The main processor 710 may adjust the brightness of the image displayed by the display panel 300 according to the brightness of the front of the display device 10.

The main processor 710 may determine whether the user's iris image is the same as the iris image previously stored in the memory according to the iris sensor signal input from the iris sensor 760. If the user's iris image is the same as the iris image previously stored in the memory, the main processor 710 may unlock the display device 10 and display the home screen on the display panel 300.

The main processor 710 may generate digital video data according to the second image data input from the second camera sensor 770. The main processor 710 outputs digital video data to the display driving circuit 320 through the display circuit board 310, thereby displaying the image captured by the second camera sensor 770 on the display panel 300. there is.

The first camera sensor 720 processes image frames such as still images or moving images obtained by the image sensor and outputs them to the main processor 710. The first camera sensor 720 may be a CMOS image sensor or a CCD sensor. The first camera sensor 720 may be exposed to the lower surface of the lower cover 900 through the second camera hole CMH2, and therefore may capture objects or backgrounds placed under the display device 10.

The cable 314 passing through the cable hole (CAH) of the bracket 600 may be connected to the main connector 730. Because of this, the main circuit board 700 may be electrically connected to the display circuit board 310.

The proximity sensor 740 is a sensor that detects whether an object is located close to the front of the display device 10. The proximity sensor 740 may include a light source that outputs light and a light receiver that receives light reflected by an object. The proximity sensor 740 may determine whether an object located close to the front of the display device 10 exists based on the amount of light reflected by the object. The proximity sensor 740 is disposed to overlap the light transmission hole (SH), the sub-display area (SDA) of the display panel 300, and the cover window 100 in the third direction (Z-axis direction), so that the display device ( 10) A proximity sensor signal can be generated and output to the main processor 710 depending on whether an object is located close to the front of the screen.

The illuminance sensor 750 is a sensor for detecting the brightness of the front of the display device 10. The illuminance sensor 750 may include a resistor whose resistance value changes depending on the brightness of incident light. The illuminance sensor 750 may determine the brightness of the front of the display device 10 according to the resistance value of the resistor. The illuminance sensor 750 is disposed to overlap the light transmission hole SH, the sub-display area SDA of the display panel 300, and the cover window 100 in the third direction (Z-axis direction), so that the display device ( 10) An illuminance sensor signal can be generated according to the brightness of the front surface and output to the main processor 710.

The iris sensor 760 is a sensor that detects whether an image taken of the user's iris is the same as an iris image previously stored in memory. The iris sensor 760 is disposed to overlap the light transmission hole (SH), the sub-display area (SDA) of the display panel 300, and the cover window 100 in the third direction (Z-axis direction), so that the display device ( 10) The user's iris placed at the top can be photographed. The iris sensor 760 may generate an iris sensor signal depending on whether the user's iris image is the same as the iris image previously stored in the memory and output the signal to the main processor 710.

The second camera sensor 770 processes image frames such as still images or moving images obtained by the image sensor and outputs them to the main processor 710. The second camera sensor 770 may be a CMOS image sensor or a CCD sensor. The number of pixels of the second camera sensor 770 may be smaller than that of the first camera sensor 720, and the size of the second camera sensor 770 may be smaller than the size of the first camera sensor 720. The second camera sensor 770 is disposed to overlap the light transmission hole SH, the sub-display area SDA of the display panel 300, and the cover window 100 in the third direction (Z-axis direction), so that the display Objects or backgrounds placed on top of the device 10 can be photographed.

The battery 790 may be arranged so as not to overlap the main circuit board 700 in the third direction (Z-axis direction). The battery 790 may overlap the battery hole (BH) of the bracket 600.

In addition, the main circuit board 700 may be further equipped with a mobile communication module capable of transmitting and receiving wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network. Wireless signals may include voice signals, video call signals, or various types of data resulting from sending and receiving text/multimedia messages.

The lower cover 900 may be placed below the main circuit board 700 and the battery 790. The lower cover 900 may be fastened to the bracket 600 and fixed. The lower cover 900 may form the lower surface of the display device 10 . The lower cover 900 may include plastic, metal, or both plastic and metal.

A second camera hole (CMH2) exposing the lower surface of the first camera sensor 720 may be formed in the lower cover 900. The position of the first camera sensor 720 and the positions of the first and second camera holes CMH1 and CMH2 corresponding to the first camera sensor 720 are not limited to the embodiment shown in FIG. 2.

FIG. 3 is a plan view showing a display panel, a display circuit board, a display driving circuit, and a touch driving circuit according to an embodiment. FIG. 4 is a plan view showing a display panel, a display circuit board, a display driving circuit, and a touch driving circuit according to another embodiment.

Referring to FIG. 3 , the display panel 300 may be a rigid display panel that is rigid and therefore not easily bent, or a flexible display panel that is flexible and can be easily bent, folded or rolled. For example, the display panel 300 may be a foldable display panel that can be folded and unfolded, a curved display panel in which the display surface is curved, a bended display panel in which an area other than the display surface is curved, etc. It may be a rollable display panel that can be unfolded, and a stretchable display panel that can be stretched.

Additionally, the display panel 300 may be transparent so that objects or backgrounds placed on the lower surface of the display panel 300 can be seen from the front of the display panel 300. Additionally, the display panel 300 may be a reflective display panel capable of reflecting an object or background in front of the display panel 300.

The display panel 300 may include a main area MA and a sub-area SBA protruding from one side of the main area MA. The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is a surrounding area of the display area (DA). The display area DA may occupy most of the main area MA. The display area DA may be placed in the center of the main area MA. The non-display area (NDA) may be an area outside the display area (DA). The non-display area NDA may be defined as an edge area of the display panel 300.

The display area DA may include a main display area MDA and a sub display area SDA. The main display area (MDA) may occupy most of the display area (DA).

The main display area (MDA) does not include a transmission area that transmits light, and may only include a pixel area that includes pixels for displaying an image. In comparison, the sub-display area SDA may include both a transmission area that transmits light and a pixel area that includes pixels for displaying an image. Therefore, the light transmittance of the sub display area SDA may be higher than the light transmittance of the main display area MDA.

The sub-display area SDA may overlap the optical devices 740, 750, 760, and 770 in the third direction (Z-axis direction). Therefore, the light passing through the sub-display area SDA can be incident on the optical devices 740, 750, 760, and 770, so that each of the optical devices 740, 750, 760, and 770 is connected to the display panel 300. Even though it is arranged to overlap, light incident from the front of the display device 10 can be detected.

The sub display area SDA may be disposed on one side of the main display area MDA, for example, above the main display area MDA as shown in FIG. 3, but is not limited to this. For example, the sub display area (SDA) may be placed to the left, right, or below the main display area (MDA). Alternatively, the sub display area SDA may be disposed adjacent to the center of the main display area MDA and surrounded by the main display area MDA. Alternatively, the sub display area SDA may be disposed adjacent to a corner of the display panel 300.

Alternatively, the display area DA may include a plurality of sub-display areas SDA1, SDA2, SDA3, and SDA4 as shown in FIG. 4. The plurality of sub-display areas SDA1, SDA2, SDA3, and SDA4 may be arranged apart from each other. Each of the plurality of sub display areas SDA1, SDA2, SDA3, and SDA4 may be surrounded by the main display area MDA.

The first sub-display area SDA1 may overlap the proximity sensor 740 in the third direction (Z-axis direction). Therefore, although the proximity sensor 740 is disposed to overlap the display panel 300, it can detect light incident from the front of the display device 10 through the first sub-display area SDA1.

The second sub-display area SDA2 may overlap the illuminance sensor 750 in the third direction (Z-axis direction). Therefore, the illuminance sensor 750 can detect light incident from the front of the display device 10 through the second sub-display area SDA2 even though it is disposed to overlap the display panel 300 .

The third sub-display area SDA3 may overlap the iris sensor 760 in the third direction (Z-axis direction). Therefore, the iris sensor 760 can detect light incident from the front of the display device 10 through the third sub-display area SDA3 even though it is arranged to overlap the display panel 300.

The fourth sub-display area SDA4 may overlap the second camera sensor 770 in the third direction (Z-axis direction). Therefore, although the second camera sensor 770 is disposed to overlap the display panel 300, it can detect light incident from the front of the display device 10 through the fourth sub-display area SDA4.

The display area DA may include four sub-display areas SDA1, SDA2, SDA3, and SDA4 as shown in FIG. 4, but is not limited thereto. The number of sub-display areas SDA1, SDA2, SDA3, and SDA4 may depend on the number of optical devices 740, 750, 760, and 770. The sub-display areas SDA1, SDA2, SDA3, and SDA4 may be arranged in one-to-one correspondence with the optical devices 740, 750, 760, and 770.

Each of the plurality of sub-display areas SDA1, SDA2, SDA3, and SDA4 may be formed in a circular shape as shown in FIG. 4, but is not limited thereto. For example, each of the plurality of sub-display areas SDA1, SDA2, SDA3, and SDA4 may be formed in a polygonal or oval shape. Additionally, the plurality of sub-display areas SDA1, SDA2, SDA3, and SDA4 may have the same size as shown in FIG. 4, but is not limited thereto. The plurality of sub-display areas SDA1, SDA2, SDA3, and SDA4 may have different sizes.

The sub area SBA may protrude from one side of the main area MA in a second direction (Y-axis direction). As shown in FIG. 2, the length of the sub area SBA in the first direction (X-axis direction) is smaller than the length of the main area MA in the first direction (X-axis direction), and the length of the sub area SBA in the second direction is smaller than the length of the sub area SBA in the first direction (X-axis direction). The length (in the Y-axis direction) may be smaller than the length in the second direction (in the Y-axis direction) of the main area (MA), but is not limited thereto. The sub-area SBA may be curved and may be disposed at the lower portion of the display panel 300 . In this case, the sub-area SBA may overlap the main area MA in the third direction (Z-axis direction).

The sub-area SBA of the display panel 300 may be curved and may be disposed at the lower portion of the display panel 300 as shown in FIG. 2 . In this case, the sub-area SBA of the display panel 300 may overlap the main area MA of the display panel 300 in the third direction (Z-axis direction).

A display circuit board 310 and a display driving circuit 320 may be attached to the sub area SBA of the display panel 300. The display circuit board 310 is made of a low-resistance, high-reliability material such as an anisotropic conductive film or SAP (Self Assembly Anisotropic Conductive Paste) to form the sub-area (SBA) of the display panel 300. Can be attached on pads. The touch driving circuit 330 may be disposed on the display circuit board 310 .

Figure 5 is a plan view showing a partial area of a display panel according to an embodiment. Figure 5 exemplarily shows the main display area and the first sub-display area of the display panel.

Referring to FIG. 5 , the display panel 300 may include a main display area (MDA) and a first sub-display area (SDA1). The main display area MDA is adjacent to the first sub-display area SDA1 and may be arranged to surround the first sub-display area SDA1.

The display panel 300 may include a plurality of pixels (PX). The plurality of pixels PX include a first pixel PX1 and a second pixel PX2 that emit light in the main display area MDA, and a third pixel PX2 that emits light in the first sub-display area SDA1. It may include a pixel (PX3). There may be a plurality of first pixels (PX1), second pixels (PX2), and third pixels (PX3). The first pixel (PX1) may be a red pixel that emits red light, the second pixel (PX2) may be a green pixel that emits green light, and the third pixel (PX3) may emit blue light. It may be a blue pixel. However, it is not limited to this, and may further include white pixels that emit white light.

The plurality of pixels (PX) may include pixel circuits (CP) that drive light emitting devices. For example, the first pixel (PX1) may include a first pixel circuit (CP1) that drives the first light-emitting device (ED1), and the second pixel (PX2) may include a first pixel circuit (CP1) that drives the second light-emitting device (ED2). may include a second pixel circuit CP2 that drives the third pixel circuit CP2, and the third pixel PX3 may include a third pixel circuit CP3 that drives the third light-emitting element ED3.

The first sub-display area SDA1 may overlap or correspond to the proximity sensor 740 shown in FIG. 1 . That is, the first sub-display area SDA1 may be disposed in an area that overlaps the proximity sensor 740 in the third direction (Z-axis direction). For example, light incident from the outside may pass through the first sub-display area SDA1 and be provided to the proximity sensor 740.

The first sub-display area SDA1 may have fewer pixels than the main display area MDA so that light incident from the outside can be transmitted. An area in the first sub-display area SDA1 where the third light-emitting element ED3 is not disposed may be an area with high light transmittance. For example, an area in the first sub-display area SDA1 where the first electrode of the third light-emitting device ED3 is not disposed may have high light transmittance.

In an exemplary embodiment, the number of third pixels PX3 disposed in the first sub-display area SDA1 may be less than the number of first pixels PX1 disposed in the main display area MDA within the same area. . However, the present invention is not limited to this, and the number of third pixels PX3 disposed in the first sub-display area SDA1 may be the same as the number of first pixels PX1 disposed in the main display area MDA.

The first pixel circuit CP1 of the first pixel PX1 and the second pixel circuit CP2 of the second pixel PX2 may be disposed in the main display area MDA, and the third pixel circuit CP1 of the third pixel PX3 may be disposed in the main display area MDA. The three-pixel circuit CP3 may not be arranged in the main display area MDA. In this case, the light transmittance of the first sub-display area SDA1 may be greater than the light transmittance of the main display area MDA.

The third light emitting element ED3 and the third pixel circuit CP3 may be electrically connected to each other through the connection wire CNL. The connection line CNL may extend from the main display area MDA to the first sub-display area SDA1. The connection wire (CNL) may include a transparent conductive wire. Transparent conductive wiring may include a transparent conductive material or a light-transmissive material. For example, the connecting wire (CNL) is a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In ₂ O ₃ ). It can be formed as a transparent conductive oxide (TCO) film.

The main display area MDA is disposed adjacent to the first sub-display area SDA1 and may surround the first sub-display area SDA1. The main display area MDA may have a lower transmittance than the first sub-display area SDA1. The main display area MDA includes the first pixel circuit CP1 and the first light emitting element ED1 of the first pixel PX1, and the second pixel circuit CP2 and the second light emitting element of the second pixel PX2. (ED2) can be placed. Additionally, the third pixel circuit CP3 of the third pixel PX3 may be disposed in the main display area MDA. Accordingly, the light transmittance of the main display area MDA may be lower than the light transmittance of the first sub-display area SDA1.

The size of the light emitting elements disposed in the main display area MDA may be smaller than the size of the light emitting elements disposed in the first sub display area SDA1. For example, the size of the first light-emitting device ED1 disposed in the main display area MDA1 may be smaller than the size of the third light-emitting device ED3 disposed in the first sub-display area SDA1. Additionally, the size of the first electrode of the first light-emitting element ED1 disposed in the main display area MDA1 is larger than the size of the first electrode of the third light-emitting element ED3 disposed in the first sub-display area SDA1. It can be small.

In one embodiment, the first sub-display area SDA1 may include at least one transparent area TA. The transmission area TA may be an area with the highest light transmittance among the first sub-display areas SDA1. For example, the light transmittance of the transmission area TA is higher than the light transmittance of the area of the first sub-display area SDA1 where the connection wire CNL and the first electrode of the third light emitting element ED3 are not disposed. You can. As will be described later, the transmission area TA is an area where substrates and inorganic films are not disposed and may have the highest light transmittance.

A plurality of transparent areas TA may be arranged within the first sub-display area SDA1 and may be arranged to be spaced apart from each other. For example, the transmission areas TA may be arranged alternately with areas where the third light emitting elements ED3 are arranged in the first direction (X-axis direction) and the second direction (Y-axis direction). That is, areas where the third light emitting elements ED3 are disposed may be disposed between the transmission areas TA.

Transmissive area TA may not overlap with connection line CNL extending from main display area MDA to first sub display area SDA1. The connection line (CNL) may extend around the transmission area (TA). For example, the connection line CNL may bypass the periphery of the transmission area TA and extend into the first sub-display area SDA1.

As described above, the display device 10 according to an embodiment includes a transmissive area TA in the sub-display area SDA that overlaps the optical devices (740, 750, 760, and 770 in FIG. 2), The transmittance of light incident on the optical devices (740, 750, 760, and 770 in FIG. 2) can be improved.

Figure 6 is a cross-sectional view taken along line II' of Figure 5. FIG. 7 is an enlarged view of a partial area of FIG. 6.

Referring to FIGS. 6 and 7 , the display device 10 according to one embodiment includes a first planarization layer (PNL1), a substrate (SUB), a thin film transistor layer (TFTL), a light emitting device layer (EML), and a thin film encapsulation layer. (TFEL) and a second planarization layer (PNL2).

The first planarization layer PNL1 may serve to planarize the lower part of the display device 10. The first flat layer (PNL1) has high transmittance and may be made of a UV-curable resin. For example, the first planarization layer (PNL1) may include a polymer resin such as polyimide (PI), but is not limited thereto.

The first planarization layer (PNL1) may include a protrusion (PRT). The protrusion PRT may be a portion that protrudes in a thickness direction, for example, in a third direction (Z-axis direction) toward the second flat layer PNL2. The protrusion (PRT) may overlap the transparent area (TA) in a plane. Additionally, at least a portion of the protrusion PRT may overlap the main display area MDA, and at least another portion may overlap the first sub-display area SDA1. The transmission area (TA) may completely overlap the planar protrusion (PRT).

The protrusion PRT may have a shape in which the width W1 gradually decreases in the third direction (Z-axis direction). Here, the width W1 of the protrusion PRT is measured in the first direction (X-axis direction), and may also be measured in the second direction (Y-axis direction). For example, the width W1 of the protrusion PRT may gradually decrease as it approaches the second planar layer PNL2 from the lower surface (eg, bottom surface) of the first planar layer PNL1.

The substrate SUB may be a base substrate or a base member. The substrate SUB may include a first substrate SUB1, a first barrier layer BA1, a second substrate SUB2, and a second barrier layer BA2. For example, the first barrier layer BA1 is disposed on the first substrate SUB1, the second substrate SUB2 is disposed on the first barrier layer BA1, and the second substrate SUB2 is disposed on the second substrate SUB2. A second barrier layer BA2 may be disposed.

The first substrate SUB1 and the second substrate SUB2 may be flexible substrates capable of bending, folding, rolling, etc. The first substrate (SUB1) and the second substrate (SUB2) may include a polymer resin such as polyimide (PI), but are not limited thereto.

The first barrier layer (BA1) and the second barrier layer (BA2) each protect the thin film transistors of the thin film transistor layer (TFTL) from moisture penetrating through the first substrate (SUB1) and the second substrate (SUB2), which are vulnerable to moisture permeation. The light emitting element layer (EML) can be protected. Each of the first barrier layer BA1 and the second barrier layer BA2 may be composed of a plurality of inorganic layers alternately stacked. For example, each of the first barrier layer (BA1) and the second barrier layer (BA2) is a single layer selected from a silicon oxide layer, a silicon nitride layer, and a silicon nitride layer, or one or more inorganic layers thereof are alternately stacked. It may be multi-act.

A first through hole (PH1) and a second through hole (PH2) may be disposed in the substrate (SUB). The first through hole PH1 may be a hole that penetrates a portion of the upper thin film encapsulation layer (TFEL), thin film transistor layer (TFTL), and substrate (SUB). The second through hole PH2 may be a hole that penetrates the first substrate SUB1. The first through hole PH1 and the second through hole PH2 are disposed to overlap the transmission area TA and may correspond to the transmission area TA. The first through hole PH1 and the second through hole PH2 may overlap with at least one of the optical devices (740, 750, 760, and 770 in FIG. 2) disposed below.

The first barrier layer BA1, the second substrate SUB2, and the second barrier layer BA2 of the substrate SUB may be penetrated by the first through hole PH1. Accordingly, the first barrier layer BA1, the second substrate SUB2, and the second barrier layer BA2 may not be disposed in the transmission area TA. The first substrate SUB1 of the substrate SUB may be penetrated by the second through hole PH2. Accordingly, the first substrate SUB1 may not be disposed in the transmission area TA.

The first through hole PH1 may be filled with the second planarization layer PNL2 described later, and the second through hole PH2 may be filled with the first planarization layer PNL1 described above. The protrusion PRT of the first substrate SUB1 may be disposed in the second through hole PH2. The width W2 of the second through hole PH2 may gradually increase from the top surface of the first substrate SUB1 to the bottom surface of the first substrate SUB1. That is, the width W2 of the second through hole PH2 may gradually increase in the direction opposite to the third direction (Z-axis direction).

Meanwhile, the thin film transistor layer (TFTL) is disposed on the substrate (SUB), and includes a light blocking layer (BML), a buffer layer (BF), a thin film transistor (TFT), a gate insulating layer (GI), an interlayer insulating layer (ILD), and a thin film transistor layer (TFTL). 1 It may include a connection electrode (CNE1), a connection wire (CNL), a first via layer (VIA1), a second connection electrode (CNE2), and a second via layer (VIA2).

The light blocking layer (BML) may be disposed on the second barrier layer (BA2). The light blocking layer (BML) may be disposed to overlap the semiconductor layer (ACT) of the thin film transistor (TFT) to prevent leakage current from occurring when light is incident on the semiconductor layer (ACT) of the thin film transistor (TFT). . Accordingly, the light blocking layer BML may be disposed in the main display area MDA where the thin film transistor TFT is disposed, and may not be disposed in the first sub display area SDA1 where the thin film transistor TFT is not disposed.

The light blocking layer (BML) may be covered by the buffer layer (BF). The light blocking layer (BML) is made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multilayer made of an alloy.

The buffer layer BF may be disposed on the light blocking layer BML and the second barrier layer BA2. The buffer layer (BF) may include an inorganic film that can prevent penetration of air or moisture. For example, the buffer layer BF may be a single layer selected from a silicon oxide layer, a silicon nitride layer, and a silicon nitride layer, or a multilayer in which one or more inorganic layers of these layers are alternately stacked.

A thin film transistor (TFT) may be disposed on the buffer layer (BF) and may form a pixel circuit for each of a plurality of pixels. For example, a thin film transistor (TFT) may be a driving transistor or switching transistor of a pixel circuit. A thin film transistor (TFT) may include a semiconductor layer (ACT), a source electrode (SE), a drain electrode (DE), and a gate electrode (GE).

The semiconductor layer (ACT) may be disposed on the buffer layer (BF). The semiconductor layer (ACT) may overlap the light blocking layer (BML) and the gate electrode (GE) in the thickness direction, and may be insulated from the gate electrode (GE) by the gate insulating layer (GI). The semiconductor layer (ACT) may include polycrystalline silicon, single crystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. A portion of the semiconductor layer (ACT) may form a source electrode (SE) and a drain electrode (DE) in which the material of the semiconductor layer (ACT) becomes a conductor.

The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer GI interposed therebetween. The gate electrode (GE) is made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multilayer made of an alloy.

The gate insulating layer (GI) may be disposed on the semiconductor layer (ACT). For example, the gate insulating layer GI may cover the semiconductor layer ACT and the buffer layer BF, and may insulate the semiconductor layer ACT and the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

The interlayer insulating layer (ILD) may cover the gate electrode (GE) and the gate insulating layer (GI). The interlayer insulating layer (ILD) may include a contact hole through which the first connection electrode (CNE1) passes. The contact hole of the interlayer insulating layer (ILD) may be connected to the contact hole of the gate insulating layer (GI).

The first connection electrode CNE1 may be disposed on the interlayer insulating layer ILD. The first connection electrode (CNE1) may electrically connect the drain electrode (DE) of the thin film transistor (TFT) and the second connection electrode (CNE2). The first connection electrode CNE1 may be inserted into a contact hole formed in the interlayer insulating layer ILD and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT. The first connection electrode (CNE1) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be formed as a single layer or multilayer made of an alloy thereof.

The first via layer VIA1 can flatten the level difference caused by the lower electrodes. The first via layer (VIA1) may be disposed on the first connection electrode (CNE1) and the interlayer insulating layer (ILD). The first via layer VIA1 may include a contact hole through which the first connection electrode CNE1 passes. The first via layer (VIA1) is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. It can be.

The second connection electrode CNE2 may be disposed on the first via layer VIA1. The second connection electrode CNE2 may be electrically connected to the drain electrode DE of the thin film transistor TFT. The second connection electrode CNE2 may be inserted into a contact hole formed in the first via layer VIA1 and contact the first connection electrode CNE1. The second connection electrode (CNE2) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be formed as a single layer or multilayer made of an alloy thereof.

The second via layer VIA2 can flatten the level difference caused by the lower electrodes. The second via layer (VIA2) may be disposed on the second connection electrode (CNE2) and the first via layer (VIA1). The second via layer VIA2 may include a contact hole through which the pixel electrodes AE1 and AE2 pass. The second via layer (VIA2) is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. It can be.

Meanwhile, the main display area MDA has the configurations described in the thin film transistor layer TFTL, but the first sub display area SDA1 does not have a thin film transistor TFT, so it is located in the thin film transistor layer TFTL. Only some layers can be placed. That is, the first sub-display area SDA1 includes not only a thin film transistor (TFT), but also a gate insulating layer (GI), an interlayer insulating layer (ILD), a first connection electrode (CNE1), a second connection electrode (CNE2), and a second connection electrode (CNE2). The via layer (VIA2) may not be placed. Among these, the gate insulating layer GI, the interlayer insulating layer ILD, and the second via layer VIA2 may be omitted to prevent the light transmittance in the first sub-display area SDA1 from being reduced. Additionally, the thin film transistor layer TFTL may be disposed in the main display area MDA and the first sub-display area SDA1, but may not be disposed in the transmission area TA. For example, the thin film transistor layer (TFTL) may not overlap the transmission area (TA) in the thickness direction.

In the first sub-display area SDA1, a buffer layer BF and a first via layer VIA1 among the thin film transistor layers TFTL may be disposed, and a connection wire CNL may be further disposed. The connection wire (CNL) may be disposed on the buffer layer (BF). The connection wire (CNL) may be disposed on the interlayer insulating layer (ILD) in the main display area (MDA), extend to the first sub-display area (SDA1), and be disposed on the buffer layer (BF).

The first via layer VIA1 is disposed on the connection line CNL and the buffer layer BF and may include a contact hole through which the pixel electrode AE3 passes. The thickness of the first via layer VIA1 of the main display area MDA may be smaller than the thickness of the first via layer VIA1 of the first sub-display area SDA1. Since some of the above-mentioned layers are not disposed in the first sub-display area SDA1, the first via layer VIA1 formed through a solution process may be formed to be relatively thicker than that in the main display area MDA.

In the transmission area TA, some layers of the thin film transistor layer TFTL may be penetrated by the first through hole PH1, and other layers may be removed by the first through hole PH1.

Specifically, in the transmission area TA, the buffer layer BF and the first via layer VIA1 may be penetrated by the first through hole PH1. For example, a first through hole PH1 may be formed in the buffer layer BF and the first via layer VIA1 to form a transmission area TA. In addition, the gate insulating layer (GI), the interlayer insulating layer (ILD), and the second via layer (VIA2) partially extending from the main display area (MDA) to the first sub-display area (SDA1) are formed through the first through hole (PH1). It can be removed from the transmission area (TA) by . Accordingly, a portion of the inner peripheral surface of the first through hole (PH1) is formed by the buffer layer (BF), the gate insulating layer (GI), the interlayer insulating layer (ILD), the first via layer (VIA1), and the second via layer (VIA2). Some of the side edges may be disposed, and some of the side edges of the buffer layer (BF) and the first via layer (VIA1) may be disposed.

Meanwhile, the light emitting device layer (EML) may be disposed on the thin film transistor layer (TFTL). Additionally, the light emitting device layer (EML) may be disposed in the main display area (MDA) and the first sub-display area (SDA1), but may not be disposed in the transmission area (TA). For example, the light emitting device layer (EML) may not overlap the transmission area (TA) in the thickness direction.

The light emitting device layer (EML) may include light emitting devices (ED1, ED2, ED3) and a plurality of bank structures (BNS). The light emitting device ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

The display device 10 may include a plurality of light-emitting areas EA1 and EA2 arranged in the main display area MDA and a plurality of light-emitting areas EA3 arranged in the first sub-display area SDA1. The light-emitting areas EA1, EA2, and EA3 may include a first light-emitting area EA1, a second light-emitting area EA2, and a third light-emitting area EA3 that emit light of different colors. The first to third light-emitting areas (EA1, EA2, EA3) may emit red, green, or blue light, respectively, and the color of light emitted from each light-emitting area (EA1, EA2, EA3) is determined by the light-emitting device layer ( It may vary depending on the type of light emitting element (ED1, ED2, ED3) placed in the EML). In an exemplary embodiment, the first light-emitting area EA1 emits red first light, the second light-emitting area EA2 emits green second light, and the third light-emitting area EA3 emits blue light. A third light may be emitted. However, it is not limited to this.

The first to third light emitting areas EA1, EA2, and EA3 may be defined by a plurality of openings OPE1, OPE2, and OPE3 formed in the bank structure BNS of the light emitting device layer EML, respectively. For example, the first light-emitting area EA1 is defined by the first opening OPE1 of the bank structure BNS, and the second light-emitting area EA2 is defined by the second opening OPE2 of the bank structure BNS. The third light emitting area EA3 may be defined by the third opening OPE3 of the bank structure BNS.

In an exemplary embodiment, the areas or sizes of the first to third light emitting areas EA1, EA2, and EA3 may be the same. For example, in the display device 10, the openings OPE1, OPE2, and OPE3 of the bank structures BNS have the same diameter, and the first emission area EA1, the second emission area EA2, and the third emission area Areas EA3 may have the same area. However, it is not limited to this. In the display device 10, the first to third light emitting areas EA1, EA2, and EA3 may have different areas or sizes. For example, the area of the second emission area EA2 is larger than the areas of the first emission area EA1 and the third emission area EA3, and the area of the third emission area EA3 is larger than the area of the first emission area EA1. ) may be larger than the area of . The intensity of light emitted from the corresponding light emitting area (EA1, EA2, EA3) may vary depending on the area of the light emitting area (EA1, EA2, EA3), and the display device ( 10) Alternatively, the color of the screen displayed on the electronic device 1 can be controlled. The areas of the light emitting areas EA1, EA2, and EA3 can be freely adjusted according to the screen color required for the display device 10 and the electronic device 1. Additionally, the area of the light emitting areas EA1, EA2, and EA3 is related to light efficiency, lifespan of the light emitting element ED, etc., and may have a trade-off relationship with reflection by external light. The areas of the light emitting areas EA1, EA2, and EA3 can be adjusted by taking the above factors into consideration.

The display device 10 may include a plurality of light-emitting elements ED1, ED2, and ED3 arranged in different light-emitting areas EA1, EA2, and EA3. The light-emitting elements ED1, ED2, and ED3 include a first light-emitting element ED1 disposed in the first light-emitting area EA1, a second light-emitting element ED2 disposed in the second light-emitting area EA2, and a third light-emitting element ED1. It may include a third light emitting device ED3 disposed in the area EA3. Each of the light emitting elements (ED1, ED2, ED3) includes a pixel electrode (AE1, AE2, AE3), a light emitting layer (EL1, EL2, EL3), and a common electrode (CE1, CE2, CE3), and has different light emitting areas ( The light emitting elements ED1, ED2, and ED3 disposed in EA1, EA2, and EA3) may emit light of different colors depending on the materials of the light emitting layers EL1, EL2, and EL3. For example, the first light-emitting device ED1 disposed in the first light-emitting area EA1 emits red light of the first color, and the second light-emitting device ED2 disposed in the second light-emitting area EA2 emits red light of the first color. The third light emitting element ED3 disposed in the third light emitting area EA3 may emit green light of the second color, and may emit blue light of the third color.

The pixel electrodes AE1, AE2, and AE3 may be disposed in a plurality of light emitting areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 include a first pixel electrode AE1 disposed in the first emission area EA1, a second pixel electrode AE2 disposed in the second emission area EA2, and a third emission area. It may include a third pixel electrode AE3 disposed in the area EA3. The first pixel electrode AE1 and the second pixel electrode AE2 are disposed on the second via layer VIA2 of the main display area MDA, and the third pixel electrode AE3 is disposed on the first sub-display area SDA1. ) may be disposed on the first via layer (VIA1). Each of the pixel electrodes AE1, AE2, and AE3 may be disposed in different light-emitting areas EA1, EA2, and EA3 to form light-emitting elements ED1, ED2, and ED3 that emit light of different colors.

Each pixel electrode (AE1, AE2, and AE3) may be arranged to overlap one of the openings (OPE1, OPE2, and OPE3) of the bank structure (BNS). The first pixel electrode AE1 and the second pixel electrode AE2 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2. The third pixel electrode AE3 may be electrically connected to the drain electrode DE of the thin film transistor (TFT) through a connection wire.

In an exemplary embodiment, the pixel electrodes AE1, AE2, and AE3 include indium-tin-oxide (ITO), indium-zinc-oxide (IZO), and zinc oxide (Zinc). A layer of materials with a high work function such as oxide (ZnO), indium oxide (In ₂ O ₃ ), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), A layer of reflective material such as palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof is laminated. It may have a laminated film structure. A layer with a high work function may be placed above the reflective material layer and close to the light emitting layers (EL1, EL2, and EL3). For example, the pixel electrodes AE1, AE2, and AE3 may have a multi-layer structure of ITO/Mg, ITO/MgF, ITO/Ag, or ITO/Ag/ITO, but are not limited thereto.

The inorganic insulating layer (ISL) is disposed on the second via layer (VIA2), the first pixel electrode (AE1), and the second pixel electrode (AE2) in the main display area (MDA), and the first sub-display area (SDA1) It may be disposed on the first via layer (VIA1) and the third pixel electrode (AE3). The inorganic insulating layer (ISL) is entirely disposed on the first via layer (VIA1) in the main display area (MDA), and a portion of the inorganic insulating layer (ISL) overlaps the first pixel electrode (AE1) and the second pixel electrode (AE2). Part of the upper surface of the pixel electrode AE1 and the second pixel electrode AE2 may be exposed. In addition, the inorganic insulating layer (ISL) is entirely disposed on the first via layer (VIA1) in the first sub-display area (SDA1), and a portion of the inorganic insulating layer (ISL) overlaps the third pixel electrode (AE3). ) can expose part of the upper surface.

For example, the inorganic insulating layer (ISL) may expose the pixel electrodes (AE1, AE2, AE3) at the portion overlapping the openings (OPE1, OPE2, OPE3) of the bank structure (BNS), and the pixel electrodes (AE1, The light emitting layers EL1, EL2, and EL3 disposed on AE2 and AE3 may be directly disposed on the pixel electrodes AE1, AE2, and AE3. The inorganic insulating layer (ISL) may include an inorganic insulating material. As an example, the inorganic insulating layer (ISL) may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride.

According to one embodiment, the inorganic insulating layer (ISL) may be disposed on the pixel electrodes (AE1, AE2, and AE3) and spaced apart from the top surface of each pixel electrode (AE1, AE2, and AE3). The inorganic insulating layer (ISL) may partially overlap and not directly contact each pixel electrode (AE1, AE2, AE3), and each light emitting layer is between the inorganic insulating layer (ISL) and each pixel electrode (AE1, AE2, AE3). Each of the light emitting layers EL1, EL2, and EL3 of the devices ED1, ED2, and ED3 may be disposed. In the manufacturing process of the display device 10, a sacrificial layer may be disposed on the pixel electrodes AE1, AE2, and AE3 before forming the inorganic insulating layer ISL. The inorganic insulating layer (ISL) may be disposed to cover a portion of the sacrificial layer, and then be spaced apart from the upper surface of each pixel electrode (AE1, AE2, AE3) when the sacrificial layer is removed. In the subsequent deposition process of the light emitting layer (EL1, EL2, EL3), the materials forming the light emitting layer (EL1, EL2, EL3) fill the space between the inorganic insulating layer (ISL) and the pixel electrodes (AE1, AE2, AE3), forming an inorganic insulating layer ( ISL) may be partially disposed on each light emitting layer (EL1, EL2, EL3). However, the inorganic insulating layer (ISL) may directly contact the side surfaces of the pixel electrodes (AE1, AE2, and AE3).

The display device 10 may include a thin film transistor layer (TFTL) or a plurality of bank structures (BNS) disposed on a substrate (SUB) and including a plurality of openings (OPE1, OPE2, and OPE3). The bank structure (BNS) may have a structure in which bank layers (BN1, BN2, BN3) containing different materials are sequentially stacked, and a plurality of openings (OPE1, OPE2) forming the light emitting areas (EA1, EA2, EA3). , OPE3) may be included. The light emitting elements ED1, ED2, and ED3 of the display device 10 may be arranged to overlap the openings OPE1, OPE2, and OPE3 of the bank structure BNS.

The bank structure (BNS) may include a first bank layer (BN1), a second bank layer (BN2), and a third bank layer (BN3) sequentially disposed on the inorganic insulating layer (ISL). The first bank layer (BN1) is the bottom layer of the bank structure (BNS), the third bank layer (BN3) is the top layer of the bank structure (BNS), and the second bank layer (BN2) is the middle layer of the bank structure (BNS). You can. The bank structure BNS may include a tip TIP in which the second bank layer BN2 protrudes from the first bank layer BN1 toward the openings OPE1, OPE2, and OPE3.

In the bank structure BNS, side sides of the first bank layer BN1 may have a shape that is depressed inward from the side sides of the second bank layer BN2. In the bank structure BNS, the first bank layer BN1 may have the same thickness as the second bank layer BN2. However, the present invention is not limited thereto, and the first bank layer BN1 may be thicker than the second bank layer BN2. As the second bank layer (BN2) has a shape that protrudes toward the openings (OPE1, OPE2, and OPE3) more than the first bank layer (BN1), the inner side walls of the openings (OPE1, OPE2, and OPE3) of the bank structure (BNS) An undercut may be formed below the tip of the second bank layer BN2.

The sidewall shape of the bank structure (BNS) may be a structure in which the first bank layer (BN1) and the second bank layer (BN2) include different materials and are formed due to a difference in etching speed during the etching process. According to one embodiment, the second bank layer BN2 may include a material with a slower etch rate than the first bank layer BN1, and in the process of forming the openings OPE1, OPE2, and OPE3 of the bank structure BNS, The first bank layer BN1 may be further etched to form an undercut under the tip of the second bank layer BN2. In an exemplary embodiment, the first bank layer BN1 may include a metal material with high electrical conductivity, and the second bank layer BN2 may include a metal material with low reflectivity. For example, the first bank layer BN1 may include aluminum (Al), and the second bank layer BN2 may include titanium (Ti). The bank structure BNS may have a structure in which Al/Ti is stacked from the inorganic insulating layer ISL, and a tip may be formed in the Ti layer of the second bank layer BN2.

The third bank layer BN3 may include an organic material. The third bank layer BN3 may serve as a mask pattern in the process of forming the openings OPE1, OPE2, and OPE3 of the bank structure BNS. In this embodiment, the third bank layer (BN3) is not removed after the process of forming the openings (OPE1, OPE2, and OPE3) of the bank structure (BNS), so that the third bank layer (BN3) is formed on the second bank layer (BN2). This can be placed. The third bank layer BN3 may have the same size as the second bank layer BN2. The width of the third bank layer BN3 in the first direction (X-axis direction) may be the same as the width of the second bank layer BN2.

In the bank structure BNS, the first bank layer BN1 may be electrically connected to the common electrodes CE1, CE2, and CE3 of the different light emitting devices ED1, ED2, and ED3. The light emitting elements (ED1, ED2, ED3) disposed in different light emitting areas (EA1, EA2, EA3) are not directly connected to the common electrodes (CE1, CE2, CE3), but are connected to the first bank layer (BNS) of the bank structure (BNS). It can be electrically connected through BN1).

In the manufacturing process of the display device 10, the pixel defining layer forming the light emitting areas EA1, EA2, and EA3 is formed of an organic material, or the light emitting layers EL1, EL2, and EL3 of the light emitting elements ED1, ED2, and ED3 are formed of an organic material, respectively. A mask process is required to form each light emitting area (EA1, EA2, EA3). In order to perform a mask process, the display device 10 may require a structure to hold the mask, or an unnecessarily large non-display area (NDA) may be required to control dispersion due to the mask process. If this mask process is minimized, unnecessary components, such as structures for holding a mask, can be omitted from the display device 10, and the area of the non-display area (NDA) for dispersion control can be minimized.

The display device 10 according to one embodiment includes a bank structure (BNS) that forms the light emitting areas (EA1, EA2, and EA3), and can be formed using a deposition and etching process rather than a mask process. In addition, the bank structure (BNS) includes a first bank layer (BN1) and a second bank layer (BN2) including different metal materials, and the inner side walls of the openings (OPE1, OPE2, OPE3) have a tip (TIP). As it has a structure that includes different layers, it is possible to form different layers individually in different light-emitting areas (EA1, EA2, and EA3) through a deposition process. For example, even if the light emitting layers (EL1, EL2, EL3) of the light emitting elements (ED1, ED2, ED3) and the common electrodes (CE1, CE2, CE3) are formed through a deposition process without a mask, the openings (OPE1, OPE2) , OPE3) The materials deposited by the tip of the second bank layer BN2 formed on the inner sidewall may be disconnected and broken between the openings OPE1, OPE2, and OPE3. After forming a material for forming a specific layer on the front of the display device 10, different layers are individually formed in different light-emitting areas (EA1, EA2, and EA3) through a process of etching and removing the layer formed in the unwanted area. It is possible to form The display device 10 can form different light-emitting elements (ED1, ED2, and ED3) for each light-emitting area (EA1, EA2, and EA3) through a deposition and etching process without using a mask process, and the display device 10 ), unnecessary configurations can be omitted and the area of the non-display area (NDA) can be minimized.

The light emitting layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers made of organic materials, and may be formed on the pixel electrodes AE1, AE2, and AE3 through a deposition process. In the light emitting layer (EL1, EL2, EL3), a thin film transistor (TFT) applies a predetermined voltage to the pixel electrodes (AE1, AE2, AE3) of the light emitting elements (ED1, ED2, ED3). When the common electrodes (CE1, CE2, CE3) of ) receive a common voltage or cathode voltage, the holes and electrons can each move to the light emitting layer (EL1, EL2, EL3) through the hole transport layer and the electron transport layer, and the holes and electrons can move to the light emitting layer (EL1, EL2, EL3). Light can be emitted by combining with each other in the light emitting layers (EL1, EL2, and EL3).

The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 disposed in different light-emitting areas EA1, EA2, and EA3. The first emission layer EL1 is disposed on the first pixel electrode AE1 in the first emission area EA1, and the second emission layer EL2 is disposed on the second pixel electrode AE2 in the second emission area EA2. and the third emission layer EL3 may be disposed on the third pixel electrode AE3 in the third emission area EA3. The first to third light emitting layers EL1, EL2, and EL3 may be light emitting layers of the first to third light emitting elements ED1, ED2, and ED3, respectively. The first light emitting layer (EL1) is a light emitting layer that emits red light of the first color, the second light emitting layer (EL2) is a light emitting layer that emits green light of the second color, and the third light emitting layer (EL3) is a light emitting layer that emits blue light of the third color. It may be a light-emitting layer that emits light.

According to one embodiment, a portion of the light emitting layers EL1, EL2, and EL3 of the light emitting devices ED1, ED2, and ED3 may be disposed between the pixel electrodes AE1, AE2, and AE3 and the inorganic insulating layer ISL. The inorganic insulating layer (ISL) may be disposed on the pixel electrodes AE1, AE2, and AE3 and spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The deposition process of the light-emitting layers EL1, EL2, and EL3 may be performed so that the material of the light-emitting layer is deposited in an inclined direction rather than perpendicular to the upper surface of the substrate SUB. Accordingly, the light emitting layers (EL1, EL2, EL3) are the upper surfaces of the pixel electrodes (AE1, AE2, AE3) exposed to the openings (OPE1, OPE2, OPE3) of the bank structure (BNS), and the pixel electrodes (AE1, AE2, AE3) ) and the inorganic insulating layer (ISL).

The common electrodes (CE1, CE2, and CE3) may be disposed on the light emitting layers (EL1, EL2, and EL3). The common electrodes (CE1, CE2, and CE3) include a transparent conductive material so that light generated in the light emitting layers (EL1, EL2, and EL3) can be emitted. The common electrodes (CE1, CE2, CE3) may receive a common voltage or a low-potential voltage. When the pixel electrodes (AE1, AE2, AE3) receive a voltage corresponding to the data voltage and the common electrodes (CE1, CE2, CE3) receive a low potential voltage, the potential difference between the pixel electrodes (AE1, AE2, AE3) and the common electrode By being formed between (CE1, CE2, and CE3), the light emitting layer (EL1, ED2, ED3) can emit light.

In an exemplary embodiment, the common electrodes (CE1, CE2, CE3) are Li, Ca, LiF/Ca, LiF/Al, Al, Mg, Ag, Pt, Pd, Ni, Au Nd, Ir, Cr, BaF, Ba Alternatively, it may include a material layer with a small work function, such as a compound or mixture thereof (for example, a mixture of Ag and Mg, etc.). The common electrodes CE1, CE2, and CE3 may further include a transparent metal oxide layer disposed on the material layer with a low work function.

The common electrodes (CE1, CE2, CE3) include a first common electrode (CE1), a second common electrode (CE2), and a third common electrode (CE3) disposed in different light-emitting areas (EA1, EA2, EA3). can do. The first common electrode CE1 is disposed on the first emission layer EL1 in the first emission area EA1, and the second common electrode CE2 is disposed on the second emission layer EL2 in the second emission area EA2. and the third common electrode CE3 may be disposed on the third emission layer EL3 in the third emission area EA3.

According to one embodiment, a portion of the common electrodes CE1, CE2, and CE3 of the light emitting devices ED1, ED2, and ED3 may be disposed on the side of the first bank layer BN1 of the bank structure BNS. Similar to the light emitting layers (EL1, EL2, and EL3), the common electrodes (CE1, CE2, and CE3) may also be formed through a deposition process. The deposition process of the common electrodes CE1, CE2, and CE3 may be performed so that the electrode material is deposited in an inclined direction rather than in a perpendicular direction to the top surface of the substrate SUB. Accordingly, the common electrodes CE1, CE2, and CE3 may be disposed on the side of the first bank layer BN1 below the tip of the second bank layer BN2 of the bank structure BNS. The common electrodes CE1, CE2, and CE3 may directly contact the side surface of the first bank layer BN1. The common electrodes (CE1, CE2, CE3) of the different light emitting elements (ED1, ED2, ED3) may each be in direct contact with the first bank layer (BN1) of the bank structure (BNS), and the common electrodes (CE1, CE2, Each of the CE3) can be electrically connected to each other. Unlike the pixel electrodes AE1, AE2, and AE3, the common electrodes (CE1, CE2, and CE3) are not divided into a plurality of pixels, but may be implemented as an electrode that is electrically common to all pixels.

In the manufacturing process of the display device 10, the light emitting layers (EL1, EL2, EL3) of each light emitting element (ED1, ED2, ED3) and the common electrode (CE1, CE2, CE3) may be formed through a deposition process. As the bank structure (BNS) includes a tip (TIP) formed in the second bank layer (BN2), even if the deposition process is performed over the entire display area (DA) of the display device 10 without using a mask, the bank structure The material can form a broken layer between the different openings (OPE1, OPE2, and OPE3) of the (BNS). Patterns containing the same material as the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 may remain on the bank structure BNS.

According to one embodiment, the display device 10 includes first to third organic patterns (ELP1, ELP2, ELP3) and first to third electrode patterns (CEP1, CEP2, CEP3) disposed on the bank structure (BNS). may include.

A plurality of organic patterns ELP1, ELP2, and ELP3 may each be disposed on the third bank layer BN3. The organic patterns ELP1, ELP2, and ELP3 each include a first organic pattern ELP1 and a second organic pattern ELP2 including the same material as the light emitting layers EL1, EL2, and EL3 of the light emitting elements ED1, ED2, and ED3. , and a third organic pattern (ELP3).

The first organic pattern ELP1 may include the same material as the first light emitting layer EL1 of the first light emitting device ED1. The second organic pattern ELP2 includes the same material as the second light emitting layer EL2 of the second light emitting device ED2, and the third organic pattern ELP3 includes the third light emitting layer EL3 of the third light emitting device ED3. ) may contain the same materials as. Each of the organic patterns ELP1, ELP2, and ELP3 may be formed in the same process as the light emitting layers EL1, EL2, and EL3 including the same material. Each of the organic patterns ELP1, ELP2, and ELP3 may be disposed adjacent to the light emitting area EA1, EA2, and EA3 where each light emitting layer EL1, EL2, and EL3 is disposed. For example, the first organic pattern ELP1 may be disposed on the first light emitting area EA1 or the third bank layer BN3 surrounding the first opening OPE1. You can. The second organic pattern ELP2 is disposed on the third bank layer BN3 in the second light emitting area EA2 or around the second opening OPE2 and surrounds the second opening OPE2. The pattern ELP3 may be disposed on the third light emitting area EA3 or the third bank layer BN3 surrounding the third opening OPE3.

These organic patterns (ELP1, ELP2, ELP3) may be traces formed by being disconnected from the light emitting layer (EL1, EL2, EL3) as the bank structure (BNS) includes a tip (TIP). The light-emitting layers (EL1, EL2, EL3) are formed within the openings (OPE1, OPE2, OPE3), and the organic patterns (ELP1, ELP2, ELP3) and the light-emitting layers (EL1, EL2) are formed by the tip of the bank structure (BNS). , EL3) can be disconnected from each other. As the light emitting layers (EL1, EL2, EL3) are formed through a deposition process without a mask, the materials of the light emitting layers (EL1, EL2, EL3) can be formed entirely on the bank structure (BNS), which is formed in each light emitting area. (EA1, EA2, EA3), or organic patterns (ELP1, ELP2, ELP3) formed by patterning around the openings (OPE1, OPE2, OPE3).

The plurality of electrode patterns (CEP1, CEP2, CEP3) may be disposed on the plurality of organic patterns (ELP1, ELP2, ELP3), respectively. The first electrode pattern (CEP1, CPE2, CEP3) includes the same material as the common electrode (CE1, CE2, CE3) of the light emitting elements (ED1, ED2, ED3), and the second electrode pattern (CEP2), respectively. ), and a third electrode pattern (CEP3).

For example, the first electrode pattern (CEP1), the second electrode pattern (CEP2), and the third electrode pattern (CEP3) are the first organic pattern (ELP1), the second organic pattern (ELP2), and the third organic pattern (ELP1), respectively. It can be placed directly on the pattern (ELP3). The arrangement relationship between the electrode patterns (CEP1, CPE2, CEP3) and the organic patterns (ELP1, ELP2, ELP3) is determined by the light emitting layers (EL1, EL2, EL3) of the light emitting elements (ED1, ED2, ED3) and the common electrodes (CE1, CE2, It may be the same as the placement relationship of CE3). These electrode patterns (CEP1, CPE2, CEP3) may be traces formed by the deposited material being disconnected from the common electrodes (CE1, CE2, CE3) as the bank structure (BNS) includes a tip (TIP). . The display device 10 can individually form common electrodes CE1, CE2, and CE3 in different areas using the tip of the bank structure BNS even in a deposition process without a mask.

A plurality of organic patterns (ELP1, ELP2, ELP3) and electrode patterns (CEP1, CPE2, CEP3) are disposed on the bank structure (BNS) and emitting areas (EA1, EA2, EA3) or openings (OPE1, OPE2, OPE3) It can be placed to surround the perimeter. The stacked structure of the plurality of organic patterns (ELP1, ELP2, ELP3) and electrode patterns (CEP1, CPE2, CEP3) disposed around the light emitting area (EA1, EA2, EA3) is partially used in the manufacturing process of the display device 10. The pattern shape may vary due to etching. Accordingly, a portion of the upper surface of the third bank layer BN3 of the bank structure BNS may not be covered by the plurality of organic patterns ELP1, ELP2, and ELP3 and the electrode patterns CEP1, CPE2, and CEP3.

The thin film encapsulation layer (TFEL) is disposed on the light emitting devices (ED1, ED2, ED3) and the bank structure (BNS) and may cover the plurality of light emitting devices (ED1, ED2, ED3) and the bank structure (BNS). . The thin film encapsulation layer (TFEL) includes at least one inorganic layer and can prevent oxygen or moisture from penetrating into the light emitting device layer (EML). The thin film encapsulation layer (TFEL) includes at least one organic layer and can protect the light emitting device layer (EML) from foreign substances such as dust.

In an exemplary embodiment, the thin film encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 that are sequentially stacked. The first encapsulation layer (TFE1) and the third encapsulation layer (TFE3) may be inorganic encapsulation layers, and the second encapsulation layer (TFE2) disposed between them may be an organic encapsulation layer.

The first encapsulation layer (TFE1) and the third encapsulation layer (TFE3) may each include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride.

The second encapsulation layer (TFE2) may include a polymer-based material. Polymer-based materials may include acrylic resin, epoxy resin, polyimide, and polyethylene. For example, the second encapsulation layer (TFE2) may include an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer (TFE2) can be formed by applying a monomer or polymer.

The first encapsulation layer (TFE1) may be disposed on the light emitting devices (ED1, ED2, ED3), a plurality of patterns, and the bank structure (BNS). The first encapsulation layer (TFE1) may include an inorganic insulating material and cover the light emitting devices (ED1, ED2, and ED3). The first encapsulation layer (TFE1) can prevent the light emitting elements (ED1, ED2, and ED3) from being damaged by external air, and prevents the patterns disposed on the bank structure (BNS) from being peeled off during the manufacturing process of the display device 10. can be prevented.

The first encapsulation layer TFE1 may be disposed to cover the organic patterns ELP1, ELP2, and ELP3 and the electrode patterns CEP1, CPE2, and CEP3. Since the first encapsulation layer (TFE1) can be formed through chemical vapor deposition (CVD), it can be formed with a uniform thickness along the steps of the deposited layer. For example, the first encapsulation layer (TFE1) may form a thin film under the undercut caused by the tip (TIP) of the bank structure (BNS).

The first encapsulation layer (TFE1) may be disposed on the first light emitting device (ED1) and the first electrode pattern (CEP1). The first encapsulation layer (TFE1) is disposed to cover the first light emitting element (ED1) and the inner sidewall of the first opening (OPE1), and also covers the first organic pattern (ELP1) and the first electrode pattern (CEP1). It can be arranged as follows. Additionally, the first encapsulation layer (TFE1) may be disposed on the second light emitting device (ED2) and the second electrode pattern (CEP2). The first encapsulation layer (TFE1) is disposed to cover the second light emitting element (ED2) and the inner sidewall of the second opening (OPE2), and also covers the second organic pattern (ELP2) and the second electrode pattern (CEP2). It can be arranged as follows. Additionally, the first encapsulation layer (TFE1) may be disposed on the third light emitting device (ED3) and the third electrode pattern (CEP3). The first encapsulation layer (TFE1) is disposed to cover the third light emitting element (ED3) and the inner sidewall of the third opening (OPE3), and also covers the third organic pattern (ELP3) and the third electrode pattern (CEP3). It can be arranged as follows. The first encapsulation layer (TFE1) may overlap with the first to third openings (OPE1, OPE2, and OPE3) and may not overlap with the transmission area (TA).

The second encapsulation layer (TFE2) may be disposed on the first encapsulation layer (TFE1). The second encapsulation layer (TFE2) may be arranged to overlap each of the light emitting areas (EA1, EA2, and EA3). Specifically, the second encapsulation layer (TFE2) may include a first organic layer (TFE21), a second organic layer (TFE22), and a third organic layer (TFE23).

Since the first organic layer (TFE21), the second organic layer (TFE22), and the third organic layer (TFE23) may be formed through a solution process such as inkjet printing or spin coating, the heights of the layers may be formed to be the same. For example, the first organic layer (TFE21), the second organic layer (TFE22), and the third organic layer (TFE23) are formed to fill the first to third openings (OPE1, OPE2, and OPE3) between the bank structure (BNS). It can be. Additionally, the first organic layer (TFE21), the second organic layer (TFE22), and the third organic layer (TFE23) are disposed on the bank structure (BNS) and may be formed to protrude to a higher height than the bank structure (BNS).

The first organic layer (TFE21) may be disposed on the first light-emitting device (ED1) and the first electrode pattern (CEP1). The first organic layer TFE21 may be arranged to overlap the first emission area EA1 and fill the first opening OPE1. However, the first organic layer TFE21 may not overlap the second opening OPE2 and the third opening OPE3, but may be disposed only on the first opening OPE1 and the surrounding bank structure BNS. The second organic layer TFE22 may be disposed on the second light emitting device ED2 and the second electrode pattern CEP2. The second organic layer TFE22 may be arranged to overlap the second light emitting area EA2 and fill the second opening OPE2. However, the second organic layer TFE22 may not overlap the first opening OPE1 and the third opening OPE3, but may be disposed only on the second opening OPE2 and the surrounding bank structure BNS. The third organic layer (TFE23) may be disposed on the third light-emitting device (ED3) and the third electrode pattern (CEP3). The third organic layer TFE23 may be arranged to overlap the third light emitting area EA3 and fill the third opening OPE3. However, the third organic layer TFE23 may not overlap the first opening OPE1 and the second opening OPE2, but may be disposed only on the third opening OPE3 and the surrounding bank structure BNS.

The third encapsulation layer (TFE3) may be disposed on the second encapsulation layer (TFE2) and the first encapsulation layer (TFE1). The third encapsulation layer TFE3 may be entirely disposed on the display area DA. The third encapsulation layer (TFE3) may directly contact the upper surface of the first encapsulation layer (TFE1) exposed by the second encapsulation layer (TFE2).

According to one embodiment, the thin film encapsulation layer (TFEL) is disposed separately from each other so that the second encapsulation layer (TFE2) corresponds to each light emitting area (EA1, EA2, EA3), and the first encapsulation layer (TFE1) and the third encapsulation layer (TFE1) The encapsulation layer TFE2 may contact each other around each light emitting area EA1, EA2, and EA3. Accordingly, the encapsulation layer TFEL can independently encapsulate each light emitting area EA1, EA2, and EA3, thereby improving the encapsulation characteristics of each light emitting device ED1, ED2, and ED3.

Additionally, the encapsulation layer TFEL may be disposed on the main display area MDA and the first sub-display area SDA1, but may not be disposed on the transmission area TA. For example, the encapsulation layer TFEL may be disposed to overlap the main display area MDA and the first sub-display area SDA1, but not to overlap the transmission area TA. Each light emitting element (ED1, ED2, ED3) includes pixel electrodes (AE1, AE2, AE3), an inorganic insulating layer (ISL), a first bank layer (BN1), a second bank layer (BN2) of the bank structure (BNS), and It can be completely sealed by the encapsulation layer (TFEL). Therefore, even if the encapsulation layer TFEL is not disposed in the transmission area TA, the light emitting elements ED1, ED2, and ED3 of each light emitting area EA1, EA2, and EA3 are sealed by the inorganic films, thereby preventing external moisture. It can prevent the penetration of hyperoxygen.

The second planarization layer (PNL2) may be disposed on the encapsulation layer (TFEL). The second planarization layer PNL2 may flatten the upper surface of the display device 10 to facilitate attachment or formation of a structure disposed thereon. The second planarization layer PNL2 may be entirely disposed on the display area DA. For example, the second planarization layer PNL2 may be disposed on the main display area MDA and the first sub-display area SDA1.

The second planarization layer PNL2 may be disposed on the transmission area TA of the first sub-display area SDA1. For example, the second planarization layer PNL2 may fill the first through hole PH1 of the transmission area TA. The second flat layer PNL2 may directly contact the layers exposed on the inner peripheral surface of the first through hole PH1. For example, the second planarization layer PNL2 may directly contact the thin film transistor layer TFTL, the bank structure BNS, and a portion of the substrate SUB. Parts of the substrate SUB may be the first barrier layer BA1, the second substrate SUB2, and the second barrier layer BA2.

Additionally, the second planarization layer (PNL2) may directly contact the first planarization layer (PNL1) disposed below. For example, in the transmission area TA, the lower surface of the second flattening layer PNL2 may directly contact the upper surface of the first flattening layer PNL1. The interface of the second planarization layer PNL2 and the first planarization layer PNL1 may be aligned with the top surface of the first substrate SUB1.

As described above, the display device 10 according to one embodiment has a transmission area (TA) in the sub-display areas (SDA1, SDA2, SDA3, SDA4) overlapping with the optical devices (740, 750, 760, and 770 in FIG. 2). ), the transmittance of light incident on the optical devices (740, 750, 760, and 770 in FIG. 2) can be improved.

In addition, by independently sealing the light-emitting elements (ED1, ED2, ED3) of each light-emitting area (EA1, EA2, EA3) through inorganic films, the light-emitting elements (ED1, ED2, ED3) are prevented from deteriorating due to penetration of moisture or oxygen. can be prevented.

Hereinafter, a manufacturing process of the display device 10 according to an embodiment will be described with reference to other drawings.

8 to 22 are cross-sectional views sequentially showing the manufacturing process of a display device according to an embodiment. 8 to 22 illustrate the manufacturing process of the display device 10 shown in FIG. 6 as an example.

Referring to FIG. 8, a substrate (SUB) is formed on the mother substrate (MSUB). The mother substrate (MSUB) may be a glass substrate and may support layers to be stacked in a process described later. The substrate SUB is formed by sequentially applying and stacking a first substrate SUB1, a first barrier layer BA1, a second substrate SUB2, and a second barrier layer BA2 on the mother substrate MSUB. You can. For example, the first substrate (SUB1) and the second substrate (SUB2) can be formed by applying polyimide, and the first barrier layer (BA1) and the second barrier layer (BA2) can be formed by depositing an inorganic material. You can.

Next, a thin film transistor layer (TFTL) is formed on the second barrier layer (BA2). The thin film transistor layer (TFTL) includes a light blocking layer (BML), a buffer layer (BF), a thin film transistor (TFT), a gate insulating layer (GI), an interlayer insulating layer (ILD), a first connection electrode (CNE1), and a connection wire (CNL). ), a first via layer (VIA1), a second connection electrode (CNE2), and a second via layer (VIA2).

The light blocking layer (BML) can be formed by laminating a metal material on the second barrier layer (BA2) and patterning it through a photolithography process. The buffer layer (BF) can be formed by depositing an inorganic material on the second barrier layer (BA2) to cover the light blocking layer (BML).

A thin film transistor (TFT), a gate insulating layer (GI), and an interlayer insulating layer (ILD) are formed on the buffer layer (BF). Specifically, a semiconductor layer (ACT) is formed on the buffer layer (BF) and a gate insulating layer (GI) is formed on the semiconductor layer (ACT). A gate electrode (GE) is formed on the gate insulating layer (GI), and a portion of the semiconductor layer (ACT) is made into a conductor using the gate electrode (GE) as a mask to connect the source electrode (SE) and drain electrode (DE). form Then, an interlayer insulating layer (ILD) is formed on the gate electrode (GE) to form a thin film transistor (TFT), and then contact holes are formed penetrating the gate insulating layer (GI) and the interlayer insulating layer (ILD). A thin film transistor (TFT) may be formed in the main display area (MDA).

Next, a connection wire (CNL) is formed on the interlayer insulating layer (ILD) and a first connection electrode (CNE1) is formed. The first connection electrode CNE1 may be connected to the source electrode SE and the drain electrode DE through contact holes penetrating the gate insulating layer GI and the interlayer insulating layer ILD. Additionally, the first connection electrode CNE1 may be connected to the connection wire CNL. The connection wire CNL may be formed to extend from the main display area MDA to the first sub-display area SDA1.

Next, the first via layer (VIA1) on the first connection electrode (CNE1) is formed through a solution process such as spin coating, and the first connection electrode (CNE1) and the connection wire (CNL) are formed through the first via layer (VIA1). ) to form contact holes that expose the And a second connection electrode (CNE2) is formed on the first via layer (VIA1). The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole penetrating the first via layer VIA1. Next, a second via layer (VIA2) is formed on the second connection electrode (CNE2). The second via layer VIA2 is disposed in the main display area MDA, and a portion extends into the first sub-display area SDA1, but is not substantially formed in the first sub-display area SDA1.

Next, a plurality of pixel electrodes AE1, AE2, and AE3 are formed on the second via layer VIA2 of the main display area MDA and the first via layer VIA1 of the first sub-display area SDA1. For example, the first pixel electrode AE1 and the second pixel electrode AE2 are formed on the second via layer VIA2 in the main display area MDA, and the first pixel electrode AE1 and AE2 are formed on the second via layer VIA2 in the main display area MDA. A third pixel electrode (AE3) is formed on the via layer (VIA1). The first pixel electrode (AE1) and the second pixel electrode (AE2) are connected to the second connection electrode (CNE2) through contact holes penetrating the second via layer (VIA2), and the third pixel electrode (AE3) is connected to the second connection electrode (CNE2). 1 Connected to the connection wire (CNL) through a contact hole penetrating the via layer (VIA1).

Next, sacrificial layers (SFL1, SFL2, and SFL3) are formed on the pixel electrodes (AE1, AE2, and AE3). The sacrificial layers (SFL1, SFL2, SFL3) form a first sacrificial layer (SFL1) on the first pixel electrode (AE1), a second sacrificial layer (SFL2) on the second pixel electrode (AE2), and a third sacrificial layer (SFL2) on the first pixel electrode (AE1). A third sacrificial layer (SFL3) may be formed on the pixel electrode (AE3). The sacrificial layers (SFL1, SFL2, and SFL3) may be disposed on the pixel electrodes (AE1, AE2, and AE3), and then partially removed in a subsequent process to form a space in which the light emitting layers (EL1, EL2, and EL3) are disposed. The sacrificial layers (SFL1, SFL2, SFL3) can prevent the upper surface of the pixel electrodes (AE1, AE2, AE3) from contacting the inorganic insulating layer (ISL), which will be described later, and the sacrificial layers (SFL1, SFL2, SFL3) can be removed. Thus, a space may be formed between the pixel electrodes (AE1, AE2, AE3) and the inorganic insulating layer (ISL). In an exemplary embodiment, the sacrificial layers SFL1, SFL2, and SFL3 may include an oxide semiconductor. For example, the sacrificial layer (SFL) is made of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin oxide (IZO), etc. It can be done by including at least one.

Next, referring to FIG. 9 , an inorganic insulating material layer (ISLL), a first bank material layer (BNL1), and a second bank material layer (BNL2) are sequentially stacked on the sacrificial layers (SFL1, SFL2, and SFL3).

The inorganic insulating material layer (ISLL) is disposed to entirely cover the sacrificial layer (SFL1, SFL2, SFL3) and the thin film transistor layer (TFTL), and the first and second bank material layers (BNL1, BNL2) are inorganic insulating material layers. It can be placed to completely cover the (ISLL). The first bank material layer BNL1 may be formed directly on the inorganic insulating material layer ISLL, and the second bank material layer BNL2 may be formed directly on the first bank material layer BNL1. The bank material layers BNL1 and BNL2 may be partially etched in a subsequent process to form the bank layers BN1 and BN2 of the bank structure BNS illustrated in FIG. 6 . The first bank material layer BNL1 and the second bank material layer BNL2 may each include different metal materials.

Next, a third bank layer (BN3) is formed on the second bank material layer (BNL2). The third bank layer BN3 may be formed by applying an organic material and performing a mask process. The third bank layer BN3 may form light emitting areas EA1, EA2, and EA3, which will be described later. The third bank layer BN3 may be arranged to be spaced apart from each other on the second bank material layer BNL2. The third bank layer BN3 is formed on the second bank material layer BNL2 to expose a portion overlapping with each pixel electrode AE1, AE2, and AE3, and exposes a portion where a transmission area TA, which will be described later, will be formed. It can be formed to do so.

Next, referring to FIG. 10, a first etching process of etching the inorganic insulating material layer (ISLL) and a portion of the first and second bank material layers (BNL1 and BNL2) using the third bank layer (BN3) as a mask. (1 ^st etch) is performed to form the first to fourth holes (HOL1, HOL2, HOL3, HOL4). The inorganic insulating material layer (ISLL) may be formed into an inorganic insulating layer (ISL) through a first etching process (1 ^st etch).

The first etching process (1 ^st etching) may be performed by dry etching. As the first etching process (1 ^st etch) is performed as a dry etching process, the inorganic insulating material layer (ISLL) and the first and second bank material layers (BNL1 and BNL2) formed of different materials can be anisotropically etched. there is. In this process, the bank material layers (BNL1, BNL2) and a portion of the inorganic insulating material layer (ISLL) may be etched together to partially expose the lower sacrificial layers (SFL1, SFL2, and SFL3). The first hole HOL1 is formed in a portion overlapping with the first pixel electrode AE1, the second hole HOL2 is formed in a portion overlapping with the second pixel electrode AE2, and the third hole HOL3 may be formed in a portion overlapping with the third pixel electrode AE3. The fourth hole HOL4 may be formed in a portion where the first through hole PH1, which will be described later, will be formed.

Next, referring to FIG. 11 , a second etching process ( ^2nd etch) is performed to remove the sacrificial layers (SFL1, SFL2, and SFL3) disposed on the pixel electrodes (AE1, AE2, and AE3). In an exemplary embodiment, the sacrificial layers SFL1, SFL2, and SFL3 include an oxide semiconductor layer, and the second etching process ( ^2nd etch) may be performed as a wet etching process. In this process, as the sacrificial layers (SFL1, SFL2, and SFL3) are removed, the first and second bank material layers (BNL1, BNL2) in the first to third holes (HOL1, HOL2, and HOL3) may be isotropically etched. Among the first and second bank material layers BNL1 and BNL2, the first bank material layer BNL1 may have a faster etch rate than the other bank material layers, and the second bank material layer BNL2 may have a faster etch rate than the first bank material layer BNL2. A tip may be formed that protrudes further than the side of the layer BNL1. An undercut may be formed on the side of the first bank material layer BNL1 below the tip of the second bank material layer BNL2. Through the second etching process (2 ^nd etch), the first hole (HOL1) is formed as the first opening (OPE1), the second hole (HOL2) is formed as the second opening (OPE2), and the third hole (HOL3) ) may be formed as a third opening (OPE3). In addition, through a second etching process (2 ^nd etch), the first bank material layer BNL1 is formed as the first bank layer BN1 and the second bank material layer BNL2 is formed as the second bank layer BN2. It can be. Accordingly, a bank structure (BNS) in which the first bank layer (BN1), the second bank layer (BN2), and the third bank layer (BN3) are sequentially stacked may be formed.

In addition, the sacrificial layers (SFL1, SFL2, SFL3) are formed in the portion exposed by the first to third holes (HOL1, HOL2, HOL3) and between the inorganic insulating layer (ISL) and the pixel electrodes (AE1, AE2, AE3). Some may be removed. As a part where the sacrificial layers (SFL1, SFL2, and SFL3) are removed, a space may be formed between the pixel electrodes (AE1, AE2, and AE3) and the inorganic insulating layer (ISL) disposed thereon.

Next, referring to FIGS. 12 to 14, light emitting layers (EL1, EL2, EL3) and common electrodes (CE1, CE2, CE3) are formed on each pixel electrode (AE1, AE2, AE3).

Specifically, the first light emitting layer (EL1) and the first common electrode (CE1) are entirely deposited on the first pixel electrode (AE1) without a mask to form the first light emitting device (ED1). The first light-emitting layer EL1 and the first common electrode CE1 are formed in the first opening OPE1, and the materials forming the first light-emitting layer EL1 and the first common electrode CE1 in the deposition process are third. It can also be deposited on bank layers (BN3). The first light-emitting layer (EL1) and the first common electrode (CE1) are disconnected by the tips of the second bank layer (BN2) and the third bank layer (BN3), so that It can be patterned without a patterning process.

The first light emitting layer EL1 and the first common electrode CE1 may be formed through a deposition process. Material deposition in the first opening OPE1 may not be smooth due to the tips of the second bank layer BN2 and the third bank layer BN3. However, since the materials of the first light emitting layer (EL1) and the first common electrode (CE1) are deposited in an inclined direction rather than perpendicular to the upper surface of the substrate, the second bank layer (BN2) and the third bank layer (BN3) Deposition can also occur in areas hidden by the tip.

For example, the deposition process for forming the first light emitting layer EL1 may be performed so that materials are deposited in a direction that is not perpendicular to the top surface of the first pixel electrode AE1, for example, in a direction inclined at a first angle. . In an exemplary embodiment, deposition of material in the process of forming the light emitting layers EL1, EL2, and EL3 may be performed at an angle of 45° to 50° from the top surface of the pixel electrodes AE1, AE2, and AE3. The first light emitting layer EL1 may be formed to fill the space between the first pixel electrode AE1 and the inorganic insulating layer ISL.

The deposition process for forming the first common electrode CE1 may be performed so that materials are deposited in a direction that is not perpendicular to the top surface of the first pixel electrode AE1, for example, in a direction inclined at a second angle. In an exemplary embodiment, the deposition of material in the process of forming the first common electrode CE1 may be performed at an angle of 30° or less from the top surfaces of the pixel electrodes AE1, AE2, and AE3. The first common electrode CE1 is disposed on the first light emitting layer EL1 and may also be formed in an area hidden by the tips of the second bank layer BN2 and the third bank layer BN3. For example, the first common electrode CE1 is an area hidden by the tip TIP and may be partially disposed on the side of the first bank layer BN1. Different common electrodes (CE1, CE2, CE3), which will be described later, may be electrically connected to each other by contacting the highly conductive first bank layer (BN1).

Next, the first photo pattern PR1 is formed to cover the first opening OPE1. The first photo pattern PR1 can be formed by applying photoresist and then exposing and developing the photoresist. Then, using the first photo pattern PR1 as a mask, materials forming the first light emitting layer EL1 and the first common electrode CE1 deposited in areas other than the first photo pattern PR1 are removed. Accordingly, some of the materials forming the first light emitting layer (EL1) and the first common electrode (CE1) are deposited on the third bank layer (BN3) to form the first organic pattern (ELP1) and the first electrode pattern (CEP1) ) can be formed.

Next, the light emitting material layer (ELL) and the electrode material layer (CEL) are entirely deposited on the second pixel electrode (AE2) to form a second light emitting device including the second light emitting layer (EL2) and the second common electrode (CE2). (ED2) is formed. The second light emitting layer EL2 and the second common electrode CE2 may be formed in the second opening OPE2. The second light-emitting layer EL2 and the second common electrode CE2 are formed through the same process as the deposition process of the first light-emitting layer EL1 and the second common electrode CE2 described above, thereby forming the second bank layer BN2. Deposition can also be performed in areas hidden by the tip of the third bank layer BN3.

Next, as shown in FIG. 13, the second photo pattern PR2 is formed to cover the second opening OPE1 and deposited in areas other than the second photo pattern PR2 using the second photo pattern PR2 as a mask. Remove the light emitting material layer (ELL) and electrode material layer (CEL). A portion of the light emitting material layer ELL and the electrode material layer CEL may be deposited on the third bank layer BN3 to form the second organic pattern ELP2 and the second electrode pattern CEP2.

Next, as shown in FIG. 14, a material forming the third light emitting layer (EL3) and the third common electrode (CE3) is deposited on the entire surface of the third pixel electrode (AE3), thereby forming the third light emitting layer (EL3) and the third common electrode. A third light emitting element (ED3) including (CE3) is formed. The third light emitting layer EL3 and the third common electrode CE3 may be formed in the third opening OPE3. Although not shown, after forming the third photo pattern covering the third opening OPE3, the material forming the third light emitting layer EL3 and the third common electrode CE3 is removed and the first to third photo patterns are formed. By removal, the structure shown in FIG. 14 can be produced. Some of the materials forming the third light emitting layer (EL3) and the third common electrode (CE3) are deposited on the third bank layer (BN3) to form the third organic pattern (ELP3) and the third electrode pattern (CEP3). You can.

Next, referring to FIG. 15, a first encapsulation layer (TFE1) is formed on each light emitting device (ED1, ED2, and ED3). The first encapsulation layer (TFE1) can be formed by depositing an inorganic material. The first encapsulation layer (TFE1) may directly contact the electrode patterns (CEP1, CEP2, CEP3), the common electrode (CE1, CE2, CE3), the bank structure (BNS), and the second substrate (SUB2).

Next, referring to FIG. 16, a second encapsulation layer (TFE2) is formed on the first encapsulation layer (TFE1). The second encapsulation layer (TFE2) is formed by applying an organic material through a solution process and then through an exposure process to form a first organic layer (TFE21) overlapping with the first light-emitting device (ED1) and a second organic layer overlapping with the second light-emitting device (ED2). A third organic layer (TFE23) overlapping with (TFE22) and the third light emitting device (ED3) may be formed. Each organic layer (TFE21, TFE22, and TFE23) may be formed to fill the first to third openings (OPE1, OPE2, and OPE3). Additionally, the second encapsulation layer TFE2 is not formed in the fourth hole HOL4.

Next, referring to FIG. 17, a third encapsulation layer (TFE3) and a hard mask layer (HML) are formed on the second encapsulation layer (TFE2) and the first encapsulation layer (TFE1). The third encapsulation layer (TFE3) can be formed by depositing an inorganic material. The third encapsulation layer (TFE3) covers the second encapsulation layer (TFE2) and the first encapsulation layer (TFE1), and may directly contact the second encapsulation layer (TFE2) and the first encapsulation layer (TFE1). The third encapsulation layer (TFE3) may also be formed in the fourth hole (HOL4).

The hard mask layer (HML) may be formed on the third encapsulation layer (TFE3). The hard mask layer (HML) may be formed entirely on the third encapsulation layer (TFE3) excluding the fourth hole (HOL4). The hard mask layer (HML) may be formed of a metal oxide such as ITO or IZO.

Next, referring to FIG. 18 , a first encapsulation layer (TFE1), a third encapsulation layer (TFE3), a second barrier layer (BA2) formed in the fourth hole (HOL4) using the hard mask layer (HML) as a mask, A third etching process ( ^3rd etch) is performed to remove the second substrate (SUB2) and the first barrier layer (BA1) by etching them. The third etching process (3 ^rd etch) may be performed by dry etching. As the third etching process (3 ^rd etch) is performed as a dry etching process, the first encapsulation layer (TFE1), the third encapsulation layer (TFE3), the second barrier layer (BA2), the second substrate (SUB2), and the 1 The barrier layer BA1 may be anisotropically etched and removed. The fourth hole HOL4 may be further penetrated through the third etching process (3 ^rd etch) to form the first through hole PH1. In this process, the first encapsulation layer (TFE1), the third encapsulation layer (TFE3), the second barrier layer (BA2), the second substrate (SUB2), and the first barrier layer (BA1) are etched to form the lower first substrate ( SUB1) may be exposed. After the third etching process (3 ^rd etch) is completed, the hard mask layer (HML) is removed.

Next, referring to FIG. 19, a second planarization layer (PNL2) is formed on the third encapsulation layer (TFE3). The second planarization layer (PNL2) may be formed entirely on the third encapsulation layer (TFE3). Additionally, the second flat layer (PNL2) can be formed by applying a UV-curable resin with high transmittance through a solution process. The second flat layer (PNL2) covers the third encapsulation layer (TFE3) and may be formed to be flat by filling the first through hole (PH1). The second planarization layer PNL2 may be in direct contact with the upper surface of the first substrate SUB1 through the first through hole PH1.

Next, referring to FIG. 20, the mother substrate (MSUB) is separated from the first substrate (SUB1). The process of separating the mother substrate (MSUB) can be done through a laser lift off (LLO) process. The laser lift-off process uses a laser, and a KrF excimer laser (248 nm wavelength) can be used as the source. By irradiating the laser to the mother substrate (MSUB), the mother substrate (MSUB) can be separated from the first substrate (SUB1).

Next, referring to FIG. 21, a fourth etching process ( ^4th etch) is performed to form a second through hole (PH2) in the first substrate (SUB1). The fourth etching process ( ^4th etch) may use dry etching or laser. For dry etching, an AP plasma etching process can be used, and for laser, a laser ablation process can be used.

According to the fourth etching process ( ^4th etch), the second through hole PH2 may be formed overlapping the first through hole PH1. The lower surface of the second flat layer PNL2 may be exposed through the second through hole PH2. The width of the second through hole PH2 may gradually decrease from the upper surface of the first substrate SUB1 to the lower surface of the first substrate SUB2. The first through hole PH1 and the second through hole PH2 may form a transparent area TA in the first sub display area SDA1.

Next, referring to FIG. 22, a first planarization layer (PNL1) is formed on the lower surface of the first substrate (SUB1). The first planarization layer (PNL1) may be formed entirely on the lower part of the first substrate (SUB1). In addition, the first planarization layer (PNL1), like the second planarization layer (PNL2), has a high transmittance and can be formed by applying a UV-curable resin through a solution process. For example, the first planarization layer (PNL1) and the second planarization layer (PNL2) may include the same material. The first flat layer (PNL1) may be formed to have a flat bottom by filling the first through hole (PH1). The first planarization layer (PNL1) may directly contact the lower surface of the second planarization layer (PNL2) through the first through hole (PH1).

As described above, the display device 10 according to one embodiment can be manufactured. According to one embodiment, by forming the first and second through-holes PH1 and PH2 in the first sub-display area SDA1, the light incident on the optical devices (740, 750, 760, and 770 of FIG. 2) Transmittance can be improved.

Hereinafter, other embodiments of the display device will be described with reference to other drawings.

Figure 23 is a cross-sectional view showing a display device according to another embodiment. FIG. 23 corresponds to FIG. 6 and exemplarily shows a display device of another embodiment. Hereinafter, descriptions that overlap with those described in FIGS. 5 to 7 will be omitted and differences will be described.

Referring to FIG. 23 , the display device 10 according to one embodiment is different from the embodiments of FIGS. 6 and 7 in that the third bank layer BN3 of the bank structure BNS is omitted.

Specifically, the bank structure (BNS) may include a first bank layer (BN1) and a second bank layer (BN2) sequentially disposed on the inorganic insulating layer (ISL). The first bank layer BN1 may be a lower layer of the bank structure BNS, and the second bank layer BN2 may be an upper layer of the bank structure BNS. The bank structure BNS may include a tip TIP in which the second bank layer BN2 protrudes from the first bank layer BN1 toward the openings OPE1, OPE2, and OPE3.

First to third organic patterns (ELP1, ELP2, ELP3) and first to third electrode patterns (CEP1, CEP2, CEP3) may be disposed on the bank structure (BNS). The first to third organic patterns ELP1, ELP2, and ELP3 are each disposed on the second bank layer BN2 and may be in direct contact with the second bank layer BN2. A plurality of electrode patterns (CEP1, CEP2, and CEP3) may be disposed on the first to third organic patterns (ELP1, ELP2, and ELP3), respectively.

A thin film encapsulation layer (TFEL) may be disposed on the light emitting elements (ED1, ED2, ED3) and the bank structure (BNS). The thin film encapsulation layer (TFEL) may include a first encapsulation layer (TFE1), a second encapsulation layer (TFE2), and a third encapsulation layer (TFE3) that are sequentially stacked.

The first encapsulation layer (TFE1) is disposed to cover the light emitting elements (ED1, ED2, ED3), the bank structure (BNS), the organic patterns (ELP1, ELP2, ELP3), and the electrode patterns (CEP1, CPE2, CEP3). You can. The first encapsulation layer (TFE1) may directly contact the top surface of the second bank layer (BN2). For example, the first encapsulation layer TFE1 may directly contact the top surface of the second bank layer BN2 between the first organic pattern ELP1 and the second organic pattern ELP2. The second encapsulation layer (TFE2) may be disposed on the first encapsulation layer (TFE2), and the third encapsulation layer (TFE3) may be disposed on the first encapsulation layer (TFE2) and the second encapsulation layer (TFE2) to cover them. there is.

According to one embodiment, the bank structure BNS includes the first bank layer BN1 and the second bank layer BN2, so the third bank layer BN3 can be omitted. For example, the third bank layer BN3 may be omitted by performing a process of removing the third bank layer BN3 used as a mask after the process of FIG. 11 described above. Accordingly, by reducing the step at the top of the display device 10 due to the third bank layer BN3, the second planarization layer PNL2 can be easily planarized and the thickness of the display device 10 can be reduced.

Figure 24 is a cross-sectional view showing a display device according to another embodiment.

Referring to FIG. 24, the display device 10 according to one embodiment is described above in that the top surface of the second encapsulation layer (TFE2) and the top surface of the first encapsulation layer (TFE1) of the thin film encapsulation layer (TFEL) are aligned with each other. There is a difference from the embodiments of FIGS. 6 and 7.

Specifically, a thin film encapsulation layer (TFEL) may be disposed on the light emitting elements (ED1, ED2, ED3) and the bank structure (BNS). The thin film encapsulation layer (TFEL) may include a first encapsulation layer (TFE1), a second encapsulation layer (TFE2), and a third encapsulation layer (TFE3) that are sequentially stacked.

In this embodiment, the second encapsulation layer (TFE2) may be arranged to fill the first to third openings (OPE1, OPE2, and OPE3) formed by the bank structure (BNS). For example, the first organic layer (TFE21) of the second encapsulation layer (TFE2) fills the first opening (OPE1) disposed on the first light-emitting device (ED1), and the second organic layer (TFE22) fills the second light-emitting device (ED1). The second opening OPE2 disposed on ED2 may be filled, and the third organic layer TFE23 may fill the third opening OPE3 disposed on the third light emitting device ED3.

In this case, the top surface of the second encapsulation layer (TFE2) may be aligned with the top surface of the first encapsulation layer (TFE1) in the main display area (MDA). The top surface of the second encapsulation layer TFE2 may be the top surface of the second encapsulation layer TFE2, and the top surface of the first encapsulation layer TFE1 may be the top surface of the first encapsulation layer TFE1. Here, the top surface of the second encapsulation layer (TFE2) may be the top surface of the first organic layer (TFE21) disposed in the first opening (OPE1) and the top surface of the second organic layer (TFE22) disposed in the second opening (OPE2). . That is, the top surface of the first organic layer (TFE21) and the top surface of the second organic layer (TFE22) are mutually aligned with the top surface of the first encapsulation layer (TFE1) disposed between the first organic layer (TFE21) and the second organic layer (TFE22). You can.

Meanwhile, unlike the main display area MDA, the first sub-display area SDA1 omits the second via layer VIA2 and includes the third light-emitting device ED3, the bank structure BNS, and the first encapsulation layer TFE1. It can be placed at a lower height than the main display area (MDA). The second encapsulation layer TFE2 is formed through a solution process and is formed at the same height in the main display area MDA and the first sub-display area SDA1. Here, the height of the second encapsulation layer TFE2 may be the height measured from the substrate SUB. Accordingly, the top surface of the second encapsulation layer (TFE2) disposed on the third opening (OPE3) of the first sub-display area (SDA1) is angled in a third direction (Z-axis direction) than the top surface of the first encapsulation layer (TFE1). It can be placed protruding. That is, the top surface of the second encapsulation layer (TFE2) is not aligned with the top surface of the first encapsulation layer (TFE1).

Additionally, the thickness T1 of the second encapsulation layer TFE2 disposed in the main display area MDA may be smaller than the thickness T2 of the second encapsulation layer TFE2 disposed in the first sub-display area SDA1. there is. Here, the thickness (T1, T2) of the second encapsulation layer (TFE2) may be the length between the lowermost surface and the uppermost surface of the second encapsulation layer (TFE2).

The third encapsulation layer (TFE3) may be disposed on the first encapsulation layer (TFE1) and the second encapsulation layer (TFE2) to cover them. The third encapsulation layer (TFE3) may be in direct contact with the first encapsulation layer (TFE1) on the bank structure (BNS) and the second encapsulation layer (TFE2) on the openings (OPE1, OPE2, and OPE3). When the top surface of the second encapsulation layer (TFE2) and the top surface of the first encapsulation layer (TFE1) are aligned with each other in the main display area (MDA), the third encapsulation layer (TFE3) and the first encapsulation layer (TFE3) are aligned on the bank structure (BNS). The contact area where TFE1) is in contact can be increased. Accordingly, the encapsulation characteristics of the thin film encapsulation layer TFEL in the main display area MDA are increased, thereby preventing deterioration of the first and second light emitting devices ED1 and ED2.

Figure 25 is a cross-sectional view showing a display device according to another embodiment.

Referring to FIG. 25, in the display device 10 according to one embodiment, the top surface of the first encapsulation layer (TFE1) of the thin film encapsulation layer (TFEL) is the top surface of the second encapsulation layer (TFE2) in the main display area (MDA). The embodiment of FIGS. 6 and 7 described above is disposed to protrude further, and the top surface of the first encapsulation layer (TFE1) and the top surface of the second encapsulation layer (TFE2) in the first sub-display area (SDA1) are aligned with each other. There is a difference.

In this embodiment, the second encapsulation layer (TFE2) may be arranged to fill the first to third openings (OPE1, OPE2, and OPE3) formed by the bank structure (BNS). For example, the first organic layer (TFE21) of the second encapsulation layer (TFE2) fills the first opening (OPE1) disposed on the first light-emitting device (ED1), and the second organic layer (TFE22) fills the second light-emitting device (ED1). The second opening OPE2 disposed on ED2 may be filled, and the third organic layer TFE23 may fill the third opening OPE3 disposed on the third light emitting device ED3.

In this case, the top surface of the first encapsulation layer TFE1 may be disposed to protrude more in the direction toward the first planarization layer PNL1 than the top surface of the second encapsulation layer TFE2 in the main display area MDA. The top surface of the second encapsulation layer TFE2 may be the top surface of the second encapsulation layer TFE2, and the top surface of the first encapsulation layer TFE1 may be the top surface of the first encapsulation layer TFE1. Here, the top surface of the second encapsulation layer (TFE2) may be the top surface of the first organic layer (TFE21) disposed in the first opening (OPE1) and the top surface of the second organic layer (TFE22) disposed in the second opening (OPE2). . Additionally, the top surface of the first encapsulation layer (TFE1) may be the top surface of the first encapsulation layer (TFE1) disposed on the bank structure (BNS). That is, the top surface of the first encapsulation layer (TFE1) may be disposed to protrude further in the third direction (Z-axis direction) than the top surface of the first organic layer (TFE21) and the top surface of the second organic layer (TFE22). As another example, the top surface of the first encapsulation layer (TFE1) may be disposed closer to the second planarization layer (PNL2) than the top surface of the first organic layer (TFE21) and the top surface of the second organic layer (TFE22).

Meanwhile, unlike the main display area MDA, the first sub-display area SDA1 omits the second via layer VIA2 and includes the third light-emitting device ED3, the bank structure BNS, and the first encapsulation layer TFE1. It can be placed at a lower height than the main display area (MDA). The second encapsulation layer TFE2 is formed through a solution process and is formed at the same height in the main display area MDA and the first sub-display area SDA1. Here, the height of the second encapsulation layer TFE2 may be the height measured from the substrate SUB. Accordingly, the top surface of the second encapsulation layer TFE2 disposed on the third opening OPE3 of the first sub-display area SDA1 may be aligned with the top surface of the first encapsulation layer TFE1.

Additionally, the thickness T1 of the second encapsulation layer TFE2 disposed in the main display area MDA may be smaller than the thickness T2 of the second encapsulation layer TFE2 disposed in the first sub-display area SDA1. there is. Here, the thickness (T1, T2) of the second encapsulation layer (TFE2) may be the length between the lowermost surface and the uppermost surface of the second encapsulation layer (TFE2). For example, the thickness T1 of the first organic layer TFE21 and the second organic layer TFE22 may be smaller than the thickness of the third organic layer TFE23.

The third encapsulation layer (TFE3) may be disposed on the first encapsulation layer (TFE1) and the second encapsulation layer (TFE2) to cover them. The third encapsulation layer (TFE3) may be in direct contact with the first encapsulation layer (TFE1) on the bank structure (BNS) and the second encapsulation layer (TFE2) on the openings (OPE1, OPE2, and OPE3). In the main display area (MDA), the top surface of the first encapsulation layer (TFE1) protrudes more than the top surface of the second encapsulation layer (TFE2), and in the first sub-display area (SDA1), the first encapsulation layer (TFE1) and the second encapsulation layer (TFE1) protrude more. When the top surfaces of the layers TFE2 are aligned with each other, the contact area between the third encapsulation layer TFE3 and the first encapsulation layer TFE1 on the bank structure BNS may be increased. Accordingly, the encapsulation characteristics of the thin film encapsulation layer (TFEL) in the main display area (MDA) and the first sub-display area (SDA1) increase, preventing the first to third light emitting elements (ED1, ED2, and ED3) from being deteriorated. It can be prevented.

Figure 26 is a cross-sectional view showing a display device according to another embodiment.

Referring to FIG. 26 , this embodiment differs from the embodiments of FIGS. 6 and 7 in that the top surface of the second planarization layer (PNL2) is aligned with the top surface of the third encapsulation layer (TFE3).

Specifically, the second planarization layer (PNL2) may be disposed on the thin film encapsulation layer (TFEL). The second planarization layer PNL2 may be disposed on the main display area MDA on the third encapsulation layer TFE3. For example, the second planarization layer PNL2 may be disposed between the first organic layer TFE21 and the second organic layer TFE22 of the second encapsulation layer TFE2. The second planarization layer PNL2 may be arranged to fill the space formed by the first organic layer TFE21 and the second organic layer TFE22 being spaced apart from each other. Additionally, the second planarization layer PNL2 may be disposed on the opening area TA of the first sub-display area SDA1. For example, the second planarization layer PNL2 may be disposed on the first planarization layer PNL1 disposed in the opening area TA and may be disposed to fill the first through hole PH. Additionally, the second planarization layer PNL2 may not be disposed in the remaining area of the first sub-display area SDA1 except for the opening area TA.

According to one embodiment, the top surface of the second planarization layer (PNL2) may be aligned with the top surface of the third encapsulation layer (TFE3). The top surface of the third encapsulation layer (TFE3) may be the top surface of the third encapsulation layer (TFE3). The height of the second planarization layer PNL2 disposed in the main display area MDA and the opening area TA may be the same. Here, the height of the second planarization layer (PNL2) may be the height measured from the substrate (SUB) to the top surface of the second planarization layer (PNL2).

Additionally, the thickness T3 of the second planarization layer PNL2 disposed in the main display area MDA may be smaller than the thickness T4 of the second planarization layer PNL2 disposed in the opening area TA. Here, the thickness T3 and T4 of the second flattening layer PNL2 may be the length between the lowermost surface and the uppermost surface of the second flattening layer PNL2.

The second planarization layer (PNL2) serves to planarize the upper part of the display device 10. According to one embodiment, the top surface of the second planarization layer (PNL2) and the top surface of the third encapsulation layer (TFE3) are formed to be aligned with each other, so that the second planarization layer (PNL2) is formed to a minimum thickness, thereby forming the display device 10. The thickness can be reduced.

Figure 27 is a cross-sectional view showing a display device according to another embodiment.

Referring to FIG. 27, in the display device 10 according to one embodiment, the width W2 of the second through hole PH2 of the first substrate SUB1 is greater than the width W3 of the first through hole PH1. It is different from the embodiments of FIGS. 6 and 7 described above in that it is larger.

Specifically, a first through hole (PH1) and a second through hole (PH2) may be disposed in the substrate (SUB). The first through hole PH1 may be a hole that penetrates a portion of the upper thin film encapsulation layer (TFEL), thin film transistor layer (TFTL), and substrate (SUB). The second through hole PH2 may be a hole that penetrates the first substrate SUB1. The first through hole PH1 and the second through hole PH2 are disposed to overlap the transmission area TA and may correspond to the transmission area TA. The first through-hole PH1 may be disposed to be filled with the second planarization layer (PNL2), and the second through-hole (PH2) may be disposed to be filled with the first planarization layer (PNL1).

According to one embodiment, the width W2 of the second through hole PH2 may be larger than the width W3 of the first through hole PH1. The second through hole (PH2) exposes the lower surface of the first barrier layer (BA1), and the lower surface of the first barrier layer (BA1) exposed by the second through hole (PH2) is exposed to the first planarization layer (PNL1) and You can contact them directly.

The second through hole PH2 may be formed after forming the first through hole PH1. In order to increase the light transmittance of the opening area TA, the alignment of the first through hole PH1 and the second through hole PH2 is important. In one embodiment, the width W2 of the second through hole PH2 is formed to be larger than the width W1 of the first through hole PH1, thereby forming a gap between the first through hole PH1 and the second through hole PH2. By facilitating alignment, the light transmittance of the opening area (TA) can be increased.

Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will be able to understand it. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

10: Display device SUB: Board
TFTL: Thin film transistor layer EML: Light emitting element layer
TFEL: Thin film encapsulation layer BNS: Bank structure
PNL1, 2: first and second flat layers PH1, 2: first and second through holes
TA: Aperture area MDA: Main display area

Claims (30)

a substrate including a sub-display area including a transparent area and a main display area other than the sub-display area;
a thin film transistor layer disposed on the main display area and the sub-display area of the substrate;
a light emitting device layer disposed on the thin film transistor layer;
a thin film encapsulation layer disposed on the light emitting device layer;
a first through hole and a second through hole disposed on the transmission area, penetrating the transmission area and overlapping each other;
a first planar layer disposed under the substrate, disposed in the main display area and the transmission area, and filling the second through hole; and
a second planar layer disposed on the thin film encapsulation layer, disposed in the main display area and the transmission area, and filling the first through hole;
The first planar layer and the second planar layer are in contact with each other in the transmission area. According to claim 1,
The first through hole penetrates the thin film transistor layer disposed in the sub-display area and a portion of the substrate, and the second through hole penetrates the remaining portion of the substrate. According to clause 2,
The substrate includes a first substrate disposed on the first planarization layer, a first barrier layer disposed on the first substrate, a second substrate disposed on the first barrier layer, and a first substrate disposed on the second substrate. It includes a second barrier layer,
The first through hole penetrates the first barrier layer, the second substrate, and the second barrier layer, and the second through hole penetrates the first substrate. According to clause 3,
The first planarization layer includes a protrusion that protrudes toward the second planarization layer through the second through hole, and the width of the protrusion gradually decreases as it becomes adjacent to the second planarization layer. According to clause 3,
A display device in which the width of the second through hole gradually increases from the top surface of the first substrate to the bottom surface of the first substrate. According to claim 1,
Further comprising at least one optical device overlapping the transmission area,
The display device wherein the at least one optical device overlaps the first through hole and the second through hole. According to claim 1,
The display device wherein the thin film transistor layer, the light emitting device layer, and the thin film encapsulation layer do not overlap with the transmission area. According to claim 1,
The light emitting device layer includes a pixel electrode disposed on the thin film transistor layer, a light emitting layer disposed on the pixel electrode, and a common electrode disposed on the light emitting layer,
The thin film encapsulation layer is disposed on the common electrode to encapsulate the light emitting device layer. According to clause 8,
an inorganic insulating layer disposed on the thin film transistor layer and covering an edge of the pixel electrode; and
The display device further includes a bank structure disposed on the inorganic insulating layer and including openings exposing the pixel electrode. According to clause 9,
The bank structure includes a first bank layer disposed on the inorganic insulating layer, and a second bank layer disposed on the first bank layer and including a tip protruding from a side wall of the opening than the first bank layer. display device. According to claim 10,
The display device wherein the light emitting layer and the common electrode contact a sidewall of the first bank layer below the tip of the second bank layer. According to claim 10,
The bank structure further includes a third bank layer disposed on the second bank layer. According to claim 12,
an organic pattern disposed on the third bank layer surrounding the opening and including the same material as the light emitting layer; and
The display device further includes an electrode pattern disposed on the organic pattern and including the same material as the common electrode. According to clause 9,
The thin film encapsulation layer includes a first encapsulation layer;
a second encapsulation layer disposed on the first encapsulation layer; and
It includes a third encapsulation layer disposed on the second encapsulation layer,
The first encapsulation layer and the third encapsulation layer are in contact with each other in a region surrounding the opening. According to claim 14,
The first encapsulation layer and the third encapsulation layer are in contact with each other in an area surrounding the transparent area. Board;
a thin film transistor layer disposed on the substrate;
a light emitting device layer disposed on the thin film transistor layer;
a thin film encapsulation layer disposed on the light emitting device layer;
first and second through holes passing through the substrate and the thin film transistor layer and overlapping each other;
a first planar layer disposed under the substrate and filling the second through hole; and
It is disposed on the thin film encapsulation layer, and includes a second planarization layer that fills the first through hole and is in contact with the first planarization layer,
The thin film transistor layer, the light emitting device layer, and the thin film encapsulation layer do not overlap the first through hole and the second through hole. According to claim 16,
The light emitting device layer includes a pixel electrode disposed on the thin film transistor layer, a light emitting layer disposed on the pixel electrode, and a common electrode disposed on the light emitting layer,
The thin film encapsulation layer is disposed on the common electrode to encapsulate the light emitting device layer. According to claim 17,
an inorganic insulating layer disposed on the thin film transistor layer and covering an edge of the pixel electrode; and
The display device further includes a bank structure disposed on the inorganic insulating layer and including openings exposing the pixel electrode. According to clause 18,
The thin film encapsulation layer includes a first encapsulation layer;
a second encapsulation layer disposed on the first encapsulation layer and filling the opening; and
A display device including a third encapsulation layer disposed on the second encapsulation layer. According to clause 19,
The display device wherein the top surface of the second encapsulation layer protrudes in a direction toward the first planarization layer rather than the top surface of the first encapsulation layer. According to clause 19,
A display device in which a top surface of the second encapsulation layer is aligned with a top surface of the first encapsulation layer. According to clause 19,
The display device wherein the top surface of the first encapsulation layer protrudes in a direction toward the first planarization layer rather than the top surface of the second encapsulation layer. According to clause 19,
A display device in which a top surface of the second planar layer is aligned with a top surface of the third encapsulation layer. Forming a substrate on a mother substrate and forming a thin film transistor layer on the substrate;
forming a pixel electrode on the thin film transistor layer and a sacrificial layer on the pixel electrode;
sequentially stacking an inorganic insulating material layer, a first bank material layer, and a second bank material layer on the pixel electrode;
A third bank layer is formed on the second bank material layer, and a first etch process is performed using the third bank layer as an etch mask to expose an opening overlapping the pixel electrode and the substrate. forming a through hole;
performing a second etching process using the third bank layer as an etch mask to form a first bank layer and a second bank layer having a tip protruding from the first bank layer;
forming a light emitting layer and a common electrode on the pixel electrode;
sequentially forming a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer on the common electrode;
forming a hard mask layer on the third encapsulation layer and performing a third etching process to etch a portion of the substrate exposed by the first through hole;
forming a first planar layer on the substrate and the third encapsulation layer;
removing the mother substrate and performing a fourth etching process to etch the remainder of the substrate to form a second through hole overlapping the first through hole; and
A method of manufacturing a display device including forming a second planar layer on a lower surface of the substrate. According to clause 24,
Further comprising removing the sacrificial layer after the first etching process,
The first etching process is a dry etching process. According to clause 24,
The second etching process is a wet etching process, and the first bank material layer has an etch rate faster than the second bank material layer. According to clause 24,
A method of manufacturing a display device in which the light emitting layer and the common electrode are disconnected from the opening by the tip of the second bank layer. According to clause 24,
The hard mask layer is formed in a region other than the region where the first through hole is formed, and is removed after the third etching process is performed. According to clause 24,
The substrate is formed by sequentially forming a first substrate, a first barrier layer, a second substrate, and a second barrier layer on the mother substrate,
The first through hole is formed by etching the second barrier layer in the first etching process and etching the second substrate and the first barrier layer in the third etching process,
The method of manufacturing a display device in which the second through hole is formed by etching the first substrate in the fourth etching process. According to clause 29,
The first planarization layer is formed on the encapsulation layer and fills the first through hole, and the second planarization layer is formed on the lower surface of the first substrate and fills the second through hole. Manufacturing method.

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