KR20240050243A - Semiconductor memory device and electronic system including the same - Google Patents

Abstract

A semiconductor memory device and an electronic system including the same are provided. A semiconductor memory device includes a substrate including a first region on which peripheral circuits are formed and a second region on which memory cell blocks are formed, the first region of the substrate being defined, and extending in first to third directions different from each other and being spaced at 90 degrees from each other. A first active region including 1_1 to 1_3 extensions forming a large angle, and a first pass transistor circuit for transmitting a driving signal to apply an operating voltage to the memory cell blocks, wherein the first pass The transistor circuit includes 1_1 to 1_3 gate structures respectively disposed on the 1_1 to 1_3 extensions, and first shared source/drain disposed between the 1_1 to 1_3 gate structures.

Description

Semiconductor memory device and electronic system including the same {SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME}

The present invention relates to semiconductor memory devices and electronic systems including the same. More specifically, the present invention relates to a semiconductor memory device including pass transistors sharing one source/drain region and an electronic system including the same.

Recently, with the multi-functionalization of information and communication devices, there is a demand for higher capacity and higher integration of memory devices. As the size of memory cells is reduced for high integration, operation circuits and/or wiring structures included in the memory device for operation and electrical connection are becoming more complex. Accordingly, there is a demand for a memory device that improves the degree of integration of the memory device and has excellent electrical characteristics.

In order to improve the integration of the memory device, the number of word lines stacked perpendicular to the substrate may be increased. Accordingly, the number of pass transistors connected to word lines also increases, which may cause problems such as an increase in the size of the memory device and deterioration in characteristics.

The technical problem to be solved by the present invention is to provide a semiconductor memory device with improved performance and reliability.

Another technical problem to be solved by the present invention is to provide an electronic system including a semiconductor memory device with improved performance and reliability.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor memory device according to some embodiments for achieving the above technical problem includes a substrate including a first region on which peripheral circuits are formed and a second region on which memory cell blocks are formed, the first region of the substrate being defined, and different A first active region including 1_1 to 1_3 extensions extending in first to third directions to form an angle greater than 90 degrees to each other, and a first active region for transmitting a driving signal so that an operating voltage is applied to the memory cell blocks. A 1-pass transistor circuit, wherein the first pass transistor circuit includes 1_1 to 1_3 gate structures disposed on the 1_1 to 1_3 extension portions, respectively, and a first gate structure disposed between the 1_1 to 1_3 gate structures. 1 Contains shared source/drain.

A semiconductor memory device according to some embodiments for achieving the above technical problem includes first surfaces each extending in first and second horizontal directions perpendicular to each other, and a memory cell area disposed on the first surface. A second substrate including a first substrate and a second surface under the first substrate and having a first peripheral circuit area configured to receive a block selection signal and transmit a driving signal to the memory cell area, The first peripheral circuit area is disposed between first to third gate structures spaced apart from each other on the first active region extending in first to third directions that are not parallel to each other, and the first to third gate structures. It includes a first shared drain.

An electronic system according to some embodiments for achieving the other technical problems includes a semiconductor memory device including a main substrate, a first substrate on which peripheral circuits are formed on the main substrate, and a second substrate on which memory cells are formed, and A controller electrically connected to the semiconductor memory device on a main substrate, wherein the semiconductor memory device is defined within the first substrate and extends in first to third directions, forming an angle greater than 90 degrees to each other. an active region including first to third extensions forming an active region, and a pass transistor circuit that transmits a driving signal so that an operating voltage is applied to the memory cells, wherein the pass transistor circuit includes the first to third extensions. It includes first to third gate structures and shared source/drain between the first to third gate structures.

Specific details of other embodiments are included in the detailed description and drawings.

1 is a block diagram showing a semiconductor memory device according to some embodiments.
FIG. 2 is a diagram schematically showing a semiconductor memory device according to some embodiments.
3 is a diagram schematically showing a memory cell array according to some embodiments.
4 is a diagram illustrating a row decoder, a pass transistor circuit, and a memory cell block according to some embodiments.
Figure 5 is a circuit diagram illustrating a pass transistor and a memory cell block according to some embodiments.
Figure 6 is a layout diagram for explaining a pass transistor and a memory cell block according to some embodiments.
FIG. 7 is an enlarged view of the pass transistor of FIG. 6.
FIG. 8 is a schematic cross-sectional view taken along line A-A' of FIG. 6.
9 to 12 are various layout diagrams for explaining the arrangement structure of pass transistors according to some embodiments.
FIG. 13 is a schematic diagram illustrating a non-volatile memory device including a semiconductor memory device according to some embodiments.
FIGS. 14 and 15 are various enlarged views for explaining the R region of FIG. 13.
FIG. 16 is a schematic diagram illustrating a non-volatile memory device including a semiconductor memory device according to some embodiments.
FIG. 17 is a block diagram illustrating an electronic system including a semiconductor memory device according to some embodiments.
FIG. 18 is a schematic perspective view illustrating an electronic system including a semiconductor memory device according to some embodiments.
FIG. 19 is a schematic cross-sectional view taken along II of FIG. 18.

Hereinafter, a semiconductor memory device according to example embodiments will be described with reference to FIGS. 1 to 8 .

1 is a block diagram illustrating a semiconductor memory device according to some embodiments.

Referring to FIG. 1 , the semiconductor memory device 10 may include a memory cell array 100 and a peripheral circuit 200. The peripheral circuit 200 may include a pass transistor circuit 210, a row decoder 220, a control logic circuit 230, and a page buffer 240. Although not specifically shown, the peripheral circuit 200 may further include a voltage generator, a data input/output circuit, an input/output interface, a temperature sensor, a command decoder, or an address decoder. In some embodiments, semiconductor memory device 10 may be a non-volatile memory device.

The memory cell array 100 may be connected to the pass transistor circuit 210 through word lines (WL), string select lines (SSL), and ground select lines (GSL), and through bit lines (BL). It may be connected to the page buffer 240. The memory cell array 100 may include a plurality of memory cells. For example, the memory cells may be NAND flash memory cells. However, the present invention is not limited thereto, and in some other embodiments, the plurality of memory cells may be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

In some embodiments, the memory cell array 100 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings, each NAND string being a word stacked vertically on a substrate. It may include memory cells each connected to lines. However, the present invention is not limited thereto, and in some other embodiments, the memory cell array 100 may include a two-dimensional memory cell array. In this case, the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

The control logic circuit 230 programs data into the memory cell array 100, reads data from the memory cell array 100, or reads data from the memory cell array 100 based on the command (CMD), address (ADDR), and control signal (CTRL). Alternatively, various control signals for erasing data stored in the memory cell array 100 may be generated. For example, the control logic circuit 230 may output a row address (X-ADDR) and a column address (Y-ADDR). Accordingly, the control logic circuit 230 can generally control various operations within the semiconductor memory device 10.

The row decoder 220 may output a block selection signal for selecting one of a plurality of memory blocks to the block selection signal lines BS in response to the row address (X-ADDR). Additionally, in response to the row address (X-ADDR), the row decoder 220 sends a word line drive signal to select one of the word lines (WL) of the selected memory block to the word line drive signal lines (SI). Outputs a string selection line driving signal for selecting one of the string selection lines (SSL) to the string selection line driving signal lines (SS), and a ground for selecting one of the ground selection lines (GSL). The selection line driving signal can be output to the ground selection line driving signal lines (GS).

The page buffer 240 may select some of the bit lines BL in response to the column address Y-ADDR. Specifically, the page buffer 240 may operate as a write driver or a sense amplifier depending on the operation mode.

The pass transistor circuit 210 outputs a low signal through block select signal lines (BS), string select line drive signal lines (SS), word line drive signal lines (SI), and ground select line drive signal lines (GS). It may be connected to the decoder 220. String selection line driving signal lines (SS), word line driving signal lines (SI), and ground selection line driving signal lines (GS) may be referred to as “driving signal lines.” The pass transistor circuit 210 may include a plurality of pass transistors (eg, PTR1_1 to PTR6_3 in FIG. 4). A plurality of pass transistors (e.g., PTR1_1 to PTR6_3 in FIG. 4) may be controlled by block selection signals received through block selection signal lines BS, string selection line driving signals, and word line. Driving signals and ground selection lines Driving signals may be provided to string selection lines (SSL), word lines (WL), and ground selection lines (GSL), respectively. In FIG. 4, the number of a plurality of pass transistors (e.g., PTR1_1 to PTR6_1 in FIG. 4) included in one pass transistor group is exemplarily shown as 6, but the number of pass transistors of the present invention is 6. It is not limited.

The pass transistor circuit 210 may include a plurality of pass transistor groups corresponding to a plurality of memory cell blocks adjacent to each other. For example, the pass transistor circuit 210 includes three pass transistor groups (211, 212, and 213 in FIG. 4) respectively corresponding to three memory cell blocks (BLK1, BLK2, and BLK3 in FIG. 4) adjacent to each other. It can be included.

With the development of semiconductor processes, as the number of memory cells arranged in the memory cell array 100 increases, that is, as the number of word lines WL stacked in the vertical direction increases, the number of word lines WL increases. The number of pass transistors to be driven increases, and accordingly, the area occupied by the pass transistor circuit 210 increases. According to some embodiments, the peripheral circuit 200 may be disposed above or below the memory cell array 100 in a vertical direction. Accordingly, since the area where the pass transistor circuit 210 is disposed overlaps the word lines WL in the vertical direction, an increase in the chip size of the semiconductor memory device 10 can be prevented despite an increase in the number of pass transistors. This will be described in more detail with reference to FIG. 2.

FIG. 2 is a diagram schematically showing a semiconductor memory device according to some embodiments.

Referring to FIGS. 1 and 2 together, the semiconductor memory device 10 may include a first semiconductor layer (S1) and a second semiconductor layer (S2), and the first semiconductor layer (S1) may be a second semiconductor layer. It can be stacked in a direction (Z) perpendicular to (S2). Specifically, the second semiconductor layer S2 may be disposed below the first semiconductor layer S1 in the vertical direction (Z). In some embodiments, the memory cell array 100 may be formed in the first semiconductor layer S1, and the peripheral circuit 200 may be formed in the second semiconductor layer S2. Accordingly, the semiconductor memory device 10 may have a structure in which the memory cell array 100 is disposed on top of the peripheral circuit, that is, a COP (Cell Over Periphery) structure.

The first semiconductor layer S1 may include a cell area (CA) and a stair area (SA), and a plurality of memory cells may be disposed in the cell area (CA). In the first semiconductor layer S1, a plurality of word lines WL may extend in the first horizontal direction (X), and a plurality of bit lines BL may extend in the second horizontal direction (Y). One end of the plurality of word lines WL may be implemented in a staircase shape. In some embodiments, an area in the first semiconductor layer S1 including a plurality of step-shaped word lines WL may be referred to as a “staircase area” (SA) or a “word line extension area.” .

The second semiconductor layer S2 may include a substrate, and a peripheral circuit 200 may be formed in the second semiconductor layer S2 by forming semiconductor devices such as transistors and patterns for wiring the devices on the substrate. You can. After the peripheral circuit 200 is formed in the second semiconductor layer S2, the first semiconductor layer S1 including the memory cell array 100 may be formed, and the word lines of the memory cell array 100 ( Patterns may be formed to electrically connect the bit lines (WL) and bit lines (BL) and the peripheral circuit 200 formed in the second semiconductor layer (S2). The second semiconductor layer S2 may include a first logic area LR1 corresponding to the step area SA and a second logic area LR2 corresponding to the cell area CA. In some embodiments, the pass transistor circuit 210 may be disposed in the first logic region LR1, but the present invention is not limited thereto.

As described above, according to some embodiments, the semiconductor memory device 10 may have a COP structure, and the pass transistor circuit 210 may be disposed below the step area SA. In this case, pass transistors included in different memory cell blocks and connected to word lines arranged at the same level may be placed adjacent to each other. However, the present invention is not limited thereto, and the semiconductor memory device 10 may have a structure other than the COP structure. In this case, the pass transistor circuit 210 may be disposed adjacent to the memory cell array 100 in the horizontal direction.

3 is a diagram schematically showing a memory cell array according to some embodiments.

Referring to FIG. 3, the memory cell array 100 may include a plurality of memory cell blocks BLK1 to BLKi (here, i may be a positive integer). Each of the plurality of memory cell blocks BLK1 to BLKi may have a three-dimensional structure (or vertical structure). Specifically, each of the plurality of memory cell blocks BLK1 to BLKi may include a plurality of NAND strings extending along the vertical direction (Z). At this time, a plurality of NAND strings may be provided spaced apart by a specific distance along the first and second horizontal directions (X, Y). A plurality of memory cell blocks (BLK1 to BLKi) may be selected by a row decoder (220 in FIG. 1). For example, the row decoder 220 may select a memory cell block corresponding to a block address among a plurality of memory cell blocks BLK1 to BLKi.

4 is a diagram illustrating a row decoder, a pass transistor circuit, and a memory cell block according to some embodiments.

Referring to FIG. 4, the semiconductor memory device 10 may include a pass transistor circuit 210, and the pass transistor circuit 210 may include a plurality of pass transistor groups each corresponding to a plurality of memory cell blocks. You can. Each of the first to third memory cell blocks (BLK1, BLK2, BLK3) includes a ground selection line (GSL), a plurality of word lines (WL0 to WLm, where m is a positive integer), and a string selection line (SSL). may include.

The row decoder 220 may include a block decoder 221 and a drive signal line decoder 222. The pass transistor circuit 210 includes a first pass transistor group 211 corresponding to the first memory cell block (BLK1), a second pass transistor group 212 corresponding to the second memory cell block (BLK2), and a third memory. It may include a third pass transistor group 213 corresponding to the cell block BLK3. The first pass transistor group 211 may include a plurality of first pass transistors (PTR1_1 to PTR6_1), and the second pass transistor group 212 may include a plurality of second pass transistors (PTR1_2 to PTR6_2). The third pass transistor group 213 may include a plurality of third pass transistors (PTR1_3 to PTR6_3).

The block decoder 221 is connected to the first pass transistor group 211 through the first block selection signal line BS1 and to the second pass transistor group 212 through the second block selection signal line BL2. and can be connected to the third pass transistor group 213 through the third block selection signal line BL3.

The first block selection signal line BS1 may be connected to the gates of the plurality of first pass transistors PTR1_1 to PTR6_1. For example, when the first block selection signal provided through the first block selection signal line BS1 is activated, the plurality of first pass transistors (PTR1_1 to PTR6_1) are turned on, and accordingly, the first memory cell block (BLK1) may be selected.

The second block selection signal line BS2 may be connected to the gates of the plurality of second pass transistors PTR1_2 to PTR6_2. For example, when the second block selection signal provided through the second block selection signal line BS2 is activated, the plurality of second pass transistors (PTR1_2 to PTR6_2) are turned on, and accordingly, the second memory cell block (BLK2) may be selected.

Additionally, the third block selection signal line BS3 may be connected to the gates of the plurality of third pass transistors PTR1_3 to PTR6_3. For example, when the third block selection signal provided through the third block selection signal line BS3 is activated, the plurality of third pass transistors (PTR1_3 to PTR6_3) are turned on, and accordingly, the third memory cell block (BLK3) may be selected.

The driving signal line decoder 222 passes the string select line driving signal line (SS), the word line driving signal lines (SI0 to SIm), and the ground selecting line driving signal line (GS) to pass transistor groups 211 and 212. , 213). Specifically, the string selection line driving signal line (SS), the word line driving signal lines (SI0 to SIm), and the ground selection line driving signal line (GS) are connected to a plurality of pass transistors (PTR1_1 to PTR6_1, PTR1_2 to PTR6_2, It can be connected to the drains of PTR1_3 to PTR6_3, respectively.

The first pass transistor group 211 may be connected to the first memory cell block BLK1 through a ground select line (GSL), a plurality of word lines (WL0 to WLm), and a string select line (SSL). The first pass transistor (PTR1_1) of the first pass transistor group 211 may be connected between the string selection line (driving signal line SS) and the string selection line (SSL). The second to fifth pass transistors (PTR2_1 to PTR5_1) of the first pass transistor group 211 may be respectively connected between the word line driving signal lines (SI0 to SIm) and the plurality of word lines (WL0 to WLm). there is. The sixth pass transistor (PTR6_1) of the first pass transistor group 211 may be connected between the ground selection line (driving) signal line (GS) and the ground selection line (GSL).

For example, when the first block selection signal is activated, the pass transistors (PTR1_1 to PTR6_1) of the first pass transistor group 211 are connected to the ground selection line driving signal line (GS) and the word line driving signal lines (SI0 to SI0). SIm), and the driving signals provided through the string selection line driving signal line (SS) can be provided to the ground selection line (GSL), the plurality of word lines (WL0 to WLm), and the string selection line (SSL), respectively. there is. Since the description of the first pass transistor group 211 can also be applied to the second and third pass transistor groups 212 and 213, duplicate descriptions will be omitted.

Figure 5 is a circuit diagram illustrating a pass transistor and a memory cell block according to some embodiments.

Referring to FIG. 5 , the 1st pass transistor group 211a may correspond to an implementation example of any one of the first to third pass transistor groups 211, 212, and 213 of FIG. 4. In some embodiments, the first memory cell block BLK1a may correspond to an implementation example of any one of the first to third memory cell blocks BLK1, BLK2, and BLK3.

The first memory cell block (BLK1a) includes a plurality of NAND strings (NS11 to NS33), a plurality of word lines (WL0 to WLm), a plurality of bit lines (BL0 to BL2), and a plurality of ground selection lines (GSL0). to GSL2), a plurality of string selection lines (SSL0 to SSL2), and a common source line (CSL). Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines are not limited to those shown and may vary depending on the embodiment.

Among the plurality of bit lines (BL0 to BL2), NAND strings (NS11, NS21, NS31) are provided between the first bit line (BL0) and the common source line (CSL), and are common to the second bit line (BL1). NAND strings (NS12, NS22, NS32) are provided between the source lines (CSL), and NAND strings (NS13, NS23, NS33) are provided between the third bit line (BL2) and the common source line (CSL). You can. Each NAND string (eg, NS33) may include a string select transistor (SST), a plurality of memory cells (MCs), and a ground select transistor (GST) connected in series.

The string select transistor (SST) may be connected to the corresponding string select line (SSL0 to SSL2). Each of the plurality of memory cells MCs may be connected to corresponding word lines WL0 to WLm. The ground select transistor (GST) may be connected to the corresponding ground select line (GSL0 to GSL2). The string select transistor (SST) may be connected to the corresponding bit lines (BL0 to BL2), and the ground select transistor (GST) may be connected to the common source line (CSL).

The 1a pass transistor group 211a includes pass transistors (PTR6a_1a to PTR6a_1c) respectively connected to the ground selection lines (GSL0 to GSL2) and pass transistors (PTR5a_1 to PTR2a_1) respectively connected to the word lines (WL0 to WLm). ), and pass transistors (PTR1a_1a to PTR1a_1c) respectively connected to the string selection lines (SSL0 to SSL2). The pass transistors (PTR6a_1a to PTR6a_1c, PTR5a_1 to PTR2a_1, and PTR1a_1a to PTR1a_1c) may be turned on according to the 1a block selection signal provided along the 1a block select signal line BS1a, and the string select line driving signal line SS0 to SS2), word line driving signal lines (SI0 to SIm), and ground selection line driving signal lines (GS0 to GS2), string selection lines (SSL0 to SSL2), a plurality of word lines. (WL0 to WLm), and ground selection lines (GSL0 to GSL2), respectively.

Figure 6 is a layout diagram for explaining a pass transistor and a memory cell block according to some embodiments. FIG. 7 is an enlarged view of the pass transistor of FIG. 6. Figure 8 is a schematic cross-sectional view taken along line A-A' of Figure 6.

Referring to FIGS. 6 to 8 , a semiconductor memory device according to some embodiments includes a first substrate 100, a first active region A1, a first pass transistor circuit TR1, and 1_1 to 1_3 gate structures ( G1_1 to G1_3), 1_1 to 1_3 individual source/drain (S1_1 to S1_3), first shared source/drain (D1), 1_1 to 1_3 individual source/drain contact (SC1_1 to SC1_3), first shared source /drain contact (DC1), second active region (A2), second pass transistor circuit (TR2), 2_1 to 2_3 gate structures (G2_1 to G2_3), 2_1 to 2_3 individual source/drain (S2_1 to S2_3) ), a second shared source/drain (D2), 2_1 to 2_3 individual source/drain contacts (SC2_1 to SC2_3), and a second shared source/drain contact (DC2).

In some embodiments, a shared source/drain may be referred to as a shared drain and individual sources/drains may be referred to as sources.

The first substrate 100 may include a base substrate and an epitaxial layer grown on the base substrate, but is not limited thereto. For example, the first substrate 100 may include only a base substrate without an epitaxial layer. The first substrate 100 may be a silicon substrate, gallium arsenide substrate, silicon germanium substrate, ceramic substrate, quartz substrate, or display glass substrate, or may be a semiconductor on insulator (SOI) substrate. Hereinafter, the first substrate 100 will be exemplarily described as being a silicon substrate.

In some embodiments, the first substrate 100 may be doped with a first conductivity type. For example, when the first and second pass transistor circuits TR1 and TR2 are each n-type transistors, the first substrate 100 may include p-type impurities. Although not shown, the first substrate 100 may include a well doped with the first conductivity type.

Referring to FIGS. 6 and 8 , the device isolation films 110A and 110B may define a plurality of active regions A1 and A2 within the first substrate 100 . For example, a device isolation trench defining a plurality of active regions A1 and A2 may be formed in the first substrate 100 . The device isolation films 110A and 110B may fill the device isolation trench. The device isolation films 110A and 110B may surround each of the active regions A1 and A2. The active regions A1 and A2 may be separated from each other by the device isolation films 110A and 110B.

Although the side of the device isolation trench is shown as having an inclination, this is only a characteristic of the process of forming the device isolation trench, and the technical idea of the present invention is not limited thereto.

The device isolation films 110A and 110B may include, but are not limited to, at least one of, for example, silicon oxide, silicon oxynitride, and silicon nitride.

The first active area A1 may include 1_1 to 1_3 extensions A1_1, A1_2, and A1_3.

The 1_1 to 1_3 extension parts (A1_1, A1_2, and A1_3) may extend in different first to third directions (DR1, DR2, and DR3). Each of the first to third directions DR1, DR2, and DR3 may be different from the first and second horizontal directions (X, Y) along which the substrate 100 extends. For example, the first and second directions DR1 and DR2 may be diagonal directions forming acute angles with respect to the first and second horizontal directions (X, Y), respectively. The third direction DR3 may be parallel to, but opposite to, the second horizontal direction Y.

The 1_1 to 1_3 extension parts (A1_1, A1_2, A1_3) may be formed in a Y shape. Each of the 1_1 to 1_3 extension parts (A1_1, A1_2, and A1_3) may form an angle greater than 90 degrees with respect to each other. In this case, the angle formed by the 1_1 to 1_3 extension parts (A1_1, A1_2, A1_3) is the first to third virtual line (L2 in FIG. 7, It can be defined as the angle formed by L1, L3).

Referring to FIG. 7, for example, the angle (a1) formed by the first and second virtual lines (L1, L2) parallel to the direction in which the 1_1 and 1_2 extension parts (A1_1, A1_2) extend, respectively, (a1), 1_2 and the angle (a2) formed by the second and third virtual lines (L2, L3) parallel to the direction in which the 1_3 extension parts (A1_2, A1_3) extend, respectively, and the 1_1 and 1_3 extension parts (A1_1, A1_3), respectively. The angle a3 formed by the first and third virtual lines L1 and L3 parallel to the extending direction may each be 120 degrees, but is not limited thereto.

The second active area A2 may include 2_1 to 2_3 extensions A2_1, A2_2, and A2_3. The second active area A2 may be spaced apart from the first active area A1.

Regarding the shape of the 2_1st to 2_3rd extension parts (A2_1, A2_2, A2_3), the description of the 1_1st to 1_3rd extension parts (A1_1, A1_2, A1_3) can be similarly applied.

Referring to FIG. 6 , a Y-shaped concave portion CN may be formed in the center of the second active area A2 adjacent to the second shared source/drain D2. Any one of the 1_1 to 1_3 extensions A1_1, A1_2, and A1_3 of the first active area A1 and the concave portion CN may correspond to each other.

Referring to FIGS. 6 and 7 , the first and second shared source/drains (D1, D2) of the first and second active regions (A1, A2) are a second virtual channel extending in the first direction (DR1). It may be located on the line L2.

The first and second pass transistor circuits TR1 and TR2 may be disposed on the first and second active regions A1 and A2. The first pass transistor circuit TR1 may be disposed on the first active area A1, and the second pass transistor circuit TR2 may be disposed on the second active area A2.

The first pass transistor circuit (TR1) includes 1_1 to 1_3 pass transistors (TR1_1, TR1_2, TR1_3) that transmit a driving signal so that an operating voltage is applied to each of the first to third memory cell blocks (BLK1, BLK2, and BLK3). may include.

The 1_1 pass transistor TR1_1 may correspond to one of the second to fifth pass transistors PTR2_1 to PTR5_1 of the first pass transistor group 211 of FIG. 4 . The 1_1 pass transistor TR1_1 is connected between the word line driving signal lines SI0 to SIm and the plurality of word lines WL0 to WLm, and receives the first block selection signal from the peripheral circuit 200. A driving signal may be transmitted so that an operating voltage is applied to the first memory cell block BLK1.

The 1_2 pass transistor TR1_2 may correspond to one of the second to fifth pass transistors PTR2_2 to PTR5_2 of the second pass transistor group 212 of FIG. 4 . The 1_2 pass transistor TR1_2 is connected between the word line driving signal lines SI0 to SIm and the plurality of word lines WL0 to WLm, and receives a second block selection signal from the peripheral circuit 200. A driving signal may be transmitted so that an operating voltage is applied to the second memory cell block BLK2.

The 1_3 pass transistor TR1_3 may correspond to one of the 2nd to 5th pass transistors PTR2_3 to PTR5_3 of the third pass transistor group 213 of FIG. 4 . The 1_3 pass transistor TR1_3 is connected between the word line driving signal lines SI0 to SIm and the plurality of word lines WL0 to WLm, and receives a third block selection signal from the peripheral circuit 200. A driving signal may be transmitted so that an operating voltage is applied to the third memory cell block BLK3.

The second pass transistor circuit TR2 includes 2_1st to 2_3rd pass transistors (TR2_1, TR2_2, TR2_3) that transmit a driving signal so that an operating voltage is applied to each of the first to third memory cell blocks BLK1, BLK2, and BLK3. may include.

The 2_1 pass transistor TR2_1 may correspond to any one of the second to fifth pass transistors PTR2_1 to PTR5_1 of FIG. 4 other than the 1_1 pass transistor TR1_1. The 2_1 pass transistor TR2_1 is connected between the word line driving signal lines SI0 to SIm and the plurality of word lines WL0 to WLm, and receives the first block selection signal from the peripheral circuit 200. A driving signal may be transmitted so that an operating voltage is applied to the first memory cell block BLK1.

The 2_2 pass transistor TR2_2 may correspond to any one of the 2nd to 5th pass transistors PTR2_2 to PTR5_2 of FIG. 4 other than the 1_2 pass transistor TR1_2. The 2_2 pass transistor TR2_2 is connected between the word line driving signal lines SI0 to SIm and the plurality of word lines WL0 to WLm, and receives a second block selection signal from the peripheral circuit 200. A driving signal may be transmitted so that an operating voltage is applied to the second memory cell block BLK2.

The 2_3 pass transistor TR2_3 may correspond to any one of the 2nd to 5th pass transistors PTR2_3 to PTR5_3 of FIG. 4 other than the 1_3 pass transistor TR1_3. The 2_3 pass transistor TR2_3 is connected between the word line driving signal lines SI0 to SIm and the plurality of word lines WL0 to WLm, and receives the third block selection signal from the peripheral circuit 200. A driving signal may be transmitted so that an operating voltage is applied to the third memory cell block BLK3.

Each of the 1_1st to 1_3rd pass transistors (TR1_1, TR1_2, and TR1_3) of the first pass transistor circuit (TR1) may include 1_1st to 1_3th gate structures (G1_1, G1_2, and G1_3). Each of the 2_1st to 2_3rd pass transistors (TR2_1, TR2_2, and TR2_3) of the second pass transistor circuit (TR2) may include 2_1st to 2_3th gate structures (G2_1, G2_2, and G2_3).

Each of the 1_1 to 1_3 gate electrodes (G1_1, G1_2, and G1_3) may be disposed on the 1_1 to 1_3 extension portions (A1_1, A1_2, and A1_3). Each of the 1_1st to 1_3rd gate electrodes (G1_1, G1_2, and G1_3) may be arranged to be spaced apart from each other along the first to third directions (DR1, DR2, and DR3). Each of the 1_1st to 1_3rd gate electrodes G1_1, G1_2, and G1_3 may be spaced apart from each other in a Y shape to form an angle greater than 90 degrees (for example, 120 degrees).

Each of the 1_1 to 1_3 gate electrodes (G1_1, G1_2, G1_3) is, for example, polycrystalline silicon (poly Si), amorphous silicon (a-Si), titanium (Ti), titanium nitride (TiN), or tungsten nitride ( WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum ( It may include at least one of Ta), cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), and combinations thereof, but is not limited thereto.

Each of the 2_1 to 2_3 gate electrodes (G2_1, G2_2, and G2_3) may be disposed on the 2_1 to 2_3 extension portions (A2_1, A2_2, and A2_3). The 2_1st to 2_3rd gate electrodes (G2_1, G2_2, G2_3) may each be arranged to be spaced apart from each other along the first to third directions (DR1, DR2, and DR3). Each of the 2_1st to 2_3rd gate electrodes (G2_1, G2_2, G2_3) may be spaced apart from each other in a Y shape to form an angle greater than 90 degrees (for example, 120 degrees).

Regarding the materials of the 2_1st to 2_3rd gate electrodes (G2_1, G2_2, and G2_3), the description of the materials of the 1_1st to 1_3rd gate electrodes (G1_1, G1_2, and G1_3) described above can be similarly applied.

In some embodiments, the first and second pass transistor circuits TR1 and TR2 may each be high voltage transistors. For example, a high voltage of about 5 V to about 100 V may be applied to the 1_1 to 1_3 gate electrodes (G1_1, G1_2, G1_3) and the 2_1 to 2_3 gate electrodes (G2_1, G2_2, G2_3). It is not limited.

Referring to FIG. 8, the 1_1 to 1_3 gate structures (G1_1, G1_2, G1_3) and the 2_1 to 2_3 gate structures (G2_1, G2_2, G2_3) are gate structures sequentially stacked on the first substrate 100. It may include a dielectric layer 120, a gate conductive layer 130C, and a gate capping layer 140.

The gate conductive layer 130C may include a first conductive film 132, a second conductive film 134, and a third conductive film 136.

The first conductive layer 132 may extend along the top surface of the gate dielectric layer 120. In some embodiments, the top surface of the first conductive layer 132 may be disposed at the same level as the top of the device isolation layers 110A and 110B.

The second conductive film 134 may extend along the top surface of the first conductive film 132 . In some embodiments, the second conductive layer 134 may extend along a portion of the upper surfaces of the device isolation layers 110A and 110B.

The third conductive film 136 may extend along the top surface of the second conductive film 134. In some embodiments, the third conductive layer 136 may extend along a portion of the upper surfaces of the device isolation layers 110A and 110B.

The first conductive film 132, the second conductive film 134, and the third conductive film 136 may each include a conductive material. For example, the first conductive film 132 and the second conductive film 134 may contain polycrystalline silicon (poly Si), and the third conductive film 136 may contain a metal (e.g., tungsten (W)). You can.

The gate dielectric film 120 may be interposed between the first substrate 100 and each of the 1_1 to 1_3 gate structures (G1_1, G1_2, G1_3) and 2_1 to 2_3 gate structures (G2_1, G2_2, G2_3). there is. In some embodiments, the end of the gate dielectric layer 120 may be continuous with the ends of each of the 1_1 to 1_3 gate structures (G1_1, G1_2, G1_3) and the 2_1 to 2_3 gate structures (G2_1, G2_2, G2_3). .

The gate dielectric layer 120 may include, but is not limited to, at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. . The high dielectric constant material is, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon. Oxide (zirconium silicon oxide), tantalum oxide (tantalum oxide), titanium oxide (barium strontium titanium oxide), barium titanium oxide (strontium titanium oxide), It may include, but is limited to, at least one of yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof. That is not the case.

The gate capping film 140 may extend along the top surface of each of the 1_1 to 1_3 gate structures (G1_1, G1_2, and G1_3) and the 2_1 to 2_3 gate structures (G2_1, G2_2, and G2_3). In some embodiments, the end of the gate capping film 140 may be continuous with the ends of the 1_1 to 1_3 gate structures (G1_1, G1_2, G1_3) and the 2_1 to 2_3 gate structures (G2_1, G2_2, G2_3). . In some other embodiments, the gate capping layer 140 may be omitted.

For example, the gate capping film 140 may include at least one of silicon oxide, silicon oxynitride, and silicon nitride, but is not limited thereto. For example, the gate capping layer 140 may include silicon nitride.

The first pass transistor circuit TR1 may include 1_1 to 1_3 gate structures (G1_1 to G1_3), 1_1 to 1_3 individual source/drains (S1_1 to S1_3), and first shared source/drain (D1). there is.

Each of the 1_1 to 1_3 individual source/drains (S1_1 to S1_3) may be disposed at one end of each of the 1_1 to 1_3 gate electrodes (G1_1, G1_2, and G1_3). Additionally, the 1_1 to 1_3 individual source/drains (S1_1 to S1_3) may be formed within the 1_1 to 1_3 extension parts (A1_1, A1_2, and A1_3), respectively.

The first shared source/drain (D1) may be disposed between the 1_1 to 1_3 gate structures (G1_1 to G1_3). The first shared source/drain D1 may be formed in the center of the first active area A1.

The 1_1 to 1_3 individual source/drains (S1_1 to S1_3) and the first shared source/drain (D1) may be doped with a second conductivity type different from the first conductivity type. For example, when the 1_1 to 1_3 pass transistors (TR1_1, TR1_2, TR1_3) are each n-type transistors, the 1_1 to 1_3 individual source/drains (S1_1 to S1_3) and the first shared source/drain (D1) ) may contain n-type impurities. The n-type impurity may include, for example, phosphorus (P) or arsenic (As), but is not limited thereto.

As another example, when the 1_1 to 1_3 pass transistors (TR1_1, TR1_2, TR1_3) are each p-type transistors, the 1_1 to 1_3 individual source/drains (S1_1 to S1_3) and the first shared source/drain (D1) may contain p-type impurities. The p-type impurity may include, for example, boron (B), but is not limited thereto.

The second pass transistor circuit TR2 may include 2_1st to 2_3rd gate structures (G2_1 to G2_3), 2_1st to 2_3rd individual source/drains (S2_1 to S2_3), and second shared source/drain (D2). there is.

Each of the 2_1st to 2_3rd individual source/drains (S2_1 to S2_3) may be disposed at one end of each of the 2_1st to 2_3rd gate electrodes (G2_1, G2_2, G2_3). Additionally, the 2_1st to 2_3rd individual source/drains (S2_1 to S2_3) may be formed within the 2_1st to 2_3rd extension parts (A2_1, A2_2, A2_3), respectively.

The second shared source/drain (D2) may be disposed between the 2_1 to 2_3 gate structures (G2_1 to G2_3). The second shared source/drain D2 may be formed in the center of the second active area A2.

The 2_1st to 2_3rd individual source/drains (S2_1 to S2_3) and the second shared source/drain (D2) may be doped with a second conductivity type different from the first conductivity type. For example, when the 2_1st to 2_3rd pass transistors (TR2_1, TR2_2, TR2_3) are each n-type transistors, the 2_1st to 2_3rd individual source/drains (S2_1 to S2_3) and the second shared source/drain (D2) ) may contain n-type impurities. The n-type impurity may include, for example, phosphorus (P) or arsenic (As), but is not limited thereto.

As another example, when the 2_1st to 2_3rd pass transistors (TR2_1, TR2_2, TR2_3) are each p-type transistors, the 2_1st to 2_3rd individual source/drain (S2_1 to S2_3) and the second shared source/drain (D2) may contain p-type impurities. The p-type impurity may include, for example, boron (B), but is not limited thereto.

Although not specifically shown, the 1_1 to 1_3 individual source/drains (S1_1 to S1_3) and the first shared source/drain (D1), the 2_1 to 2_3 individual source/drains (S2_1 to S2_3) and the second shared Each of the source/drain D2 may include a low concentration impurity region and a high concentration impurity region. A high-concentration impurity region may be formed within a low-concentration impurity region. A low-concentration impurity region may surround a high-concentration impurity region. At this time, the doping concentration of the high-concentration impurity region may be higher than the doping concentration of the low-concentration impurity region.

The interlayer insulating film 190 may be formed on the first substrate 100 . The interlayer insulating film 190 may cover the first substrate 100, the device isolation films 110A and 110B, and the first and second pass transistor circuits TR1 and TR2.

The interlayer insulating film 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material with a lower dielectric constant than silicon oxide. The low dielectric constant materials include, for example, FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), and PETEOS (Plasma Enhanced Glass). Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous It may include at least one of polymeric materials and combinations thereof, but is not limited thereto.

Although not specifically shown, the gate contact may be connected to each of the 1_1st to 1_3rd gate structures (G1_1, G1_2, G1_3) and the 2_1st to 2_3rd gate structures (G2_1, G2_2, G2_3). For example, the gate contact may extend in the vertical direction (Z) and penetrate the interlayer insulating layer 190 and the gate capping layer 140. The gate contact is electrically connected to each of the 1_1 to 1_3 gate structures (G1_1, G1_2, G1_3) and the 2_1 to 2_3 gate structures (G2_1, G2_2, G2_3) to form the 1_1 to 1_3 gate structures (G1_1, G1_2). , G1_3) and the 2_1st to 2_3rd gate structures (G2_1, G2_2, G2_3).

The gate contact may include a metal such as aluminum (Al), copper (Cu), or tungsten (W), but is not limited thereto.

The 1_1 to 1_3 individual source/drain contacts (SC1_1 to SC1_3) may be connected to the 1_1 to 1_3 individual source/drains (S1_1 to S1_3). Additionally, the first shared source/drain contact (DC1) may be connected to the first shared source/drain (D1).

For example, the 1_1st to 1_3rd individual source/drain contacts (SC1_1 to SC1_3) and the first shared source/drain contact (DC1) may extend in the vertical direction (Z) and penetrate the interlayer insulating film 190. The 1_1 to 1_3 individual source/drain contacts (SC1_1 to SC1_3) are electrically connected to the 1_1 to 1_3 individual source/drains (S1_1 to S1_3) and are connected to the 1_1 to 1_3 individual source/drains (S1_1 to S1_3). Voltage can be applied. The first shared source/drain contact (DC1) is electrically connected to the first shared source/drain (D1) and can apply a voltage to the first shared source/drain (D1). In some embodiments, the 1_1 to 1_3 individual source/drain contacts (SC1_1 to SC1_3) and the first shared source/drain contact (DC1) may contact a high concentration impurity region.

The first shared source/drain (D1) is electrically connected to one of the word line driving signal lines (SI0 to SIm) through the first shared source/drain contact (DC1) to input an operating voltage from the peripheral circuit 200. You can receive it. The 1_1 to 1_3 individual source/drains (S1_1 to S1_3) are electrically connected to the first to third memory cell blocks (BLK1, BLK2, BLK3) through the 1_1 to 1_3 individual source/drain contacts (SC1_1 to SC1_3). can be connected

The 1_1 to 1_3 individual source/drain contacts (SC1_1 to SC1_3) and the first shared source/drain contact (DC1) include a metal such as aluminum (Al), copper (Cu), or tungsten (W). It can be done, but is not limited to this.

The 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3) may be connected to the 2_1st to 2_3rd individual source/drains (S2_1 to S2_3). Additionally, the second shared source/drain contact (DC2) may be connected to the second shared source/drain (D2).

For example, the 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3) and the second shared source/drain contact (DC2) may extend in the vertical direction (Z) and penetrate the interlayer insulating film 190. The 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3) are electrically connected to the 2_1st to 2_3rd individual source/drains (S2_1 to S2_3) and are connected to the 2_1st to 2_3rd individual source/drains (S2_1 to S2_3). Voltage can be applied. The second shared source/drain contact (DC2) is electrically connected to the second shared source/drain (D2) and can apply a voltage to the second shared source/drain (D2). In some embodiments, the 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3) and the second shared source/drain contact (DC2) may contact a high concentration impurity region.

The second shared source/drain (D2) is electrically connected to one of the word line driving signal lines (SI0 to SIm) through the second shared source/drain contact (DC2) to input an operating voltage from the peripheral circuit 200. You can receive it. The 2_1st to 2_3rd individual source/drains (S2_1 to S2_3) are electrically connected to the first to third memory cell blocks (BLK1, BLK2, BLK3) through the 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3). can be connected

Regarding the materials of the 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3) and the second shared source/drain contact (DC2), the materials of the 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3) and the second shared source/drain contact (DC2_3) are described above. 2 The explanation regarding the shared source/drain contact (DC2) can be similarly applied.

Meanwhile, the positions where the 1_1st to 1_3rd individual source/drain contacts (SC1_1 to SC1_3) and the first shared source/drain contact (DC1) are formed are not limited to those shown in the drawing. Likewise, the positions of the 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3) and the second shared source/drain contact (DC2) are also not limited to those shown in the drawing.

In some embodiments, three high voltage transistors sharing one source/drain may be formed to have a Y shape. Accordingly, a transistor array can be formed so as to reduce the area occupied by the transistors in a semiconductor memory device and increase the distance between shared sources/drains compared to before. As a result, the dose of impurities injected into the shared source/drain can be reduced, thereby providing a semiconductor memory device with improved breakdown voltage characteristics while occupying a small area.

9 to 12 are various layout diagrams for explaining the arrangement structure of pass transistors according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 8 will be briefly described or omitted.

The semiconductor memory device may further include third to seventh active regions A3 to A7 spaced apart from the first and second active regions A1 and A2.

Each of the third to seventh active regions A3 to A7 may include three extension parts extending in the first to third directions DR1, DR2, and DR3.

The extension portions of each of the third to seventh active regions A3 to A7 may be formed in a Y shape. In this case, the extension portions of the third to seventh active regions A3 to A7 may form an angle greater than 90 degrees to each other.

The semiconductor memory device may further include third to seventh pass transistors TR3 to TR7 that are spaced apart from the first and second pass transistors TR1 and TR2 and transmit driving signals to the memory cell blocks.

Each of the third to seventh pass transistors TR3 to TR7 may be disposed on the third to seventh active regions A3 to A7.

Regarding the three pass transistors of each of the third to seventh pass transistors (TR3 to TR7), the three pass transistors (TR1_1, TR1_2, TR1_3) of the above-described first pass transistor (TR1) or the second pass transistor (TR1_3) The description of the three pass transistors (TR2_1, TR2_2, TR2_3) of TR2) can be similarly applied.

The third pass transistor TR3 may include three pass transistors that transmit a driving signal to apply an operating voltage to each of the first to third memory cell blocks BLK1, BLK2, and BLK3.

The third pass transistor TR3 may include a 3_1 to 3_3 gate electrode (G3_1, G3_2, G3_3), a third individual source/drain (S3_1, S3_2, S3_3), and a third shared source/drain (D3). there is.

Each of the 3_1st to 3_3rd gate electrodes G3_1, G3_2, and G3_3 may be disposed on the third extension portion A3 that extends in the first to third directions and forms an angle greater than 90 degrees with respect to each other. Each of the 3_1st to 3_3rd gate electrodes G3_1, G3_2, and G3_3 may be arranged to be spaced apart from each other along the first to third directions DR1, DR2, and DR3. Each of the 3_1st to 3_3rd gate electrodes G3_1, G3_2, and G3_3 may be spaced apart from each other in a Y shape to form an angle greater than 90 degrees (for example, 120 degrees).

The fourth pass transistor TR4 may include three pass transistors that transmit a driving signal to apply an operating voltage to each of the first to third memory cell blocks BLK1, BLK2, and BLK3.

The fourth pass transistor TR4 may include 4_1 to 4_3 gate electrodes (G4_1, G4_2, G4_3), fourth individual source/drain (S4_1, S4_2, S4_3), and fourth shared source/drain (D4). there is.

Each of the 4_1st to 4_3rd gate electrodes G4_1, G4_2, and G4_3 may be disposed on the fourth extension portion A4 that extends in the first to third directions and forms an angle greater than 90 degrees with respect to each other. The 4_1st to 4_3rd gate electrodes G4_1, G4_2, and G4_3 may each be arranged to be spaced apart from each other along the first to third directions DR1, DR2, and DR3. Each of the 4_1st to 4_3rd gate electrodes G4_1, G4_2, and G4_3 may be spaced apart from each other in a Y shape to form an angle greater than 90 degrees (for example, 120 degrees).

The fifth pass transistor TR5 may include a 5_1 to 5_3 gate electrode (G5_1, G5_2, G5_3), a fifth individual source/drain (S5_1, S5_2, S5_3), and a fifth shared source/drain (D5). there is.

The sixth pass transistor TR6 may include a 6_1 to 6_3 gate electrode (G6_1, G6_2, G6_3), a sixth individual source/drain (S6_1, S6_2, S6_3), and a sixth shared source/drain (D6). there is.

The seventh pass transistor TR7 may include a 7_1 to 7_3 gate electrode (G7_1, G7_2, G7_3), a seventh individual source/drain (S7_1, S7_2, S7_3), and a seventh shared source/drain (D7). there is.

Referring to FIG. 9 , the first and second active regions A1 and A2 may be arranged in a Y shape parallel to each other in the first direction DR1. The second and third active regions A2 and A3 may be arranged in a Y shape parallel to each other in the second direction DR2. The first and third active areas A1 and A3 may be arranged in a Y shape parallel to each other in the second horizontal direction (Y).

In FIG. 9 , the shape connecting the centers of the first to third shared source/drain regions D1, D2, and D3 may be an equilateral triangle. In this case, the distance (d) between the centers of the first and second shared source/drain regions (D1, D2), the distance between the centers of the second and third shared drain regions (D2, D3), and the The distance between the centers of the three shared drain regions D1 and D3 may be equal to each other.

Centering on the third pass transistor TR3, the center of each shared source/drain of the remaining pass transistors TR1, TR2, TR4, TR5, TR6, and TR7 may have a regular hexagon.

Referring to FIG. 10 , the first and second active regions A1 and A2 may be arranged in an inverted Y shape in the first diagonal direction DR1. The first and third active regions A1 and A3 may be arranged in an inverted Y shape in the second diagonal direction DR2. The second and third active areas A2 and A3 may be arranged in a Y shape parallel to each other in the first horizontal direction (X).

In FIG. 10 , the shape connecting the centers of the first to third shared source/drains D1, D2, and D3 may be an isosceles triangle. In this case, a first distance (d1) between the centers of the first and second shared source/drain (D1, D2) and a second distance (d1) between the centers of the first and third shared source/drain (D1, D3) d2) may be identical to each other. Meanwhile, the third distance (d3) between the centers of the second and third shared source/drains (D2, D3) is the first distance (d1) between the centers of the first and second shared source/drains (D1, D2) ) or may be different from the second distance (d2) between the centers of the first and third shared source/drain (D1, D3).

Referring to FIG. 11 , the first and second active regions A1 and A2 may be arranged in a Y shape parallel to each other in the first diagonal direction DR1. The second and third active regions A2 and A3 may be arranged in a Y shape parallel to each other in the second diagonal direction DR2. The first and third active areas A1 and A3 may be arranged in a Y shape parallel to each other in the second horizontal direction (Y). The first and fourth active regions A1 and A4 may be arranged in a Y shape parallel to each other in the second diagonal direction DR2.

In FIG. 11 , the shape connecting the centers of the first to fourth shared source/drains D1, D2, D3, and D4 may be a diamond shape. In this case, a first distance (d1) between the centers of the first and second shared source/drain (D1, D2), a second distance (d1) between the centers of the second and third shared source/drain (D2, D3) d2), a third distance d3 between the centers of the third and fourth shared sources/drains D3, D4, and a fourth distance between the centers of the first and fourth shared sources/drains D1, D4. (d4) may be identical to each other.

A fifth distance (d5) between the centers of the first and third shared source/drains (D1, D3) is a first distance (d1) between the centers of the first and second shared source/drains (D1, D2); a second distance (d2) between the centers of the second and third shared source/drains (D2, D3), a third distance (d3) between the centers of the third and fourth shared source/drains (D3, D4), Alternatively, it may be different from the fourth distance d4 between the centers of the first and fourth shared source/drains D1 and D4.

Referring to FIG. 12, the first and second active areas A1 and A2 adjacent to each other in the first horizontal direction (X) may be arranged in an inverted Y shape. The third and fourth active areas A3 and A4 adjacent to each other in the first horizontal direction (X) may be arranged in an inverted Y shape. The second and third active areas A2 and A3 adjacent to each other in the second horizontal direction Y may be arranged in a Y shape parallel to each other. The first and fourth active areas A1 and A4 adjacent to each other in the second horizontal direction Y may be arranged in a Y shape parallel to each other.

Referring to FIG. 12, the shape connecting the centers of the first to fourth shared source/drains D1, D2, D3, and D4 may be square. In this case, a first distance (d1) between the centers of the first and second shared source/drain (D1, D2), a second distance (d1) between the centers of the second and third shared source/drain (D2, D3) d2), a third distance (d3) between the centers of the third and fourth shared source/drains (D3, D4) and a fourth distance (d3) between the centers of the first and fourth shared source/drains (D1, D4) d4) may be identical to each other.

Hereinafter, a non-volatile memory device including a semiconductor memory device according to example embodiments will be described with reference to FIGS. 1 to 16 .

FIG. 13 is a schematic diagram illustrating a non-volatile memory device including a semiconductor memory device according to some embodiments. Figures 14 and 15 are various enlarged views for explaining the R region of Figure 13. FIG. 16 is a schematic diagram illustrating a non-volatile memory device including a semiconductor memory device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 12 will be briefly described or omitted.

The first to third circuit elements TR1, TR2, and TR3 may refer to the first to third pass transistor circuits TR1, TR2, and TR3 described using FIGS. 1 to 12.

Referring to FIG. 13, a non-volatile memory device including a semiconductor memory device according to some embodiments may include a peripheral circuit area (PERI) and a cell area (CELL).

The peripheral circuit area PERI includes the first substrate 100, the interlayer insulating film 190, and a plurality of circuit elements TR1, TR2, TR3, 220a, 220b, and 220c formed on the first substrate 100. A first metal layer (164, 230a, 230b) connected to each of TR1, TR2, TR3, 220a, 220b, and 220c, a second metal layer formed on the first metal layer (164, 230a, 230b) ( 240, 240a, 240b).

The first substrate 100 may include first and second surfaces 100a and 100b facing each other. A peripheral circuit area PERI may be disposed on the first surface 100a of the first substrate 100. In some embodiments, the first to third circuit elements TR1, TR2, and TR3 may provide a decoder circuit (eg, 1110 in FIG. 17, described later) in the peripheral circuit area PERI. In some embodiments, the fourth circuit element 220a may provide a logic circuit (eg, 1130 in FIG. 17) in the peripheral circuit area PERI. In some embodiments, the fifth circuit element 220b may provide a page buffer (eg, 1120 in FIG. 17 ) in the peripheral circuit area PERI.

In this specification, only the first metal layers (164, 230a, 230b) and the second metal layers (240, 240a, 240b) are shown and described, but are not limited thereto, and the second metal layers (240, 240a, 240b) At least one metal layer may further be formed on the top. At least a portion of the one or more metal layers formed on top of the second metal layers 240, 240a, 240b is formed of aluminum, etc., which has a lower resistance than the copper forming the second metal layers 240, 240a, 240b. It can be.

In some embodiments, the first metal layers 164, 230a, and 230b may be formed of tungsten with a relatively high resistance, and the second metal layers 240, 240a, and 240b may be formed of copper with a relatively low resistance. You can.

The interlayer insulating film 190 covers a plurality of circuit elements (TR1, TR2, TR3, 220a, 220b, 220c), first metal layers (164, 230a, 230b), and second metal layers (240, 240a, 240b). It may be placed on the first substrate 100 to do so.

The cell area (CELL) may provide at least one memory block. The cell area CELL may include a second substrate 310 and a common source line 320. The second substrate 310 may include first and second surfaces 310a and 310b facing each other. A cell region CELL may be disposed on the first surface 310a of the second substrate 310.

On the second substrate 310, a plurality of word lines 331 to 338 (330) may be stacked along a vertical direction (Z) that intersects the top surface of the second substrate 310. A string selection line (e.g., SSL0 to SSL2 in FIG. 5) and a ground selection line (e.g., GSL0 to GSL2 in FIG. 5) may be disposed above and below each of the word lines 330, and the string selection lines and A plurality of word lines 330 may be disposed between ground selection lines.

The channel structure (CH) may extend in the vertical direction (Z) and pass through the word lines 330, the string select lines, and the ground select line. As shown in FIGS. 14 and 15, the channel structure CH may include a semiconductor pattern 390 and an information storage film 392 formed on the sidewall of the channel hole CHH penetrating the word lines 330. You can.

The semiconductor pattern 390 may extend in the vertical direction (Z). The semiconductor pattern 390 is shown as having a cup shape, but this is only an example, and the semiconductor pattern 390 may have various shapes such as a cylindrical shape, a rectangular cylinder shape, or a solid pillar shape. The semiconductor pattern 390 may include, but is not limited to, semiconductor materials such as single crystal silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

The information storage layer 392 may be interposed between the semiconductor pattern 390 and the word lines 330. For example, the information storage layer 392 may extend along the side of the semiconductor pattern 390 .

In some embodiments, the information storage layer 392 may be formed as a multilayer. For example, the information storage layer 392 may include a tunnel insulating layer 392a, a charge storage layer 392b, and a blocking insulating layer 392c that are sequentially stacked on the semiconductor pattern 390. The tunnel insulating film 392a may include, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ )). The charge storage layer 392b may include, for example, silicon nitride. The blocking insulating film 392c may include, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide. In some embodiments, the information storage layer 392 may further include a gate insulating layer 392d extending along the surface of each word line 330.

In some embodiments, the channel structure (CH) may further include a filling pattern (396). The filling pattern 396 may be formed to fill the interior of the cup-shaped semiconductor pattern 130. The filling pattern 396 may include an insulating material, for example, silicon oxide, but is not limited thereto.

The common source line 320 may be formed to be connected to the semiconductor pattern 390 of the channel structure (CH).

Although not specifically shown, in some embodiments, the channel structure CH may pass through the common source line 320 and be buried in the second substrate 310 . The common source line 320 may pass through a portion of the information storage layer 392 and be connected to the side of the semiconductor pattern 390.

Although not specifically shown, in some other embodiments, at least a portion of the common source line 320 may be buried in the second substrate 310 . For example, the common source line 320 may be formed from the second substrate 310 through a selective epitaxial growth (SEG) process. The channel structure (CH) may penetrate a portion of the information storage film 392 and be connected to the upper surface of the common source line 320.

The channel structure CH may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line (eg, BL0 to BL2 in FIG. 5). In some embodiments, the bit line 360c may extend in one direction (e.g., the second horizontal direction Y) parallel to the top surface of the second substrate 310. In some embodiments, the bit line 360c ) may be electrically connected to the fifth circuit element 220b that provides a page buffer (eg, 1120 in FIG. 17, which will be described later) in the peripheral circuit area PERI.

The word lines 330 may extend along a direction parallel to the top surface of the second substrate 310 (e.g., the first horizontal direction (X)) and may be connected to a plurality of cell contact plugs 340. . The word lines 330 and the cell contact plugs 340 may be connected to each other at pads provided by at least some of the word lines 330 extending to different lengths. A first metal layer 350b and a second metal layer 360b may be sequentially connected to the top of the cell contact plugs 340 connected to the word lines 330.

In some embodiments, the cell contact plugs 340 are electrically connected to the first to third circuit elements TR1, TR2, and TR3 that provide a decoder circuit (e.g., 1110 in FIG. 17) in the peripheral circuit region PERI. It can be connected to . For example, the first metal layer 350b connected to the cell contact plugs 340 may be connected to the first metal layer 350d by the second metal layer 360b. The first metal layer 350d may be connected to the second metal layer 240 through a connection contact plug 345. Accordingly, the first to third circuit elements TR1, TR2, and TR3 may be electrically connected to the word lines 330. For example, the first circuit element TR1 may be electrically connected to some of the word lines 330, and the second circuit element TR2 may be electrically connected to another part of the word lines 330. , the third circuit element TR3 may be electrically connected to another portion of the word lines 330.

In some embodiments, the operating voltage of the first to third circuit elements TR1, TR2, and TR3 may be different from the operating voltage of the fifth circuit element 220b that provides a page buffer (e.g., 1120 in FIG. 17). You can.

The common source line contact plug 380 may be electrically connected to the common source line 320. The common source line contact plug 380 is made of a conductive material such as metal, a metal compound, or polysilicon, and a first metal layer 350a may be formed on the common source line contact plug 380.

In some embodiments, a lower insulating film 201 may be formed on the lower part of the first substrate 100 to cover the lower surface of the first substrate 100, and a first input/output pad 205 may be formed on the lower insulating film 201. can be formed. The first input/output pad 205 is connected to at least one of the plurality of circuit elements TR1, TR2, TR3, 220a, and 220b disposed in the peripheral circuit area PERI through the first input/output contact plug 203, It may be separated from the first substrate 100 by the lower insulating film 201. Additionally, a side insulating film (not shown) is disposed between the first input/output contact plug 203 and the first substrate 100 to electrically separate the first input/output contact plug 203 from the first substrate 100. .

In some embodiments, an upper insulating film 301 may be formed on the second substrate 310 to cover the top surface of the second substrate 310, and a second input/output pad 305 may be formed on the upper insulating film 301. can be placed. The second input/output pad 305 may be connected to at least one of the plurality of circuit elements TR1, TR2, TR3, 220a, and 220b disposed in the peripheral circuit area PERI through the second input/output contact plug 303. .

In some embodiments, the second substrate 310 and the common source line 320 may not be disposed in the area where the second input/output contact plug 303 is disposed. Additionally, the second input/output pad 305 may not overlap the word lines 330 in the vertical direction (Z). The second input/output contact plug 303 is separated from the second substrate 310 and may be connected to the second input/output pad 305 through the interlayer insulating film 315 of the cell region CELL.

In some embodiments, the first input/output pad 205 and the second input/output pad 305 may be formed selectively. For example, a non-volatile memory device including a semiconductor memory device according to some embodiments includes only the first input/output pad 205 disposed on the first substrate 100 or the second substrate 310. It may also include only the second input/output pad 305 disposed. Alternatively, a non-volatile memory device including a semiconductor memory device according to some embodiments may include both the first input/output pad 205 and the second input/output pad 305.

Referring to FIG. 15 , the channel structure CH may include an information storage layer 392, a semiconductor pattern 390, a variable resistance layer 394, and a filling pattern 396. For example, a channel hole (CHH) extending in the vertical direction (Z) and penetrating the word lines 330 may be formed. The information storage layer 392, semiconductor pattern 390, variable resistance layer 394, and filling pattern 396 may be sequentially stacked in the channel hole CHH. In some embodiments, the semiconductor pattern 390, the variable resistance layer 394, and the filling pattern 396 may each extend conformally along the profile of the channel hole CHH. The filling insulating layer 396 may fill the area of the channel hole CHH remaining after the information storage layer 392, the semiconductor pattern 390, and the variable resistance layer 394 are filled.

The variable resistance film 394 may extend along the inner surface of the semiconductor pattern 390 . For example, the variable resistance layer 394 may extend conformally along the inner wall of the semiconductor pattern 390 .

The variable resistance film 394 may include a variable resistive material. The variable resistance material may have variable resistance characteristics depending on the current flowing through the variable resistance film 394. For example, the variable resistance film 394 may be made of a material having switching characteristics, such as silicon oxide (SiO _x ), aluminum oxide (AlO), magnesium oxide (MgO), zirconium oxide (ZrO), hafnium oxide (HfO), It may include, but is not limited to, at least one of silicon nitride (SiN), tungsten oxide (WO), titanium oxide (TiO), and tantalum oxide (TaO).

In some embodiments, the variable resistance layer 394 may include transition metal oxide (TMO). For example, the variable resistance film 394 may include at least one of hafnium oxide (HfO) and tantalum oxide (TaO).

Areas of the variable resistance layer 394 facing each of the word lines 330 are areas capable of storing information and may form memory cells.

FIG. 16 is a schematic diagram illustrating a non-volatile memory device including a semiconductor memory device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 15 will be briefly described or omitted.

Referring to FIG. 16, a non-volatile memory device including a semiconductor memory device according to some embodiments may have a C2C (chip to chip) structure.

First bonding pads 372a, 372b, 372c, and 372d on the first substrate 100 so that the first surface 100a of the first substrate 100 and the first surface 310a of the second substrate 310 face each other. ) and the second bonding pads 273a, 272b, 272c, and 272d on the second substrate 310 may be bonded.

In the C2C structure, an upper chip including a cell region (CELL) is manufactured on a first wafer, and a lower chip including a peripheral circuit region (PERI) is fabricated on a second wafer that is different from the first wafer. This may mean connecting a chip and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the top metal layer of the upper chip and the bonding metal formed on the top metal layer of the lower chip. For example, when the bonding metal is made of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be made of aluminum or tungsten.

In some embodiments, each of the peripheral circuit area (PERI) and the cell area (CELL) may include an external pad bonding area (PA), a word line bonding area (WLBA), and a bit line bonding area (BLBA).

The word line bonding area (WLBA) may be defined as an area where a plurality of cell contact plugs 340, etc. are disposed. Lower bonding metals 271b and 272b may be formed on the second metal layer 240 of the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 271b and 272b of the peripheral circuit area (PERI) may be electrically connected to the upper bonding metals 371b and 372b of the cell area (CELL) by a bonding method. . The lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b may be formed of aluminum, copper, or tungsten. The cell contact plugs 340 are connected to the peripheral circuit through the upper bonding metals 371b and 372b of the cell area (CELL) and the lower bonding metals 271b and 272b of the peripheral circuit area (PERI) in the word line bonding area (WLBA). It can be connected to the area (PERI).

The bit line bonding area (BLBA) may be defined as an area where the channel structure (CH) and the bit line 360c are placed. The bit line 360c may be electrically connected to the fifth circuit element 220b in the bit line bonding area BLBA. For example, the bit line 360c is connected to the upper bonding metal 371c and 372c in the peripheral circuit area (PERI), and the upper bonding metal 371c and 372c are lower bonding metals connected to the fifth circuit element 220b. It can be connected to metal (271c, 272c).

A common source line contact plug 380 may be disposed in the external pad bonding area PA. The common source line contact plug 380 is made of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a may be sequentially stacked on the common source line contact plug 380. For example, the area where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as the external pad bonding area PA. Additionally, input/output pads 205 and 305 may be disposed in the external pad bonding area PA.

The metal pattern of the uppermost metal layer exists as a dummy pattern in each of the external pad bonding area (PA) and bit line bonding area (BLBA) included in each of the cell area (CELL) and the peripheral circuit area (PERI). The top metal layer may be empty.

A non-volatile memory device including a semiconductor memory device according to some embodiments has a peripheral circuit area corresponding to the upper metal patterns 371a and 372a formed on the uppermost metal layer of the cell area CELL in the external pad bonding area PA. Lower metal patterns 271a, 272a, and 273a similar to the upper metal patterns 371a and 372a of the cell region CELL may be formed on the uppermost metal layer of the PERI. The lower metal patterns 271a, 272a, and 273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, the lower metal pattern of the peripheral circuit area (PERI) is formed on the upper metal layer of the cell area (CELL) in response to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area (PERI) in the external pad bonding area (PA). An upper metal pattern of the same shape as may be formed.

Additionally, in the bit line bonding area (BLBA), the peripheral circuit area (PERI) is formed on the uppermost metal layer of the cell area (CELL) corresponding to the lower metal patterns (271d, 272d) formed on the uppermost metal layer of the peripheral circuit area (PERI). The upper metal patterns 371d and 372d may be formed in a similar form to the lower metal patterns 271d and 272d. A contact may not be formed on the upper metal patterns 371d and 372d formed on the uppermost metal layer of the cell region (CELL).

Hereinafter, an electronic system including a semiconductor memory device according to example embodiments will be described with reference to FIGS. 17 to 19 .

FIG. 17 is a block diagram illustrating an electronic system including a semiconductor memory device according to some embodiments. FIG. 18 is a schematic perspective view illustrating an electronic system including a semiconductor memory device according to some embodiments. FIG. 19 is a schematic cross-sectional view taken along line II of FIG. 18.

Referring to FIG. 17, an electronic system 1000 including a semiconductor memory device according to some embodiments may include a non-volatile memory device 1100 and a controller 1200 electrically connected to the non-volatile memory device 1100. You can. The electronic system 1000 may be a storage device including one or a plurality of non-volatile memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or a plurality of non-volatile memory devices 1100. there is.

The non-volatile memory device 1100 may be a NAND flash memory device and, for example, may include the semiconductor memory device described above using FIGS. 1 to 16 . The non-volatile memory device 1100 may communicate with the controller 1200 through an input/output pad 1101 that is electrically connected to the logic circuit 1130. The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first structure 1100F to the second structure 1100S. For example, the input/output connection wire 1135 may be the first input/output contact plug 203 or the second input/output contact plug 303 described above using FIGS. 3 to 16 .

An electronic system including a semiconductor memory device according to some embodiments may control the first to third circuit elements TR1, TR2, and TR3 using the controller 1200. For example, as described above, the logic circuit 1130 may be connected to the gate electrodes of each of the first to third pass transistor circuits TR1, TR2, and TR3. The gate electrodes may be controlled by the controller 1200 to apply voltage.

The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of non-volatile memory devices 1100, and in this case, the controller 1200 may control the plurality of non-volatile memory devices 1100.

The processor 1210 may control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the non-volatile memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that handles communication with the non-volatile memory device 1100. Through the NAND interface 1221, control commands for controlling the non-volatile memory device 1100, data to be written to the memory cell transistors (MCT) of the non-volatile memory device 1100, and non-volatile memory device 1100. Data to be read from the memory cell transistors (MCT), etc. may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When receiving a control command from an external host through the host interface 1230, the processor 1210 may control the non-volatile memory device 1100 in response to the control command.

Referring to FIG. 18, an electronic system 2000 including a semiconductor memory device according to some embodiments includes a main board 2001, a main controller 2002 mounted on the main board 2001, and one or more semiconductor packages 2003. ), and DRAM (2004). The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through wiring patterns 2005 formed on the main substrate 2001.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may include interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). You can communicate with an external host according to any one of the following. In some embodiments, the electronic system 2000 may operate with power supplied from an external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

The main controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

DRAM (2004) may be a buffer memory to alleviate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a type of cache memory and may provide space for temporarily storing data during control operations for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b that are spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, and adhesive layers 2300 disposed on the lower surfaces of each of the semiconductor chips 2200. ), a connection structure 2400 that electrically connects the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. It can be included.

The package substrate 2100 may be a printed circuit board including top pads 2130 of the package. Each semiconductor chip 2200 may include an input/output pad 2210. The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 17 . Each of the semiconductor chips 2200 may include gate stacked structures 3210 and memory channel structures 3220. The gate stacked structures 3210 may correspond to a memory block, and the memory channel structures 3220 may correspond to a channel structure (CH). Each of the semiconductor chips 2200 may include the semiconductor memory device described above using FIGS. 1 to 16 .

In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input/output pad 2210 and the top pads 2130 of the package. Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and the package upper pads 2130 of the package substrate 2100 and Can be electrically connected. In some embodiments, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 use a through electrode (Through Silicon Via, TSV) instead of the bonding wire-type connection structure 2400. They may be electrically connected to each other by a connection structure that includes a connection structure.

In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be included in one package. In some embodiments, the main controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer board different from the main board 2001, and the main controller 2002 and the semiconductor chips are connected by wiring formed on the interposer board. Chips 2200 may be connected to each other.

18 and 19, in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 disposed on the upper surface of the package substrate body 2120, and disposed on or exposed through the lower surface of the package substrate body 2120. may include lower pads 2125 and internal wires 2135 that electrically connect the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The upper pads 2130 may be electrically connected to the connection structures 2400. The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2001 of the electronic system 2000 as shown in FIG. 18 through conductive connectors 2800.

Each of the semiconductor chips 2200 may include a first structure 3100 and a second structure 3200 that are sequentially stacked. The first structure 3100 may correspond to the peripheral circuit area (PERI) of FIG. 13, and the second structure 3200 may correspond to the cell area (CELL) of FIG. 13. For example, the first structure 3100 may include a first semiconductor substrate 3010 corresponding to the first substrate 100 of FIG. 13 . The second structure 3200 may include a second semiconductor substrate 3205 corresponding to the second substrate 310 of FIG. 13 . Additionally, the second structure 3200 may include the gate stacked structures 3210 and memory channel structures 3220 described above with respect to FIG. 18 .

The second structure 3200 may include gate connection wires 3235. Gate connection wires 3235 may be electrically connected to the gate stacked structure 3210. The gate connection wires 3235 may correspond to the cell contact plugs 340 of FIG. 13 .

Each of the semiconductor chips 2200 is electrically connected to the peripheral wirings 3110 of the first structure 3100 and may include a through wiring 3245 extending into the second structure 3200. The through wiring 3245 may be disposed outside the gate stacked structure 3210 and may be further disposed to penetrate the gate stacked structure 3210. Each of the semiconductor chips 2200 may further include an input/output pad (2210 in FIG. 18) that is electrically connected to the peripheral wires 3110 of the first structure 3100.

In some embodiments, the first structure 3100 includes the first active region A1, the first pass transistor circuit TR1, and the 1_1 to 1_3 gate structures (G1_1 to G1_3) described above using FIGS. 1 to 12. ), 1_1 to 1_3 individual source/drain (S1_1 to S1_3), first shared source/drain (D1), 1_1 to 1_3 individual source/drain contact (SC1_1 to SC1_3), first shared source/drain contact (DC1), second active region (A2), second pass transistor circuit (TR2), 2_1st to 2_3rd gate structures (G2_1 to G2_3), 2_1st to 2_3rd individual source/drain (S2_1 to S2_3), It may include 2 shared source/drain (D2), 2_1st to 2_3rd individual source/drain contacts (SC2_1 to SC2_3), and a second shared source/drain contact (DC2).

The semiconductor chips 2200 of FIGS. 18 and 19 may be electrically connected to each other by connection structures 2400 in the form of bonding wires ( 2400 of FIG. 18 ). However, in some embodiments, semiconductor chips within one semiconductor package, such as the semiconductor chips 2200 of FIGS. 17 and 18, may be electrically connected to each other by a connection structure including a through electrode (TSV).

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: first substrate
A1: first active area
TR1: first pass transistor circuit
S1_1, S1_2, S1_3: 1_1 to 1_3 individual source/drain
D1: First shared source/drain
A2: second active area
TR2: second pass transistor circuit
S2_1, S2_2, S2_3: 2_1 to 2_3 individual source/drain
D2: Second shared source/drain

Claims (10)

A substrate including a first area where peripheral circuits are formed and a second area where memory cell blocks are formed;
a first active region defined in a first region of the substrate and including 1_1 to 1_3 extensions extending in first to third different directions to form an angle greater than 90 degrees from each other; and
A first pass transistor circuit transmitting a driving signal to apply an operating voltage to the memory cell blocks,
The first pass transistor circuit includes 1_1 to 1_3 gate structures respectively disposed on the 1_1 to 1_3 extensions and a first shared source/drain disposed between the 1_1 to 1_3 gate structures. Semiconductor memory device. According to clause 1,
The first pass transistor circuit includes 1_1 to 1_3 pass transistors that transmit the driving signal so that an operating voltage is applied to each of the first to third memory cell blocks among the memory cell blocks. According to clause 1,
The first pass transistor circuit further includes 1_1 to 1_3 individual source/drains disposed at ends of each of the 1_1 to 1_3 extension parts. According to clause 1,
A semiconductor memory device wherein the first active region is Y-shaped. According to clause 1,
a second active region defined in the first region of the substrate and spaced apart from the first active region; and
Further comprising a second pass transistor circuit on the second active region, spaced apart from the first pass transistor circuit,
The second active region is,
It includes 2_1 to 2_3 extension parts extending in the first to third directions and forming an angle greater than 90 degrees to each other,
The second pass transistor circuit,
A semiconductor memory device including 2_1 to 2_3 gate structures on 2_1 to 2_3 extensions and second shared source/drain between the 2_1 to 2_3 gate structures. According to clause 5,
The substrate extends in first and second horizontal directions perpendicular to each other,
The first and second shared source/drain are located on a first virtual line extending in the first direction. According to clause 5,
a third active region defined in the first region of the substrate and spaced apart from the first and second active regions; and
Further comprising a third pass transistor circuit on the third active region, spaced apart from the first and second pass transistor circuits,
The third active region includes a third extension portion extending in the first to third directions,
The third pass transistor circuit includes a third gate structure and a third shared source/drain on the third extension. According to clause 7,
Each of the first and second active regions and each of the first and third active regions are arranged in a Y shape parallel to each other,
A semiconductor memory device wherein the distance between the first and second shared source/drain, the distance between the second and third shared source/drain, and the distance between the first and third shared source/drain are each equal. According to clause 7,
Each of the first and second active regions and each of the first and third active regions are arranged in an inverted Y shape,
A semiconductor memory device wherein a distance between the first and second shared source/drain and a distance between the first and third shared source/drain are the same. a first substrate including a first surface extending in first and second horizontal directions perpendicular to each other, and having a memory cell area disposed on the first surface; and
A second substrate including a second surface under the first substrate and having a first peripheral circuit area arranged to receive a block selection signal and transmit a driving signal to the memory cell area,
The first peripheral circuit area is,
First to third gate structures spaced apart from each other on the first active region extending in first to third directions that are not parallel to each other, and
A semiconductor memory device including a first shared drain disposed between the first to third gate structures.

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