KR20240050238A - A semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device with improved reliability. The semiconductor device of the present invention includes a substrate including upper and lower surfaces opposing each other, an active pattern extending in a first direction on the upper surface of the substrate, a field insulating film covering sidewalls of the active pattern on the upper surface of the substrate, a power rail disposed on the lower surface of the substrate and extending in the first direction, a trench formed in the substrate and exposing a portion of the power rail, and filling at least a portion of the trench and connected to the power rail. It includes a metal pattern, the bottom surface of the trench lies on the same plane as the bottom surface of the substrate, the sidewalls of the trench have a convex shape, and at least a portion of the field insulating film is disposed in the trench.

Description

Semiconductor device{A SEMICONDUCTOR DEVICE}

The present invention relates to semiconductor devices.

As one of the scaling technologies to increase the density of semiconductor devices, a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and placed on the surface of the multi-channel active pattern. A multi gate transistor forming a gate has been proposed.

Because these multi-gate transistors use three-dimensional channels, they are easy to scale. Additionally, current control ability can be improved without increasing the gate length of the multi-gate transistor. In addition, short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed.

Meanwhile, as the pitch size of semiconductor devices decreases, research is needed to reduce capacitance and ensure electrical stability between contacts within the semiconductor device.

The technical problem to be solved by the present invention is to provide a semiconductor device with improved reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor device according to some embodiments of the present invention for achieving the above technical problem includes a substrate including opposing upper and lower surfaces, an active pattern extending in a first direction on the upper surface of the substrate, and an active pattern extending in a first direction on the upper surface of the substrate. A field insulating film covering a sidewall of the active pattern, a power rail disposed on a lower surface of the substrate and extending in the first direction, a trench formed in the substrate and exposing a portion of the power rail, and the trench fills at least a portion of and includes a metal pattern connected to the power rail, wherein a bottom surface of the trench lies on the same plane as a bottom surface of the substrate, side walls of the trench have a convex shape, and at least one of the field insulating films Some are placed within the trench.

A semiconductor device according to some embodiments of the present invention for achieving the above technical problem includes a substrate including opposing upper and lower surfaces, an active pattern extending in a first direction on the upper surface of the substrate, and covering the active pattern. , a gate electrode extending in a second direction intersecting the first direction, a power rail disposed on a lower surface of the substrate and extending in the first direction, a metal pattern disposed in the substrate and connected to the power rail. , and a power rail via disposed on one side of the gate electrode on the metal pattern and connected to the power rail through the metal pattern, wherein the bottom surface of the metal pattern extends parallel to the bottom surface of the substrate. It is placed on the same plane as the lower surface of the substrate, and the width of the metal pattern in the second direction intersecting the first direction and the width in the first direction are respectively defined by the lower surface of the substrate and the upper surface of the substrate. It includes parts that gradually increase as you go.

A semiconductor device according to some embodiments of the present invention for achieving the above technical problem includes a substrate including opposing upper and lower surfaces, an active pattern extending in a first direction on the upper surface of the substrate, and covering the active pattern. , a gate electrode extending in a second direction intersecting the first direction, a field insulating film covering a sidewall of the active pattern on an upper surface of the substrate, disposed on a lower surface of the substrate and extending in the first direction. A power rail, a trench formed in the substrate, exposing a portion of the power rail, and having a convex sidewall, a metal pattern that fills at least a portion of the trench and connected to the power rail, on the active pattern, A source/drain pattern disposed on one side of the gate electrode, a source/drain contact on the source/drain pattern, and a source/drain contact on the metal pattern, disposed on one side of the gate electrode and connected to the power rail through the metal pattern. and a power rail via, wherein a bottom surface of the trench lies on the same plane as a bottom surface of the substrate, at least a portion of the field insulating film is disposed in the trench, and the width of the trench in the first direction and the first The width in the two directions gradually increases and then decreases from the bottom surface of the substrate toward the top surface of the substrate, respectively.

Specific details of other embodiments are included in the description and drawings.

1 is an example layout diagram for explaining a semiconductor device according to some embodiments.
FIG. 2 is an exemplary cross-sectional view taken along line AA′ of FIG. 1.
FIG. 3 is an exemplary cross-sectional view taken along line BB′ in FIG. 1.
FIG. 4 is an exemplary cross-sectional view taken along line CC' of FIG. 1.
5 to 13 are diagrams for explaining semiconductor devices according to some other embodiments.
14 to 17 are diagrams for explaining semiconductor devices according to some other embodiments.
18 to 29 are intermediate stage diagrams for explaining a semiconductor device manufacturing method according to some embodiments.

In this specification, although first, second, etc. are used to describe various elements or components, these elements or components are of course not limited by these terms. These terms are merely used to distinguish one device or component from another device or component. Therefore, it goes without saying that the first element or component mentioned below may also be a second element or component within the technical spirit of the present invention.

In the drawings of semiconductor devices according to some embodiments, illustrative examples include a fin-type transistor (FinFET) including a channel region in the shape of a fin-type pattern, a transistor including a nanowire or nanosheet, and a MBCFET ^TM (Multi-Bridge Channel Field Effect Transistor or vertical transistor (Vertical FET) is shown, but is not limited thereto. Of course, the semiconductor device according to some embodiments may include a tunneling transistor (tunneling FET) or a three-dimensional (3D) transistor. Of course, a semiconductor device according to some embodiments may include a planar transistor. In addition, the technical idea of the present invention can be applied to 2D material based transistors (2D material based FETs) and their heterostructure.

Additionally, a semiconductor device according to some embodiments may include a bipolar junction transistor, a horizontal double diffusion transistor (LDMOS), and the like.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the attached drawings.

First, with reference to FIGS. 1 to 4 , semiconductor devices according to some embodiments will be described.

1 is an example layout diagram for explaining a semiconductor device according to some embodiments. FIG. 2 is an exemplary cross-sectional view taken along line A-A' in FIG. 1. FIG. 3 is an exemplary cross-sectional view taken along line B-B' in FIG. 1. FIG. 4 is an exemplary cross-sectional view taken along line C-C' of FIG. 1. For convenience of explanation, the via plug 195 is not shown in FIG. 1 .

1 to 4 , a semiconductor device according to some embodiments includes at least one first active pattern AP1, at least one second active pattern AP2, and a plurality of gate electrodes 120. , a first source/drain contact 170, a second source/drain contact 270, a gate contact 180, a power rail (PR), a power rail via (PRVA), and a metal pattern (MP). ) may include.

First, a substrate 100 may be provided. The substrate 100 may include a plurality of active regions and a field region. Each of the plurality of active areas may be an area where the first active pattern AP1 or the second active pattern AP2 is disposed. The field area may be formed immediately adjacent to the plurality of active areas. A field area may border a plurality of active areas.

The plurality of active regions are spaced apart from each other. A plurality of active areas may be separated by a field area. In other words, a device isolation layer may be disposed around a plurality of active regions that are spaced apart from each other. At this time, a portion of the device isolation film between a plurality of active regions may be a field region. For example, a portion where a channel region of a transistor, which is an example of a semiconductor device, is formed may be an active region, and a portion that separates the channel region of a transistor formed in the active region may be a field region. Alternatively, the active region may be a portion where a fin-shaped pattern or nanosheet used as a channel region of a transistor is formed, and the field region may be a region where a fin-shaped pattern or nanosheet used as a channel region is not formed.

The substrate 100 may include an upper surface 100US and a lower surface 100BS that are opposite in the third direction Z. The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon-germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. no.

The first active pattern AP1 and the second active pattern AP2 may each be disposed on the upper surface 100US of the substrate 100. The first active pattern AP1 and the second active pattern AP2 may each extend long along the first direction (X) on the substrate 100 . The first active pattern AP1 and the second active pattern AP2 may be spaced apart from each other in the second direction Y.

The first active pattern AP1 and the second active pattern AP2 may each include a long side extending in the first direction (X) and a short side extending in the second direction (Y). Here, the first direction (X) may intersect with the second direction (Y) and the third direction (Z). Additionally, the second direction (Y) may intersect the third direction (Z). The third direction (Z) may be the thickness direction of the substrate 100.

The first activation pattern (AP1) and the second activation pattern (AP2) may each be a multi-channel activation pattern. In the semiconductor device according to some embodiments, each of the first active pattern AP1 and the second active pattern AP2 may be, for example, a fin-type pattern. The first active pattern AP1 and the second active pattern AP2 may each be used as a channel region of a transistor. Although the number of the first active pattern AP1 and the second active pattern AP2 is shown to be three, this is only for convenience of explanation and is not limited thereto. There may be one or more first active patterns (AP1) and one or more second active patterns (AP2).

The first active pattern AP1 and the second active pattern AP2 may each be part of the substrate 100 and may include an epitaxial layer grown from the substrate 100. The first active pattern AP1 and the second active pattern AP2 may include, for example, silicon or germanium, which are elemental semiconductor materials. Additionally, the first active pattern AP1 and the second active pattern AP2 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

Group IV-IV compound semiconductors are, for example, binary compounds or ternary compounds containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). compound) or a compound doped with a group IV element.

Group III-V compound semiconductors include, for example, at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements and phosphorus (P), arsenic (As), and antimonium (as group V elements). It may be one of a binary compound, a ternary compound, or a quaternary compound formed by combining one of Sb).

In some embodiments, the first active pattern AP1 and the second active pattern AP2 may each include the same material. For example, the first active pattern AP1 and the second active pattern AP2 may each be a silicon fin-type pattern. Or, for example, the first active pattern AP1 and the second active pattern AP2 may each be a fin-shaped pattern including a silicon-germanium pattern. As another example, the first active pattern AP1 and the second active pattern AP2 may include different materials. For example, some of the first active pattern AP1 and the second active pattern AP2 may be a silicon fin-type pattern, and other parts may be a fin-type pattern including a silicon-germanium pattern.

The field insulating film 105 may be formed on the substrate 100 . The field insulating film 105 may be formed on the upper surface 100US of the substrate 100. The field insulating layer 105 may be disposed on the metal pattern MP, which will be described later. The field insulating layer 105 may cover the top surface (MP_US) of the metal pattern (MP). At least a portion of the field insulating layer 105 may fill a portion of the trench TR formed in the substrate 100, but is not limited thereto.

In some embodiments, the bottom surface of the field insulating layer 105 defining the metal pattern MP may have a convex shape. For example, the bottom surface of the field insulating layer 105 defining the metal pattern MP may be convex toward the bottom surface 100BS of the substrate 100. The bottom surface of the field insulating layer 105 defining the metal pattern MP may be convex toward the power rail PR. The height from the bottom surface 100BS of the substrate 100 to the bottom surface of the field insulating layer 105 defining the metal pattern MP may be less than the thickness of the substrate 100. However, the technical idea of the present invention is not limited thereto.

The field insulating layer 105 may cover the sidewall of the first active pattern AP1. Although not shown, the field insulating layer 105 may cover the sidewall of the second active pattern AP2. The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. The field insulating layer 105 is shown as a single layer, but is not limited thereto. Unlike shown, the field insulating layer 105 may include a field liner extending along the sidewall and bottom of the fin trench, and a field filling layer on the field liner.

A plurality of gate electrodes 120 may be disposed on the substrate 100 . For example, a plurality of gate electrodes 120 may be disposed on the field insulating layer 105 . Each of the plurality of gate electrodes 120 may extend in the second direction (Y). The plurality of gate electrodes 120 may be spaced apart from each other in the first direction (X).

A plurality of gate electrodes 120 may be disposed on the first active pattern AP1 and the second active pattern AP2. The plurality of gate electrodes 120 may cover the first active pattern AP1 and the second active pattern AP2. The plurality of gate electrodes 120 may intersect the first active pattern AP1 and the second active pattern AP2. Each of the plurality of gate electrodes 120 may include a long side extending in the second direction (Y) and a short side extending in the first direction (X).

3 and 4 , the top surface of each of the plurality of gate electrodes 120 may be a convex curved surface that is recessed toward the top surface of the first active pattern AP1, but is not limited thereto. That is, unlike what is shown, the top surface of each of the plurality of gate electrodes 120 may be a flat plane.

The plurality of gate electrodes 120 may be, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or tantalum titanium nitride (TaTiN). ), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), Titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum ( Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC) , rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. You can.

Each of the plurality of gate electrodes 120 may include conductive metal oxide, conductive metal oxynitride, etc., or may include an oxidized form of the above-mentioned material.

A plurality of gate electrodes 120 may be disposed on both sides of the source/drain pattern 150, which will be described later.

For example, the gate electrodes 120 disposed on both sides of the source/drain pattern 150 may be normal gate electrodes used as gates of transistors. As another example, the gate electrode 120 disposed on one side of the source/drain pattern 150 is used as the gate of a transistor, but the gate electrode 120 disposed on the other side of the source/drain pattern 150 is a dummy gate electrode. You can.

A plurality of gate spacers 140 may be disposed on the sidewall of each of the plurality of gate electrodes 120. The plurality of gate spacers 140 do not contact the plurality of gate electrodes 120 . A gate insulating film 130 may be disposed between the gate spacer 140 and the sidewall of the gate electrode 120. Each of the plurality of gate spacers 140 may extend in the second direction (Y). The plurality of gate spacers 140 are, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), and silicon oxyboron. It may include at least one of nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

The gate insulating film 130 may extend along the sidewall and bottom surface of each of the plurality of gate electrodes 120. The gate insulating layer 130 may be formed on the first active pattern AP1, the second active pattern AP2, and the field insulating layer 105. The gate insulating film 130 may be formed between the plurality of gate electrodes 120 and the plurality of gate spacers 140.

The gate insulating layer 130 may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. High-k materials include, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, and lanthanum aluminum oxide. (lanthanum aluminum oxide), zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. It may include one or more of these.

The gate insulating layer 130 is shown as a single layer, but this is only for convenience of explanation and is not limited thereto. The gate insulating layer 130 may include a plurality of layers. The gate insulating layer 130 includes an interfacial layer disposed between the first active pattern (AP1) and the gate electrode 120 and between the second active pattern (AP2) and the plurality of gate electrodes 120, It may also include a high dielectric constant insulating film.

A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer 130 may include a ferroelectric material layer with ferroelectric properties and a paraelectric material layer with paraelectric properties.

The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance will be less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

When a ferroelectric material film with a negative capacitance and a paraelectric material film with a positive capacitance are connected in series, the overall capacitance value of the ferroelectric material film and the paraelectric material film connected in series may increase. By taking advantage of the increase in overall capacitance value, a transistor including a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV/decade at room temperature.

A ferroelectric material film may have ferroelectric properties. Ferroelectric material films include, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium oxide. It may contain at least one of titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The ferroelectric material film may further include a doped dopant. For example, dopants include aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), and cerium (Ce). ), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on what kind of ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film is, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). It can be included.

When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% of zirconium.

A paradielectric material film may have paradielectric properties. For example, the paradielectric material film may include at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paradielectric material film may include, but is not limited to, at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide.

The ferroelectric material film and the paraelectric material film may include the same material. A ferroelectric material film may have ferroelectric properties, but a paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

The ferroelectric material film may have a thickness having ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness representing ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

For example, the gate insulating layer 130 may include one ferroelectric material layer. As another example, the gate insulating film 130 may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film 130 may have a stacked structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

The plurality of gate capping films 145 may be disposed on the upper surface of the plurality of gate electrodes 120 and the upper surface of the plurality of gate spacers 140, respectively. The plurality of gate capping films 145 are, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and their It may contain at least one of the combinations.

Source/drain patterns 150 may be disposed on the substrate 100 . The source/drain pattern 150 may be formed on the first active pattern AP1. The source/drain pattern 150 is connected to the first active pattern AP1. The bottom surface of the source/drain pattern 150 is in contact with the first active pattern AP1.

The source/drain pattern 150 may be disposed on each side of the plurality of gate electrodes 120 . The source/drain pattern 150 may be disposed between the plurality of gate electrodes 120 .

For example, the source/drain pattern 150 may be disposed on both sides of the plurality of gate electrodes 120 . Unlike shown, the source/drain pattern 150 may be disposed on one side of the plurality of gate electrodes 120 and not on the other side of the plurality of gate electrodes 120.

The source/drain pattern 150 may include an epitaxial pattern. The source/drain pattern 150 may include a semiconductor material. The source/drain pattern 150 may be included in the source/drain of a transistor using the first active pattern AP1 as a channel region.

The source/drain pattern 150 may be connected to a channel region used as a channel in the first active pattern AP1. The source/drain pattern 150 is shown as a merge of three epitaxial patterns formed on each first active pattern AP1, but this is only for convenience of explanation and is not limited thereto. That is, the epitaxial patterns formed on each first active pattern AP1 may be separated from each other.

For example, an air gap may be disposed in the space between the field insulating film 105 and the combined source/drain pattern 150. As another example, the space between the field insulating film 105 and the combined source/drain pattern 150 may be filled with an insulating material.

The etch stop layer 160 may extend along the top surface of the field insulating layer 105, the sidewalls of the plurality of gate spacers 140, and the profile of the source/drain pattern 150. The etch stop film 160 may be disposed on the top surface of the source/drain pattern 150, the sidewall of the source/drain pattern 150, and the sidewalls of the plurality of gate spacers 140. In some embodiments, the etch stop layer 160 is not disposed on the sidewall of the gate capping layer 145. That is, the gate capping layer 145 may be disposed on the top surface of the etch stop layer 160. Additionally, the sidewall of the etch stop layer 160 may be connected to the outer wall of the gate capping layer 145. Unlike shown, the etch stop layer 160 may be disposed on the sidewall of the gate capping layer 145.

The etch stop layer 160 may include a material having an etch selectivity with respect to the first interlayer insulating layer 190, which will be described later. The etch stop layer 160 may include a nitride-based insulating material. For example, it may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), and combinations thereof. there is.

The first interlayer insulating layer 190 is disposed on the etch stop layer 160. The first interlayer insulating film 190 may be formed on the field insulating film 105 . The first interlayer insulating film 190 may be disposed on the source/drain pattern 150 . The first interlayer insulating layer 190 may not cover the top surface of the gate capping layer 145. For example, the top surface of the first interlayer insulating film 190 may be on the same plane as the top surface of the gate capping film 145.

For example, the first interlayer insulating film 190 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSylyl Borate (TMSB), etoxyDitertiaryButoSiloxane ( DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate Glass), SiLK , Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, mesoporous silica, or a combination thereof, but is not limited thereto.

The first source/drain contact 170 may be disposed on the source/drain pattern 150 on the first active pattern AP1. The second source/drain contact 270 may be disposed on the source/drain pattern on the second active pattern AP2. Since the description of the first source/drain contact 170 may be the same as the description of the second source/drain contact 270, only the first source/drain contact 170 will be described below.

The gate contact 180 may be connected to some of the plurality of gate electrodes 120. The gate contact 180 may be disposed at a position overlapping with the plurality of gate electrodes 120 .

The first source/drain contact 170 may penetrate the etch stop layer 160 and be connected to the source/drain pattern 150. The first source/drain contact 170 may be disposed on the source/drain pattern 150 .

The first source/drain contact 170 may be disposed within the first interlayer insulating film 190. The first source/drain contact 170 may be surrounded by a first interlayer insulating film 190.

A contact silicide film 155 may be disposed between the first source/drain contact 170 and the source/drain pattern 150. The contact silicide film 155 is shown as being formed along the profile of the interface between the source/drain pattern 150 and the first source/drain contact 170, but is not limited thereto. The contact silicide layer 155 may include, for example, a metal silicide material.

The first interlayer insulating film 190 does not cover the top surface 170US of the first source/drain contact 170. For example, the top surface 170US of the first source/drain contact 170 may not protrude above the top surface of the first gate capping layer 145. The top surface 170US of the first source/drain contact 170 may be placed on the same plane as the top surface of the gate capping film 145. Unlike what is shown, in another example, the top surface 170US of the first source/drain contact 170 may protrude above the top surface of the gate capping film 145.

Additionally, the top surface 170US of the first source/drain contact 170 may be placed on the same plane as the top surface of the gate contact 180. The top surface (170US) of the first source/drain contact 170 may be placed on the same plane as the top surface (PRVA_US) of the power rail via (PRVA).

In some embodiments, the first source/drain contact 170 may include a source/drain barrier layer 170a and a source/drain filling layer 170b on the source/drain barrier layer 170a.

The bottom surface of the first source/drain contact 170 is shown as having a flat shape, but it is not limited thereto. Of course, unlike what is shown, the bottom surface of the first source/drain contact 170 may have a wavy shape.

The source/drain barrier film 170a may include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), and cobalt (Co). ), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride ( It may include at least one of VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and two-dimensional (2D) material. In a semiconductor device according to some embodiments, the two-dimensional material may be a metallic material and/or a semiconductor material. 2D materials may include 2D allotropes or 2D compounds, for example, graphene, molybdenum disulfide (MoS2), and molybdenum diselenide (MoSe). ₂ ), tungsten diselenide (WSe ₂ ), and tungsten disulfide (WS ₂ ), but is not limited thereto. That is, since the above-described two-dimensional materials are listed only as examples, the two-dimensional materials that can be included in the semiconductor device of the present invention are not limited by the above-described materials.

The source/drain filling film 170b may include, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum. It may contain at least one of Denum (Mo).

The first source/drain contact 170 is shown as including a plurality of conductive films, but is not limited thereto. Of course, unlike what is shown, the first source/drain contact 170 may be a single layer.

Gate contact 180 may be disposed on gate electrode 120. The gate contact 180 may penetrate the gate capping film 145 and be connected to the gate electrode 120.

For example, the top surface of the gate contact 180 may be on the same plane as the top surface of the gate capping film 145. Unlike what is shown, in another example, the top surface of the gate contact 180 may protrude above the top surface of the gate capping film 145.

The gate contact 180 may include a gate barrier layer 180a and a gate filling layer 180b on the gate barrier layer 180a. Details regarding the materials included in the gate barrier film 180a and the gate filling film 180b may be the same as the descriptions of the source/drain barrier film 170a and the source/drain filling film 170b.

The gate contact 180 is shown as including a plurality of conductive films, but is not limited thereto. Of course, unlike what is shown, the gate contact 180 may be a single layer.

A semiconductor device according to some embodiments may further include a lower insulating layer 101.

The lower insulating film 101 may be disposed on the lower surface 100BS of the substrate 100. The lower insulating film 101 may contact the lower surface 100BS of the substrate 100. The lower insulating layer 101 may contact the bottom surface (MP_BS) of the metal pattern (MP).

For example, the lower insulating layer 101 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSylyl Borate (TMSB), etoxyDitertiaryButoSiloxane ( DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate Glass), SiLK , Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, mesoporous silica, or a combination thereof, but is not limited thereto.

The power rail PR may be disposed between the first active pattern AP1 and the second active pattern AP2. The power rail PR may be disposed within the lower insulating film 101 . The lower insulating film 101 may surround the power rail (PR). The power rail (PR) may extend long in the first direction (X), but is not limited thereto.

The power rail PR is disposed on the lower surface 100BS of the substrate 100. The power rail PR is disposed within the lower insulating film 101. The power rail (PR) may contact the bottom surface (MP_BS) of the metal pattern (MP). The power rail (PR) may be electrically connected to the metal pattern (MP).

In some embodiments, the power rail PR may be connected to the source/drain pattern 150. For example, the power rail (PR) is connected to the source/drain pattern 150 through a metal pattern (MP), a power rail via (PRVA), a via plug 195, and a first source/drain contact 170. It can be. Voltage can be applied to the source/drain pattern 150 through the power rail (PR).

In some embodiments, the power rail PR may include a power rail barrier film PR_a and a power rail filling film PR_b on the power rail barrier film PR_a. Details regarding the materials included in the power rail barrier film (PR_a) and the power rail filling film (PR_b) may be the same as the descriptions of the source/drain barrier film 170a and the source/drain filling film 170b. Although the power rail PR is shown as including a plurality of conductive films, it is not limited thereto. Of course, unlike what is shown, the power rail (PR) may be a single layer.

In some embodiments, a trench TR may be formed in the substrate 100. The bottom surface (TR_BS) of the trench (TR) may expose the bottom surface (100BS) of the substrate 100. The bottom surface (TR_BS) of the trench (TR) may be placed on the same plane as the bottom surface (100BS) of the substrate 100. The top surface of the trench TR may be placed on the same plane as the top surface 100US of the substrate 100.

In FIG. 2 , the width of the trench TR in the second direction Y may gradually increase and then decrease as it moves from the lower surface 100BS of the substrate 100 to the upper surface 100US of the substrate 100. . In FIG. 4 , the width of the trench TR in the first direction . That is, the sidewall TR_SW of the trench TR may have a convex shape. The sidewall TR_SW of the trench TR may be concave toward the metal pattern MP.

In some embodiments, the slope of the sidewall TR_SW of the trench TR may gradually decrease and then increase as it moves from the bottom surface 100BS of the substrate 100 to the top surface 100US of the substrate 100 . In this specification, the “slope of A” may be the angle formed between A and the baseline extending along the first direction (X) and/or the angle formed between A and the baseline extending along the second direction (Y). In other words, the trench TR may have a maximum width at any position between the lower surface 100BS and the upper surface 100US of the substrate 100. At the point where the width of the trench TR is maximum, the inclination of the sidewall TR_SW of the trench TR may be 90°. The width of the bottom surface (TR_BS) of the trench (TR) is not the maximum width of the trench (TR). The width of the top surface of the trench (TR) is not the maximum width of the trench (TR).

In some embodiments, the metal pattern MP may be disposed within the trench TR. The metal pattern MP may fill at least a portion of the trench TR. The metal pattern MP may not completely fill the trench TR, but is not limited thereto. The metal pattern MP may be disposed within the substrate 100 . The metal pattern (MP) may be placed on the power rail (PR). The metal pattern (MP) may be disposed between the power rail (PR) and the power rail via (PRVA). The metal pattern (MP) may be connected to the power rail (PR) and the power rail via (PRVA).

In some embodiments, the bottom surface MP_BS of the metal pattern MP may be placed on the same plane as the bottom surface 100BS of the substrate 100. The bottom surface (MP_BS) of the metal pattern (MP) may extend parallel to the bottom surface (100BS) of the substrate 100. The bottom surface (MP_BS) of the metal pattern (MP) may be the bottom surface (TR_BS) of the trench (TR).

In FIG. 2, the width of the metal pattern MP in the second direction Y may gradually increase and then decrease as it moves from the lower surface 100BS of the substrate 100 to the upper surface 100US of the substrate 100. there is. In FIG. 4, the width of the metal pattern MP in the first direction there is. That is, the sidewall MP_SW of the metal pattern MP may have a convex shape. The sidewall MP_SW of the metal pattern MP may be concave toward the center of the metal pattern MP. The sidewall (MP_SW) of the metal pattern (MP) may be the sidewall (TR_SW) of the trench (TR).

In some embodiments, the slope of the sidewall MP_SW of the metal pattern MP may gradually decrease and then increase as it moves from the lower surface 100BS of the substrate 100 to the upper surface 100US of the substrate 100. In other words, the metal pattern MP may have a maximum width at any position between the lower surface 100BS and the upper surface 100US of the substrate 100. At the point where the width of the metal pattern MP is maximum, the inclination of the sidewall MP_SW of the metal pattern MP may be 90°. The width of the bottom surface (MP_BS) of the metal pattern (MP) is not the maximum width of the metal pattern (MP).

In some embodiments, the upper surface MP_US of the metal pattern MP may be convex toward the lower surface 100BS of the substrate 100. The upper surface MP_US of the metal pattern MP may be an interface between the metal pattern MP and the field insulating layer 105. In other words, the boundary between the metal pattern MP and the field insulating layer 105 may be convex toward the lower surface 100BS of the substrate 100.

As previously described, the metal pattern MP does not completely fill the trench TR. The field insulating layer 105 may be disposed in the trench TR remaining after the metal pattern MP is filled. That is, at least a portion of the field insulating layer 105 may be disposed within the trench TR. That is, at least a portion of the field insulating film 105 may overlap the substrate 100 in the first direction (X) and/or the second direction (Y).

In some embodiments, at least a portion of the power rail via (PRVA) may be disposed within the trench (TR). At least a portion of the power rail via PRVA may overlap the substrate 100 in the first direction (X) and/or the second direction (Y). Additionally, in some embodiments, the height of the upper surface (MP_US) of the metal pattern (MP) relative to the lower surface (100BS) of the substrate 100 is the upper surface (MP_US) of the substrate 100 ( It may be smaller than the height of 100US), but is not limited to this.

The metal pattern MP may include a metal pattern barrier film MP_a and a metal pattern filling film MP_b on the metal pattern barrier film MP_a. Details regarding the materials included in the metal pattern barrier film MP_a and the metal pattern filling film MP_b may be the same as the descriptions of the source/drain barrier film 170a and the source/drain filling film 170b. Of course, unlike what is shown, the metal pattern MP may be a single layer.

The power rail via (PRVA) may be placed on the power rail (PR). The power rail via (PRVA) may be placed on the metal pattern (MP). The power rail via (PRVA) may be connected to the power rail (PR) through a metal pattern (MP). A power rail via (PRVA) may be disposed between the plurality of gate electrodes 120 . Additionally, the power rail via PRVA may be disposed between the first active pattern AP1 and the second active pattern AP2. Specifically, the power rail via (PRVA) may be placed on one side of the source/drain pattern 150. The power rail via (PRVA) may be disposed between the first source/drain contact 170 and the second source/drain contact 270.

The power rail via PRVA may penetrate the first interlayer insulating layer 190, the etch stop layer 160, and the field insulating layer 105 and be connected to the metal pattern MP. The bottom surface of the power rail via (PRVA) may contact the top surface (MP_US) of the metal pattern (MP).

In some embodiments, the height from the bottom surface 100BS of the substrate 100 to the bottom surface of the power rail via PRVA may be less than the thickness of the substrate 100. Based on the bottom surface 100BS of the substrate 100, the bottom surface of the power rail via PRVA may be disposed at a lower level than the top surface 100US of the substrate 100. However, the technical idea of the present invention is not limited thereto.

The first interlayer insulating film 190 may not cover the top surface (PRVA_US) of the power rail via (PRVA). For example, the top surface (PRVA_US) of the power rail via (PRVA) may be placed on the same plane as the top surface of the first interlayer insulating film 190. Additionally, the top surface (PRVA_US) of the power rail via (PRVA) may be placed on the same plane as the top surface (170US) of the first source/drain contact 170. Additionally, the top surface (PRVA_US) of the power rail via (PRVA) may be placed on the same plane as the top surface of the gate contact 180 and the top surface of the gate capping film 145.

In some embodiments, the power rail via (PRVA) may include a power rail via barrier layer (PRVA_a) and a power rail via filling layer (PRVA_b) on the power rail via barrier layer (PRVA_a). The information regarding the materials included in the power rail via barrier layer (PRVA_a) and the power rail via filling layer (PRVA_b) may be the same as the description of the source/drain barrier layer 170a and the source/drain filling layer 170b. .

The top stop film 191 may be disposed on the first interlayer insulating film 190, the gate capping film 145, the first source/drain contact 170, the power rail via (PRVA), and the gate contact 180. . The second interlayer insulating film 192 is disposed on the upper stop film 191.

The upper stop film 191 may include a material having an etch selectivity with respect to the second interlayer insulating film 192. The upper stop film 191 is, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide ( It may include at least one of SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), and combinations thereof. Although the upper stop film 191 is shown as a single film, it is not limited thereto. Unlike what is shown, the upper stop film 191 may not be formed. For example, the second interlayer insulating film 192 may include at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material.

The via plug 195 may be disposed within the second interlayer insulating film 192. The via plug 195 may pass through the upper stop film 191 and be directly connected to the first source/drain contact 170 and the power rail via (PRVA).

A portion of the via plug 195 may completely cover the top surface (170US) of the first source/drain contact 170 and the top surface (PRVA_US) of the power rail via (PRVA). That is, the first source/drain contact 170 and the power rail via (PRVA) may be connected to one via plug 195.

The via plug 195 may include a via barrier layer 195a and a via filling layer 195b. The via barrier layer 195a may extend along the sidewall and bottom surface of the via filling layer 195b. The via barrier film 195a may be formed of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), or nickel boron (NiB). , tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt) ), iridium (Ir), rhodium (Rh), and 2D material. The via filling film 195b is, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn). and molybdenum (Mo).

Hereinafter, a semiconductor device according to some other embodiments will be described with reference to FIGS. 5 to 17 . For convenience of explanation, the description will focus on differences from those described using FIGS. 1 to 4.

5 to 13 are diagrams for explaining semiconductor devices according to some other embodiments.

First, referring to FIG. 5 , the top surface (MP_US) of the metal pattern (MP) may be flat. The top surface (MP_US) of the metal pattern (MP) may be parallel to the top surface (100US) of the substrate 100. The top surface (MP_US) of the metal pattern (MP) may be placed on the same plane as the top surface (100US) of the substrate 100.

The interface between the metal pattern MP and the field insulating layer 105 may be flat. The boundary between the metal pattern MP and the field insulating layer 105 may lie on the same plane as the top surface 100US of the substrate 100.

The metal pattern (MP) may completely fill the trench (TR). The top surface (MP_US) of the metal pattern (MP) may be the top surface of the trench (TR). The field insulating layer 105 is not disposed in the trench TR. Additionally, the power rail via PRVA may not overlap the substrate 100 in the first direction (X) and/or the second direction (Y).

In some embodiments, the height of the upper surface (MP_US) of the metal pattern (MP) with respect to the lower surface (100BS) of the substrate 100 is the upper surface (100US) of the substrate 100 with respect to the lower surface (100BS) of the substrate 100. It may be equal to the height of .

Referring to FIG. 6 , the upper surface (MP_US) of the metal pattern (MP) may be concave toward the lower surface (100BS) of the substrate 100. At least a portion of the metal pattern MP may protrude from the upper surface 100US of the substrate 100 in the third direction Z. The boundary between the metal pattern MP and the field insulating layer 105 may be concave toward the lower surface 100BS of the substrate 100.

The field insulating layer 105 is not disposed in the trench TR. Additionally, the power rail via PRVA may not overlap the substrate 100 in the first direction (X) and/or the second direction (Y).

Referring to FIG. 7 , the width of the trench TR in the second direction Y gradually increases from the lower surface 100BS of the substrate 100 toward the upper surface 100US of the substrate 100. The width of the trench TR in the second direction Y does not decrease as it moves from the lower surface 100BS of the substrate 100 to the upper surface 100US of the substrate 100. Likewise, the width of the metal pattern MP in the second direction Y gradually increases from the lower surface 100BS of the substrate 100 toward the upper surface 100US of the substrate 100. The width of the metal pattern MP in the second direction Y does not decrease as it moves from the lower surface 100BS of the substrate 100 to the upper surface 100US of the substrate 100.

Although not shown, the width of the trench TR in the first direction It gradually increases as it moves towards the upper surface (100US). The width of the trench TR in the first direction It does not decrease as it goes toward .

That is, the width of the bottom surface TR_BS of the trench TR may be the maximum width of the trench TR. The width of the bottom surface MP_BS of the metal pattern MP may be the maximum width of the metal pattern MP.

Additionally, the slope of the sidewall TR_SW of the trench TR gradually decreases from the lower surface 100BS of the substrate 100 toward the upper surface 100US of the substrate 100. The slope of the side wall (TR_SW) of the trench (TR) has a minimum value at the bottom surface (TR_BS) of the trench (TR).

The slope of the sidewall MP_SW of the metal pattern MP gradually decreases from the lower surface 100BS of the substrate 100 toward the upper surface 100US of the substrate 100. The slope of the side wall (MP_SW) of the metal pattern (MP) has a minimum value at the bottom surface (MP_BS) of the metal pattern (MP).

Referring to FIG. 8, the power rail via (PRVA) may be misaligned with the metal pattern (MP). Misalignment of the power rail via (PRVA) and the metal pattern (MP) may mean that the bottom surface of the power rail via (PRVA) does not completely contact the top surface (MP_US) of the metal pattern (MP). Additionally, misalignment of the power rail via (PRVA) and the metal pattern (MP) may mean that the power rail via (PRVA) and the metal pattern (MP) include a portion that does not overlap in the third direction (Z). .

That is, at least a portion of the power rail via (PRVA) may contact the substrate 100 . At least a portion of the power rail via (PRVA) is disposed within the substrate 100 . At least a portion of the power rail via (PRVA) contacts the sidewall (MP_SW) of the metal pattern (MP). Since the sidewall (MP_SW) of the metal pattern (MP) has a convex structure, the probability of an electrical short occurring even if the power rail via (PRVA) and the metal pattern (MP) are misaligned may be reduced. Accordingly, a semiconductor device with improved reliability can be manufactured.

Referring to FIG. 9, the power rail via (PRVA) may be misaligned with the metal pattern (MP). Additionally, at least a portion of the power rail via (PRVA) may contact the power rail (PR). The bottom surface of the power rail via (PRVA) may contact the top surface of the power rail (PR). At least a portion of the power rail via (PRVA) is disposed within the substrate 100 . At least a portion of the power rail via (PRVA) may contact the sidewall (MP_SW) of the metal pattern (MP).

Referring to FIG. 10, the power rail (PR) and the metal pattern (MP) can be formed through a single process. That is, the boundary between the power rail (PR) and the metal pattern (MP) may be unclear. At this time, the power rail barrier film PR_a does not extend along the bottom surface MP_BS of the metal pattern MP. The power rail barrier layer (PR_a) may be formed through the same process as the metal pattern barrier layer (MP_a). The power rail filling film (PR_b) may be formed through the same process as the metal pattern filling film (MP_b).

Referring to FIG. 11 , in a semiconductor device according to some embodiments, the first source/drain contact 170 may include a first part 170_1 and a second part 170_2.

The first part 170_1 of the first source/drain contact 170 may be directly connected to the second part 170_2 of the first source/drain contact 170. The second portion 170_2 of the first source/drain contact 170 is a portion where the via plug 195 lands. The first source/drain contact 170 may be connected to the via plug 195 through the second portion 170_2 of the first source/drain contact 170. The first portion 170_1 of the first source/drain contact 170 is not a portion where the via plug 195 lands.

For example, the second portion 170_2 of the first source/drain contact 170 may be located at a portion connected to the via plug 195. The first portion 170_1 of the first source/drain contact 170 may be located in a portion not connected to the via plug 195.

In addition, although not shown, in order to prevent the gate contact 180 and the first source/drain contact 170 from being shorted, on both sides of the gate electrode 120 connected to the gate contact 180, The first part 170_1 of the first source/drain contact 170 may be located, and the second part 170_2 of the first source/drain contact 170 may not be located.

The top surface of the second part 170_2 of the first source/drain contact 170 is higher than the top surface of the first part 170_1 of the first source/drain contact 170. Based on the top surface of the field insulating film 105, the top surface of the second part 170_2 of the first source/drain contact 170 is higher than the top surface of the first part 170_1 of the first source/drain contact 170. . For example, the top surface of the first source/drain contact 170 may be the top surface of the second portion 170_2 of the first source/drain contact 170.

In FIG. 11, the first source/drain contact 170 is shown as having an 'L' shape, but is not limited thereto. Unlike shown, the first source/drain contact 170 may have a T-shape rotated by 180 degrees. In this case, the first part 170_1 of the first source/drain contact 170 may be disposed on both sides of the second part 170_2 of the first source/drain contact 170.

Referring to FIG. 12 , in a semiconductor device according to some embodiments, the first source/drain contact 170 may include a lower source/drain contact 171 and an upper source/drain contact 172.

The lower source/drain contact 171 may include a lower source/drain barrier layer 171a and a lower source/drain filling layer 171b. The upper source/drain contact 172 may include an upper source/drain barrier layer 172a and an upper source/drain filling layer 172b.

The top surface 170US of the first source/drain contact 170 may be the top surface 172US of the upper source/drain contact 172.

Description of the materials included in the lower source/drain barrier layer 171a and the upper source/drain barrier layer 172a may be the same as the description of the source/drain barrier layer 170a. Description of the materials included in the lower source/drain filling layer 171b and the upper source/drain filling layer 172b may be the same as the description of the source/drain filling layer 170b. Unlike shown, the upper source/drain contact 172 may be formed as a single layer.

Referring to FIG. 13, the first source/drain contact 170 may extend long in the second direction (Y). The first source/drain contact 170 may overlap the metal pattern MP in the third direction Z. The first source/drain contact 170 may overlap the power rail via (PRVA) in the third direction (Z).

In some embodiments, the bottom surface 170BS of the first source/drain contact 170 may contact the top surface PRVA_US of the power rail via PRVA. The top surface (PRVA_US) of the power rail via (PRVA) may be placed on the same plane as the top surface (150US) of the source/drain pattern 150. However, the technical idea of the present invention is not limited thereto.

14 to 17 are diagrams for explaining semiconductor devices according to some other embodiments.

14 is an example layout diagram for explaining a semiconductor device according to some embodiments. FIG. 15 is an exemplary cross-sectional view taken along line A-A' in FIG. 14. Figures 16 and 17 are cross-sectional views taken along line B-B' of Figure 14, respectively. For convenience of explanation, the description will focus on differences from those described using FIGS. 1 to 4.

Referring to FIGS. 14 to 17 , in semiconductor devices according to some embodiments, the first active pattern AP1 may include a lower pattern BP and at least one sheet pattern NS. Although not shown, the second active pattern AP2 may include a lower pattern and at least one sheet pattern.

The lower pattern BP may extend along the first direction (X). The sheet pattern NS may be disposed on the lower pattern BP and spaced apart from the lower pattern BP.

The sheet pattern NS may include a plurality of sheet patterns stacked in the third direction (Z). Although not shown, there are three sheet patterns NS, but this is only for convenience of explanation and is not limited thereto. The top surface of the sheet pattern NS disposed at the top of the sheet patterns NS may be the top surface of the first active pattern AP1.

The sheet pattern NS may be connected to the source/drain pattern 150. The sheet pattern NS may be a channel pattern used as a channel region of a transistor. For example, the sheet pattern NS may be a nanosheet or nanowire.

The lower pattern BP may include, for example, silicon or germanium, which are elemental semiconductor materials. Alternatively, the lower pattern BP1 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The sheet pattern NS may include, for example, silicon or germanium, which are elemental semiconductor materials. Alternatively, the sheet pattern NS may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The source/drain pattern 150 may be disposed on the lower pattern BP. The source/drain pattern 150 may be disposed between the plurality of gate electrodes 120 . The source/drain pattern 150 may be connected to the sheet pattern NS.

The power rail via (PRVA) may be disposed on one side of the lower pattern (BP). The power rail via (PRVA) is disposed on one side of the source/drain pattern 150. Additionally, a power rail via (PRVA) may be disposed between the plurality of gate electrodes 120 .

Although not shown, the gate insulating layer 130 may extend along the top surface of the lower pattern BP and the top surface of the field insulating layer 105. The gate insulating layer 130 may surround the sheet pattern NS.

The gate electrode 120 is disposed on the lower pattern BP. The gate electrode 120 intersects the lower pattern BP. The gate electrode 120 may surround the sheet pattern NS.

In FIG. 16, the gate spacer 140 may include an outer spacer 141 and an inner spacer 142. The inner spacer 142 may be disposed between the lower pattern BP and the sheet pattern NS and between adjacent sheet patterns NS.

In Figure 17, the gate spacer 140 may include only outer spacers. The inner spacer is not disposed between the lower pattern BP and the sheet pattern NS and between the adjacent sheet patterns NS.

18 to 29 are intermediate stage diagrams for explaining a semiconductor device manufacturing method according to some embodiments. For reference, FIGS. 18 to 29 may be cross-sectional views taken along line A-A' of FIG. 1. The following manufacturing method is explained in terms of cross-sectional views.

Referring to FIG. 18, a free substrate 100P may be provided. A first active pattern AP1 may be formed on the free substrate 100P. Although not shown, a second active pattern (AP2 in FIG. 1) may be formed on the free substrate 100P. The first active pattern AP1 and the second active pattern (AP2 in FIG. 1) may be formed by patterning the free substrate 100P. The free substrate 100P may be a silicon substrate, but is not limited thereto.

Referring to FIG. 19, a trench TR may be formed in the free substrate 100P. The trench TR may be formed through a wet etching process. Accordingly, the profile of the trench TR may be curved. The profile of the trench TR may be concave toward the center of the trench TR, but is not limited thereto.

Referring to FIG. 20, a sacrificial layer (SCL) may be formed on the free substrate 100P. The sacrificial layer (SCL) may cover the first active pattern (AP1) and the free substrate (100P). The sacrificial layer (SCL) may fill the trench (TR). The sacrificial layer SCL may include a material having an etch selectivity with the free substrate 100P and the first active pattern AP1.

Referring to FIG. 21 , the free substrate 100P may be exposed by removing a portion of the sacrificial layer (SCL). Additionally, the first active pattern AP1 may be exposed by removing a portion of the sacrificial layer SCL. As described previously, the sacrificial layer (SCL) has an etch selectivity with the free substrate (100P) and the first active pattern (AP1), so while the sacrificial layer (SCL) is removed, the free substrate (100P) and the first active pattern (AP1) ) may not be removed. That is, the sacrificial layer (SCL) can be selectively removed.

In some embodiments, the top surface (SCL_US) of the sacrificial layer (SCL) in the trench (TR) may be recessed toward the bottom surface of the free substrate (100P). This may be because the sacrificial layer SCL is overetched when the sacrificial layer SCL is removed.

Referring to FIG. 22, a field insulating film 105 may be formed. The field insulating film 105 may cover the upper surface 100US of the substrate 100. The field insulating layer 105 may cover the top surface (SCL_US) of the sacrificial layer (SCL). The field insulating layer 105 may cover the sidewall of the first active pattern AP1.

Subsequently, source/drain patterns 150 may be formed. The source/drain pattern 150 is formed on the first active pattern AP1. The source/drain pattern 150 may be an epitaxial pattern.

Subsequently, the etch stop layer 160, the first interlayer insulating layer 190, the first source/drain contact 170, and the power rail via (PRVA) may be formed.

First, an etch stop layer 160 may be formed on the top surface of the field insulating layer 105 and along the profile of the source/drain pattern 150. Subsequently, a first interlayer insulating layer 190 may be formed on the etch stop layer 160.

On the source/drain pattern 150, a first source/drain contact 170 is formed that penetrates the first interlayer insulating layer 190 and the etch stop layer 160. A contact silicide film 155 is formed at the boundary between the first source/drain contact 170 and the source/drain pattern 150.

Subsequently, a power rail via (PRVA) penetrating the first interlayer insulating layer 190, the etch stop layer 160, and the field insulating layer 105 may be formed on the sacrificial layer (SCL). A power rail via (PRVA) may be formed on one side of the source/drain pattern 150. The power rail via (PRVA) may be formed on one side of the first source/drain contact 170. The power rail via (PRVA) may land on the top surface (SCL_US) of the sacrificial layer (SCL).

Subsequently, an upper stop film 191, a second interlayer insulating film 192, and a via plug 195 are formed on the first source/drain contact 170, the power rail via (PRVA), and the first interlayer insulating film 190. can be formed.

Referring to FIG. 23 , a capping substrate 500 may be formed on the second interlayer insulating film 192 and the via plug 195. The capping substrate 500 may be a glass substrate or a silicon substrate. The semiconductor device can then be rotated 180 degrees.

Referring to FIG. 24, the substrate 100 may be formed by etching the free substrate 100P. The substrate 100 may include an upper surface (100US) and a lower surface (100BS) that are opposite to each other.

The sacrificial layer (SCL) can be exposed by etching the free substrate (100P). Specifically, the free substrate 100P may be etched through a planarization process (CMP; Chemical Mechanical Polishing). If the sacrificial layer (SCL) is exposed while performing the planarization process, the planarization process may be stopped. Accordingly, the bottom surface 100BS of the substrate 100 may be placed on the same plane as the bottom surface SCL_BS of the sacrificial layer SCL. The bottom surface 100BS of the substrate 100 may be placed on the same plane as the bottom surface TR_BS of the trench TR.

Referring to FIG. 25, the sacrificial layer (SCL) can be removed. The sacrificial layer (SCL) may be removed to expose the power rail via (PRVA) and the field insulating layer 105. The sacrificial layer (SCL) may have an etch selectivity with the substrate 100. Accordingly, the substrate 100 may not be removed while the sacrificial layer (SCL) is removed. The sacrificial layer (SCL) can be selectively removed.

Referring to FIG. 26, a metal pattern (MP) may be formed in the trench (TR). First, a metal pattern barrier layer MP_a may be formed along the sidewall TR_SW of the trench TR. A metal pattern filling film (MP_b) may be formed on the metal pattern barrier film (MP_a). Since the sidewall TR_SW of the trench TR has a convex shape, the sidewall MP_SW of the metal pattern MP may also have a convex shape. The metal pattern (MP) and the power rail via (PRVA) may be electrically connected to each other.

Referring to FIG. 27 , a lower insulating film 101 may be formed on and on the lower surface 100BS of the substrate 100. The lower insulating film 101 may cover the lower surface 100BS and the metal pattern MP of the substrate 100.

Referring to FIG. 28, a recess RC may be formed by etching a portion of the lower insulating film 101. The recess (RC) is formed on the metal pattern (MP). The recess RC may expose the bottom surface MP_BS of the metal pattern MP.

Referring to FIG. 29, a power rail (PR) may be formed filling the recess (RC). The power rail (PR) may be in contact with the metal pattern (MP). The power rail (PR) may be connected to the metal pattern (MP). The power rail (PR) may be connected to a power rail via (PRVA). The power rail (PR) may be electrically connected to the power rail via (PRVA) through a metal pattern (MP). Subsequently, although not shown, the capping substrate 500 may be removed and the semiconductor device may be rotated 180 degrees again.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: substrate 105: field insulating film
150: source/drain pattern 170, 270: source/drain contact
145: gate capping film 180: gate contact
120: gate electrode 140: gate spacer
PR: Power rail PRVA: Power rail via
MP: metal pattern
AP1, AP2: Active pattern 190: First interlayer insulating film

Claims (10)

A substrate including upper and lower surfaces opposing each other;
an active pattern extending in a first direction on the upper surface of the substrate;
a field insulating film covering sidewalls of the active pattern on the upper surface of the substrate;
a power rail disposed on a lower surface of the substrate and extending in the first direction;
a trench formed in the substrate and exposing a portion of the power rail; and
Filling at least a portion of the trench and including a metal pattern connected to the power rail,
The bottom surface of the trench is on the same plane as the bottom surface of the substrate,
The side walls of the trench have a convex shape,
At least a portion of the field insulating film is disposed within the trench. According to clause 1,
A semiconductor device wherein the width of the trench in a second direction crossing the first direction gradually increases and then decreases from the bottom surface of the substrate toward the top surface of the substrate. According to clause 1,
A semiconductor device wherein the width of the trench in the first direction gradually increases and then decreases from the bottom surface of the substrate toward the top surface of the substrate. According to clause 1,
A semiconductor device wherein an interface between the field insulating film and the metal pattern is convex toward the power rail. According to clause 1,
A semiconductor device wherein the slope of the sidewall of the trench gradually decreases and then increases as it moves from the lower surface of the substrate toward the upper surface of the substrate. A substrate including upper and lower surfaces opposing each other;
an active pattern extending in a first direction on the upper surface of the substrate;
a gate electrode covering the active pattern and extending in a second direction intersecting the first direction;
a power rail disposed on a lower surface of the substrate and extending in the first direction;
a metal pattern disposed within the substrate and connected to the power rail; and
A power rail via is disposed on one side of the gate electrode on the metal pattern and connected to the power rail through the metal pattern,
The bottom surface of the metal pattern extends parallel to the bottom surface of the substrate and lies on the same plane as the bottom surface of the substrate,
The width of the metal pattern in the second direction intersecting the first direction and the width in the first direction each include a portion that gradually increases from the lower surface of the substrate toward the upper surface of the substrate. Device. According to clause 6,
A semiconductor device wherein the height from the bottom surface of the substrate to the bottom surface of the power rail via is smaller than the thickness of the substrate. According to clause 6,
On the active pattern, it further includes a source/drain pattern disposed on one side of the gate electrode, and a source/drain contact on the source/drain pattern,
The power rail via is connected to the source/drain contact. According to clause 6,
At least a portion of the power rail via is in direct contact with the power rail. A substrate including upper and lower surfaces opposing each other;
an active pattern extending in a first direction on the upper surface of the substrate;
a gate electrode covering the active pattern and extending in a second direction intersecting the first direction;
a field insulating film covering sidewalls of the active pattern on the upper surface of the substrate;
a power rail disposed on a lower surface of the substrate and extending in the first direction;
a trench formed in the substrate, exposing a portion of the power rail, and having sidewalls having a convex shape;
a metal pattern that fills at least a portion of the trench and is connected to the power rail;
A source/drain pattern disposed on one side of the gate electrode on the active pattern;
Source/drain contacts on the source/drain pattern; and
A power rail via is disposed on one side of the gate electrode on the metal pattern and connected to the power rail through the metal pattern,
The bottom surface of the trench is on the same plane as the bottom surface of the substrate,
At least a portion of the field insulating film is disposed in the trench,
A semiconductor device wherein the width of the trench in the first direction and the width in the second direction gradually increase and then decrease respectively from the lower surface of the substrate toward the upper surface of the substrate.

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