KR20240050236A - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a first plurality of lower nanosheets stacked and spaced apart from each other in the vertical direction, an upper separation layer disposed on the first plurality of lower nanosheets, and a first plurality of first plurality of nanosheets stacked and spaced apart from each other in the vertical direction on the upper separation layer. An upper nanosheet, a first upper source/drain region disposed on the first side of the first plurality of upper nanosheets in the first horizontal direction, and opposite to the first side of the first plurality of upper nanosheets in the first horizontal direction. a second upper source/drain region disposed on the second side of the first plurality of upper nanosheets, extending in a second horizontal direction different from the first horizontal direction, the first plurality of lower nanosheets, an upper separation layer, and a first A first gate electrode surrounding each of the plurality of upper nanosheets, extending from the first side of the second horizontal direction of the first gate electrode in the first horizontal direction, from the lower surface of the first gate electrode to the upper surface of the first gate electrode. A first gate cut extending in a vertical direction, a first through via extending in a first horizontal direction inside the first gate cut and insulated from the first gate electrode, in a second horizontal direction on the first upper source/drain region. a first upper source/drain contact extending and electrically connected to the first upper source/drain region, and a second upper source/drain contact extending in a second horizontal direction on the second upper source/drain region, the second upper source/drain region and the first upper source/drain contact. and a second upper source/drain contact electrically connecting the through via.

Description

Semiconductor device

The present invention relates to semiconductor devices. Specifically, the present invention relates to a semiconductor device including a MBCFET ^TM (Multi-Bridge Channel Field Effect Transistor).

It is one of the scaling technologies to increase the density of integrated circuit devices, forming a fin-shaped or nanowire-shaped silicon body on a substrate and forming a gate on the surface of the silicon body. A multi-gate transistor has been proposed.

Because these multi-gate transistors use three-dimensional channels, they are easy to scale. Additionally, current control ability can be improved without increasing the gate length of the multi-gate transistor. In addition, short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed.

The problem that the present invention aims to solve is that, in a structure in which a plurality of upper nanosheets are stacked on a plurality of lower nanosheets, through vias connecting each of the lower source/drain contact and the upper source/drain contact are arranged in the gate cut. The goal is to provide a semiconductor device with improved integration.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

Some embodiments of a semiconductor device according to the technical idea of the present invention for solving the above problems include a first plurality of lower nanosheets stacked and spaced apart from each other in the vertical direction, and an upper separation disposed on the first plurality of lower nanosheets. layer, a first plurality of upper nanosheets stacked vertically apart from each other on the upper separation layer, a first upper source/drain region disposed on the first side of the first plurality of upper nanosheets in the first horizontal direction, 1 A second upper source/drain region disposed on the second side of the first plurality of upper nanosheets opposite to the first side of the plurality of upper nanosheets in the first horizontal direction, a second horizontal direction different from the first horizontal direction A first gate electrode that extends and surrounds each of the first plurality of lower nanosheets, the upper separation layer, and the first plurality of upper nanosheets, and a first horizontal direction on the first side of the second horizontal direction of the first gate electrode. A first gate cut extending vertically from the lower surface of the first gate electrode to the upper surface of the first gate electrode, extending in the first horizontal direction inside the first gate cut, and insulating from the first gate electrode A first through via, a first upper source/drain contact extending in a second horizontal direction on the first upper source/drain region and electrically connected to the first upper source/drain region, and on the second upper source/drain region. It extends in a second horizontal direction and includes a second upper source/drain contact electrically connecting the second upper source/drain region and the first through via.

Some other embodiments of a semiconductor device according to the technical idea of the present invention for solving the above problems include a plurality of lower nanosheets stacked vertically spaced apart from each other, an upper separation layer disposed on the plurality of lower nanosheets, and an upper A plurality of upper nanosheets stacked and spaced apart from each other in the vertical direction on the separation layer, a first gate cut extending in the first horizontal direction, and a second layer extending in the first horizontal direction and different from the first gate cut and the first horizontal direction. a second gate cut spaced apart in the horizontal direction, a first gate cut extending in a second horizontal direction between the first gate cut and the second gate cut, and surrounding each of the plurality of lower nanosheets, the upper separation layer, and the plurality of upper nanosheets. A gate electrode, extending in a second horizontal direction and separated from the first gate electrode by a first gate cut, a second gate electrode extending in a second horizontal direction and separated from the first gate electrode by a second gate cut A third gate electrode, a first lower source/drain region disposed on the first side of the plurality of lower nanosheets in the first horizontal direction, and a first lower source/drain region on the first side of the plurality of upper nanosheets in the first horizontal direction. A first upper source/drain region disposed on the drain region, a first through via extending in the first horizontal direction inside the first gate cut and insulated from each of the first and second gate electrodes, and a second gate cut. a second through via extending internally in a first horizontal direction and insulated from each of the first and third gate electrodes, extending in a second horizontal direction on the first upper source/drain region, the first upper source/drain region; A first upper source/drain contact electrically connecting the second through via, and a first lower source/drain contact disposed below the first lower source/drain region and electrically connected to the first lower source/drain region. Includes.

Some other embodiments of a semiconductor device according to the technical idea of the present invention for solving the above problems include a plurality of lower nanosheets stacked vertically spaced apart from each other, an upper separation layer disposed on the plurality of lower nanosheets, A plurality of upper nanosheets stacked vertically apart from each other on the upper separation layer, a first lower source/drain region disposed on the first side of the first horizontal direction of the plurality of lower nanosheets, and a first lower source/drain region of the plurality of lower nanosheets A second lower source/drain region disposed on the second side of the plurality of lower nanosheets opposite to the first side in the first horizontal direction, and a first upper portion disposed on the first side of the plurality of upper nanosheets in the first horizontal direction. Source/drain region, a second upper source/drain region disposed on the second side of the plurality of upper nanosheets opposite to the first side of the plurality of upper nanosheets in the first horizontal direction, a second upper source/drain region different from the first horizontal direction A gate electrode extending in the horizontal direction and surrounding each of the plurality of lower nanosheets, the upper separation layer, and the plurality of upper nanosheets, extending in the first horizontal direction from the first side of the second horizontal direction of the gate electrode, and the gate electrode a first gate cut extending in a vertical direction from the lower surface of the gate electrode to the upper surface of the gate electrode, extending in a first horizontal direction from the second side of the gate electrode opposite the first side of the gate electrode in a second horizontal direction, and A second gate cut extending in a vertical direction from the lower surface to the top surface of the gate electrode, a first through via extending in a first horizontal direction inside the first gate cut and insulated from the gate electrode, a first through via inside the second gate cut 1 a second through via extending in the horizontal direction and insulated from the gate electrode, a first lower source/drain contact disposed below the first lower source/drain region and electrically connected to the first lower source/drain region, A second lower source/drain contact extending in a second horizontal direction from the bottom of the second lower source/drain region and electrically connecting the second lower source/drain region and the first through via, and a first upper source/drain region. a first upper source/drain contact extending in a second horizontal direction on the first upper source/drain region and electrically connecting the first upper source/drain region and the second through via, and extending in a second horizontal direction on the second upper source/drain region; , and includes a second upper source/drain contact electrically connecting the second upper source/drain region and the first through via.

Other specific details of the invention are included in the detailed description and drawings.

1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention.
Figure 2 is a cross-sectional view taken along line AA' of Figure 1.
Figure 3 is a cross-sectional view taken along line BB' in Figure 1.
Figure 4 is a cross-sectional view taken along line CC' of Figure 1.
Figure 5 is a cross-sectional view taken along line DD' in Figure 1.
6 to 58 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.
Figure 59 is a layout diagram for explaining a semiconductor device according to some other embodiments of the present invention.
Figure 60 is a layout diagram for explaining a semiconductor device according to another embodiment of the present invention.
Figure 61 is a cross-sectional view for explaining a semiconductor device according to another embodiment of the present invention.
Figure 62 is a cross-sectional view for explaining a semiconductor device according to another embodiment of the present invention.

In the drawings below of semiconductor devices according to some embodiments, the semiconductor device is illustratively described as including a transistor (MBCFET ^TM (Multi-Bridge Channel Field Effect Transistor)) including a nanosheet. The technical idea of the present invention is not limited thereto. In some other embodiments, the semiconductor device may include a fin-type transistor (FinFET), a tunneling FET, or a three-dimensional (3D) transistor including a channel region in the shape of a fin-type pattern. Additionally, semiconductor devices according to some other embodiments may include a bipolar junction transistor or a horizontal double diffusion transistor (LDMOS).

Hereinafter, a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 1 to 5.

1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1. Figure 3 is a cross-sectional view taken along line B-B' in Figure 1. Figure 4 is a cross-sectional view taken along line C-C' in Figure 1. Figure 5 is a cross-sectional view taken along line D-D' in Figure 1.

1 to 5, a semiconductor device according to some embodiments of the present invention includes a first lower interlayer insulating film 100, a lower separation layer 110, and first to fourth plurality of lower nanosheets BNW1 and BNW2. , BNW3, BNW4), upper separation layer 120, first to fourth plurality of upper nanosheets (UNW1, UNW2, UNW3, UNW4), first to twelfth gate electrodes (G1 to G12), gate spacer (131) ), gate insulating film 132, capping pattern 133, first to third lower source/drain regions (BSD1, BSD2, BSD3), first to third upper source/drain regions (USD1, USD2, USD3), Second lower interlayer insulating film 140, liner layer 150, third lower interlayer insulating film 160, first upper interlayer insulating film 170, second upper interlayer insulating film 180, first to fourth lower source/ Drain contacts (BCA1, BCA2, BCA3, BCA4), first to third upper source/drain contacts (UCA1, UCA2, UCA3), lower silicide layer (SL1), upper silicide layer (SL2), gate contact (CB), First and second gate cuts (GC1, GC2), first to third through vias (TV1, TV2, TV3), lower connection pad (BP), upper connection pad (UP), first and second lower vias ( BV1, BV2), and first and second upper vias (UV1, UV2).

For example, the first lower interlayer insulating film 100 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethylcycloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), oxyDitertiaryButoxySiloxane ( DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate Glass), SiLK , Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, mesoporous silica, or a combination thereof, but the technical idea of the present invention is not limited thereto.

Hereinafter, each of the first horizontal direction DR1 and the second horizontal direction DR2 may be defined as a direction parallel to the top surface of the first lower interlayer insulating layer 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 may be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 may be defined as a direction perpendicular to the top surface of the first lower interlayer insulating layer 100.

Each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 may be disposed on the first lower interlayer insulating film 100. Each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 may be spaced apart from the first lower interlayer insulating film 100 in the vertical direction DR3. The second plurality of lower nanosheets BNW2 may be spaced apart from the first plurality of lower nanosheets BNW1 in the first horizontal direction DR1. The third plurality of lower nanosheets BNW3 may be spaced apart from the second plurality of lower nanosheets BNW2 in the first horizontal direction DR1. The fourth plurality of lower nanosheets BNW4 may be spaced apart from the third plurality of lower nanosheets BNW3 in the first horizontal direction DR1.

Each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 may include a plurality of nanosheets stacked and spaced apart from each other in the vertical direction DR3. 2 and 3, each of the first to fourth plurality of lower nanosheets (BNW1, BNW2, BNW3, BNW4) is shown as including two nanosheets stacked in the vertical direction (DR3), but this is for the purpose of explanation. This is for convenience. In some other embodiments, each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 may include three or more nanosheets stacked in the vertical direction DR3. For example, each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 may include silicon (Si). In some other embodiments, each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 may include silicon germanium (SiGe).

The lower separation layer 110 may be disposed between the first lower interlayer insulating film 100 and the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4, respectively. The lower surface of the lower separation layer 110 may be in contact with the first lower interlayer insulating film 100. For example, the upper surface of the lower separation layer 110 may be spaced apart from each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 in the vertical direction DR3. For example, the lower separation layer 110 may be disposed only on the lower portion of each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4. For example, the sidewall of the lower separation layer 110 may be aligned with the sidewalls of each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 in the vertical direction DR3.

The upper separation layer 120 may be disposed on each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4. For example, the lower surface of the upper separation layer 120 may be spaced apart from each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4 in the vertical direction DR3. For example, the upper separation layer 120 may be disposed only on top of each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4. For example, the sidewall of the upper separation layer 120 may be aligned in the vertical direction DR3 with the sidewall of each of the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4.

Each of the lower separation layer 110 and the upper separation layer 120 may include an insulating material. For example, the lower separation layer 110 and the upper separation layer 120 are each made of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), and silicon oxynitride. (SiON) and combinations thereof. However, the technical idea of the present invention is not limited thereto.

Each of the first to fourth plurality of upper nanosheets (UNW1, UNW2, UNW3, and UNW4) may be disposed on the upper separation layer 120. Each of the first to fourth plurality of upper nanosheets UNW1, UNW2, UNW3, and UNW4 may be spaced apart from the upper separation layer 120 in the vertical direction DR3. For example, each of the first to fourth plurality of upper nanosheets (UNW1, UNW2, UNW3, UNW4) is oriented in a vertical direction (DR3) with each of the first to fourth plurality of lower nanosheets (BNW1, BNW2, BNW3, BNW4). ) can be overlapped. The second plurality of upper nanosheets UNW2 may be spaced apart from the first plurality of upper nanosheets UNW1 in the first horizontal direction DR1. The third plurality of upper nanosheets UNW3 may be spaced apart from the second plurality of upper nanosheets UNW2 in the first horizontal direction DR1. The fourth plurality of upper nanosheets UNW4 may be spaced apart from the third plurality of upper nanosheets UNW3 in the first horizontal direction DR1.

For example, the sidewalls of each of the first to fourth plurality of upper nanosheets (UNW1, UNW2, UNW3, and UNW4) are the sidewalls of each of the first to fourth plurality of lower nanosheets (BNW1, BNW2, BNW3, and BNW4). Can be aligned vertically. However, the technical idea of the present invention is not limited thereto. That is, in some other embodiments, the width of each of the first to fourth plurality of upper nanosheets (UNW1, UNW2, UNW3, UNW4) in the first horizontal direction (DR1) is the width of the first to fourth plurality of lower nanosheets (UNW1, UNW2, UNW3, UNW4). BNW1, BNW2, BNW3, BNW4) may be different from the width of each first horizontal direction (DR1).

Each of the first to fourth plurality of upper nanosheets UNW1, UNW2, UNW3, and UNW4 may include a plurality of nanosheets stacked and spaced apart from each other in the vertical direction DR3. 2 and 3, each of the first to fourth plurality of upper nanosheets (UNW1, UNW2, UNW3, UNW4) is shown as including two nanosheets stacked in the vertical direction (DR3), but this is for the purpose of explanation. This is for convenience. In some other embodiments, each of the first to fourth plurality of upper nanosheets (UNW1, UNW2, UNW3, and UNW4) may include three or more nanosheets stacked in the vertical direction (DR3). For example, each of the first to fourth plurality of upper nanosheets UNW1, UNW2, UNW3, and UNW4 may include silicon (Si). In some other embodiments, each of the first to fourth plurality of upper nanosheets UNW1, UNW2, UNW3, and UNW4 may include silicon germanium (SiGe).

Each of the first to twelfth gate electrodes G1 to G12 may extend in the second horizontal direction DR2 on the first lower interlayer insulating film 100 . The fifth to eighth gate electrodes G5, G6, G7, and G8 may be sequentially spaced apart in the first horizontal direction DR1. The first gate electrode G1 may be spaced apart from the fifth gate electrode G5 in the second horizontal direction DR2. The first gate electrode G1 may surround each of the lower separation layer 110, the first plurality of lower nanosheets BNW1, the upper separation layer 120, and the first plurality of upper nanosheets UNW1. The second gate electrode G2 may be spaced apart from the sixth gate electrode G6 in the second horizontal direction DR2. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The second gate electrode G2 may surround each of the lower separation layer 110, the second plurality of lower nanosheets BNW2, the upper separation layer 120, and the second plurality of upper nanosheets UNW2.

The third gate electrode G3 may be spaced apart from the seventh gate electrode G7 in the second horizontal direction DR2. The third gate electrode G3 may be spaced apart from the second gate electrode G2 in the first horizontal direction DR1. The third gate electrode G3 may surround each of the lower separation layer 110, the third plurality of lower nanosheets BNW3, the upper separation layer 120, and the third plurality of upper nanosheets UNW3. The fourth gate electrode G4 may be spaced apart from the eighth gate electrode G8 in the second horizontal direction DR2. The fourth gate electrode G4 may be spaced apart from the third gate electrode G3 in the first horizontal direction DR1. The fourth gate electrode G4 may surround each of the lower separation layer 110, the fourth plurality of lower nanosheets BNW4, the upper separation layer 120, and the fourth plurality of upper nanosheets UNW4.

The ninth gate electrode G9 may be spaced apart from the first gate electrode G1 in the second horizontal direction DR2. The tenth gate electrode G10 may be spaced apart from the second gate electrode G2 in the second horizontal direction DR2. The tenth gate electrode G10 may be spaced apart from the ninth gate electrode G9 in the first horizontal direction DR1. The eleventh gate electrode G11 may be spaced apart from the third gate electrode G3 in the second horizontal direction DR2. The eleventh gate electrode G11 may be spaced apart from the tenth gate electrode G10 in the first horizontal direction DR1. The twelfth gate electrode G12 may be spaced apart from the fourth gate electrode G4 in the second horizontal direction DR2. The twelfth gate electrode G12 may be spaced apart from the eleventh gate electrode G11 in the first horizontal direction DR1.

For example, each of the first to twelfth gate electrodes G1 to G12 may contact the first lower interlayer insulating layer 100. Each of the first to twelfth gate electrodes (G1 to G12) is, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), Tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide ( TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni) , platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide. At least one of (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof may include.

The gate spacer 131 may extend in the second horizontal direction DR2 on the uppermost nanosheet among the first plurality of upper nanosheets UNW1 and the first lower interlayer insulating film 100. For example, the gate spacer 131 may extend in the second horizontal direction DR2 along both sidewalls of each of the first to twelfth gate electrodes G1 to G12. The gate spacer 131 is, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN). ), silicon oxycarbide (SiOC), and combinations thereof. However, the technical idea of the present invention is not limited thereto.

The first lower source/drain region BSD1 may be disposed on the first side of the first plurality of lower nanosheets BNW1 in the first horizontal direction DR1. For example, the first lower source/drain region BSD1 may be disposed between the first plurality of lower nanosheets BNW1 and the second plurality of lower nanosheets BNW2. The first lower source/drain region BSD1 may contact each of the first and second plurality of lower nanosheets BNW1 and BNW2. For example, the lower surface of the first lower source/drain region BSD1 may be formed between the upper surface of the lower separation layer 110 and the lower surface of the lowermost nanosheet of the second plurality of lower nanosheets BNW2. For example, the upper surface of the first lower source/drain region BSD1 may be formed between the upper surface of the uppermost nanosheet of the second plurality of lower nanosheets BNW2 and the lower surface of the upper separation layer 120.

The second lower source/drain region BSD2 is formed on the second side of the second plurality of lower nanosheets BNW2 opposite to the first side of the second plurality of lower nanosheets BNW2 in the first horizontal direction DR1. can be placed in For example, the second lower source/drain region BSD2 may be disposed between the second plurality of lower nanosheets BNW2 and the third plurality of lower nanosheets BNW3. The second lower source/drain region BSD2 may contact each of the second and third plurality of lower nanosheets BNW2 and BNW3. For example, the lower surface of the second lower source/drain region BSD2 may be formed between the upper surface of the lower separation layer 110 and the lower surface of the lowermost nanosheet of the second plurality of lower nanosheets BNW2. For example, the upper surface of the second lower source/drain region BSD2 may be formed between the upper surface of the uppermost nanosheet of the second plurality of lower nanosheets BNW2 and the lower surface of the upper separation layer 120.

The third lower source/drain region BSD3 may be disposed between the third plurality of lower nanosheets BNW3 and the fourth plurality of lower nanosheets BNW4. The third lower source/drain region BSD3 may contact each of the third and fourth plurality of lower nanosheets BNW3 and BNW4. For example, the lower surface of the third lower source/drain region BSD3 may be formed between the upper surface of the lower separation layer 110 and the lower surface of the lowermost nanosheet of the third plurality of lower nanosheets BNW3. For example, the upper surface of the third lower source/drain region BSD3 may be formed between the upper surface of the uppermost nanosheet of the third plurality of lower nanosheets BNW3 and the lower surface of the upper separation layer 120.

The first upper source/drain region USD1 may be disposed on the first lower source/drain region BSD1. The first upper source/drain region USD1 may be spaced apart from the first lower source/drain region BSD1 in the vertical direction DR3. The first upper source/drain region USD1 may be disposed on the first side of the first plurality of upper nanosheets UNW1 in the first horizontal direction DR1. For example, the first upper source/drain region USD1 may be disposed between the first plurality of upper nanosheets UNW1 and the second plurality of upper nanosheets UNW2. For example, the lower surface of the first upper source/drain region USD1 may be formed between the upper surface of the upper separation layer 120 and the lower surface of the lowermost nanosheet of the second plurality of upper nanosheets UNW2.

The second upper source/drain region USD2 may be disposed on the second lower source/drain region BSD2. The second upper source/drain region USD2 may be spaced apart from the second lower source/drain region BSD2 in the vertical direction DR3. The second upper source/drain region USD2 is formed on the second side of the second plurality of upper nanosheets UNW2 opposite to the first side of the second plurality of upper nanosheets UNW2 in the first horizontal direction DR1. can be placed in For example, the second upper source/drain region USD2 may be disposed between the second plurality of upper nanosheets UNW2 and the third plurality of upper nanosheets UNW3. For example, the lower surface of the second upper source/drain region USD2 may be formed between the upper surface of the upper separation layer 120 and the lower surface of the lowermost nanosheet of the second plurality of upper nanosheets UNW2.

The third upper source/drain region USD3 may be disposed on the third lower source/drain region BSD3. The third upper source/drain region USD3 may be spaced apart from the third lower source/drain region BSD3 in the vertical direction DR3. The third upper source/drain region USD3 may be disposed between the third plurality of upper nanosheets UNW3 and the fourth plurality of upper nanosheets UNW4. For example, the lower surface of the third upper source/drain region USD3 may be formed between the upper surface of the upper separation layer 120 and the lower surface of the lowermost nanosheet of the third plurality of upper nanosheets UNW3.

For example, the gate insulating film 132 may be disposed between each of the first to fourth gate electrodes G1, G2, G3, and G4 and the lower separation layer 110. The gate insulating film 132 may be disposed between each of the first to fourth gate electrodes G1, G2, G3, and G4 and the upper isolation layer 120. The gate insulating film 132 may be disposed between each of the first to fourth gate electrodes G1, G2, G3, and G4 and the gate spacer 131.

For example, the gate insulating film 132 may be disposed between the first gate electrode G1 and each of the first plurality of lower nanosheets BNW1 and the first plurality of upper nanosheets UNW1. The gate insulating film 132 may be disposed between the second gate electrode G2 and each of the second plurality of lower nanosheets BNW2 and the second plurality of upper nanosheets UNW2. The gate insulating film 132 may be disposed between the third gate electrode G3 and each of the third plurality of lower nanosheets BNW3 and the third plurality of upper nanosheets UNW3. The gate insulating film 132 may be disposed between the fourth gate electrode G4 and each of the fourth plurality of lower nanosheets BNW4 and the fourth plurality of upper nanosheets UNW4.

The gate insulating film 132 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. High dielectric constant materials include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, and zirconium. oxide (zirconium oxide), zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium May contain one or more of strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. there is.

Semiconductor devices according to some other embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer 132 may include a ferroelectric material layer with ferroelectric properties and a paraelectric material layer with paraelectric properties.

The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance will be less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

When a ferroelectric material film with a negative capacitance and a paraelectric material film with a positive capacitance are connected in series, the overall capacitance value of the ferroelectric material film and the paraelectric material film connected in series may increase. By taking advantage of the increase in overall capacitance value, a transistor including a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV/decade at room temperature.

A ferroelectric material film may have ferroelectric properties. Ferroelectric material films include, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium oxide. It may contain at least one of titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The ferroelectric material film may further include a doped dopant. For example, dopants include aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), and cerium (Ce). ), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on what kind of ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film is, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). It can be included.

When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% of zirconium.

A paradielectric material film may have paradielectric properties. For example, the paradielectric material film may include at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paradielectric material film may include, but is not limited to, at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide.

The ferroelectric material film and the paraelectric material film may include the same material. A ferroelectric material film may have ferroelectric properties, but a paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

The ferroelectric material film may have a thickness having ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness representing ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

As an example, the gate insulating layer 132 may include one ferroelectric material layer. As another example, the gate insulating film 132 may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film 132 may have a stacked structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

The capping pattern 133 may extend in the second horizontal direction DR2 on the top surface of each of the first to twelfth gate electrodes G1 to G12. For example, the capping pattern 133 is formed on the top surface of the gate spacer 131, the top surface of the gate insulating film 132, and the top surfaces of each of the first to twelfth gate electrodes G1 to G12 in the second horizontal direction DR2. It may be extended. However, the technical idea of the present invention is not limited thereto. In some other embodiments, the capping pattern 133 may be disposed between the gate spacers 131. The capping pattern 133 is, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. may include. However, the technical idea of the present invention is not limited thereto.

The second lower interlayer insulating film 140 may be disposed on the first lower interlayer insulating film 100. For example, the second lower interlayer insulating film 140 may contact the sidewall of the lower separation layer 110 in the first horizontal direction DR1. The third lower interlayer insulating film 160 may be disposed on the first lower interlayer insulating film 100 and the second lower interlayer insulating film 140. The third lower interlayer insulating film 160 may cover each of the first to third lower source/drain regions BSD1, BSD2, and BSD3.

The first upper interlayer insulating film 170 may be disposed on the third lower interlayer insulating film 160. The first upper interlayer insulating film 170 may cover each of the first to third upper source/drain regions USD1, USD2, and USD3. The first upper interlayer insulating film 170 may surround the sidewall of the gate spacer 131 and the sidewall of the capping pattern 133. For example, the top surface of the first upper interlayer insulating film 170 may be formed on the same plane as the top surface of the capping pattern 133. However, the technical idea of the present invention is not limited thereto. In some other embodiments, the first upper interlayer insulating film 170 may cover the top surface of the capping pattern 133.

Each of the second lower interlayer insulating film 140, the third lower interlayer insulating film 160, and the first upper interlayer insulating film 170 includes, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. can do. For example, the second lower interlayer insulating film 140, the third lower interlayer insulating film 160, and the first upper interlayer insulating film 170 may each include the same material, but the technical idea of the present invention is not limited thereto. That is not the case.

The liner layer 150 may be disposed between the second lower interlayer insulating film 140 and the third lower interlayer insulating film 160. The liner layer 150 may be disposed between the lower separation layer 110 and the third lower interlayer insulating layer 160. The liner layer 150 may be disposed between the upper separation layer 120 and the third lower interlayer insulating layer 160. The liner layer 150 may be disposed between the gate insulating layer 132 and the third lower interlayer insulating layer 160. The liner layer 150 may be disposed between each of the first to third lower source/drain regions BSD1, BSD2, and BSD3 and the third lower interlayer insulating film 160.

Additionally, the liner layer 150 may be disposed between the gate spacer 131 and the first upper interlayer insulating layer 170. The liner layer 150 may be disposed between the capping pattern 133 and the first upper interlayer insulating layer 170. The liner layer 150 may be disposed between each of the first to third upper source/drain regions USD1, USD2, and USD3 and the first upper interlayer insulating film 170. The liner layer 150 may be disposed between the third lower interlayer insulating film 160 and the first upper interlayer insulating film 170.

For example, the liner layer 150 may be formed conformally. The liner layer 150 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

The first gate cut GC1 is formed between each of the first to fourth gate electrodes G1, G2, G3, and G4 and the fifth to eighth gate electrodes G5, G6, G7, and G8 in the first horizontal direction ( It can be extended to DR1). For example, the first gate cut GC1 may be disposed on the first side of each of the first to fourth gate electrodes G1, G2, G3, and G4 in the second horizontal direction DR2. The first gate cut GC1 may separate the first to fourth gate electrodes G1, G2, G3, and G4 and the fifth to eighth gate electrodes G5, G6, G7, and G8.

The second gate cut GC2 may be spaced apart from the first gate cut GC1 in the second horizontal direction DR2. The second gate cut GC2 is formed between each of the first to fourth gate electrodes G1, G2, G3, and G4 and the ninth to twelfth gate electrodes G9, G10, G11, and G12 in the first horizontal direction ( It can be extended to DR1). For example, the second gate cut GC2 is formed by forming the first to fourth gates opposite the first sides of each of the first to fourth gate electrodes G1, G2, G3, and G4 in the second horizontal direction DR2. Each of the electrodes G1, G2, G3, and G4 may be disposed on the second side of the second horizontal direction DR2. The second gate cut GC2 may separate the first to fourth gate electrodes G1, G2, G3, and G4 and the ninth to twelfth gate electrodes G9, G10, G11, and G12.

For example, each of the first gate cut (GC1) and the second gate cut (GC2) is connected to the first to fourth gate electrodes (G1) from the lower surfaces of each of the first to fourth gate electrodes (G1, G2, G3, and G4). , G2, G3, G4) may extend in the vertical direction (DR3) to each upper surface. For example, the lower surfaces of each of the first gate cut GC1 and the second gate cut GC2 may be formed on the same plane as the lower surfaces of each of the first to fourth gate electrodes G1, G2, G3, and G4. there is.

For example, the first gate cut GC1 and the second gate cut GC2 each extend from the top surface of the first lower interlayer insulating film 100 to the top surface of the first upper interlayer insulating film 170 and the top surface of the capping pattern 133. It can extend in the vertical direction (DR3). For example, the top surface of each of the first gate cut GC1 and the second gate cut GC2 may be formed on the same plane as the top surface of the first upper interlayer insulating film 170 and the top surface of the capping pattern 133. there is. For example, the first gate cut GC1 may contact the sidewalls of each of the first to eighth gate electrodes G1 to G8. For example, the second gate cut GC2 is in contact with the sidewalls of each of the first to fourth gate electrodes G1, G2, G3, and G4 and the ninth to twelfth gate electrodes G9, G10, G11, and G12. You can.

In some embodiments, for example, each of the first gate cut GC1 and the second gate cut GC2 may include silicon oxide (SiO ₂ ). In some other embodiments, for example, the first gate cut (GC1) and the second gate cut (GC2) each include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxycarbonitride. It may include at least one of (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

The first through via TV1 may extend in the first horizontal direction DR1 within the first gate cut GC1. For example, the first through via TV1 may overlap each of the first gate electrode G1 and the second gate electrode G2 in the second horizontal direction DR2. For example, the first through via TV1 does not overlap each of the third and fourth gate electrodes G3 and G4 in the second horizontal direction DR2. For example, the first through via TV1 may be electrically insulated from each of the first gate electrode G1, the second gate electrode G2, the fifth gate electrode G5, and the sixth gate electrode G6. there is. That is, a first gate cut (GC1) is formed between each of the first gate electrode (G1), the second gate electrode (G2), the fifth gate electrode (G5), and the sixth gate electrode (G6) and the first through via (TV1). ) can be placed.

For example, the lowermost surface of the first through via TV1 may contact the first lower interlayer insulating layer 100. For example, the lowermost surface of the first through via TV1 may be formed on the same plane as the lowermost surface of the first gate cut GC1. For example, the lowermost surface of the first through via (TV1) is the lower surface of each of the first gate electrode (G1), the second gate electrode (G2), the fifth gate electrode (G5), and the sixth gate electrode (G6). It can be formed on the same plane. For example, the top surface of the first through via (TV1) is lower than the top surfaces of each of the first gate electrode (G1), the second gate electrode (G2), the fifth gate electrode (G5), and the sixth gate electrode (G6). can be formed. For example, the first gate cut GC1 may cover the top surface of the first through via TV1. For example, the first through via TV1 may include a conductive material.

The second through via TV2 may extend in the first horizontal direction DR1 within the first gate cut GC1. The second through via TV2 may be spaced apart from the first through via TV1 in the first horizontal direction DR1. A first gate cut (GC1) may be disposed between the first through via (TV1) and the second through via (TV2). For example, the second through via TV2 may overlap the fourth gate electrode G4 in the second horizontal direction DR2. For example, the second through via TV2 does not overlap each of the first to third gate electrodes G1, G2, and G3 in the second horizontal direction DR2. For example, the second through via TV2 may be electrically insulated from each of the fourth gate electrode G4 and the eighth gate electrode G8. That is, the first gate cut GC1 may be disposed between each of the fourth gate electrode G4 and the eighth gate electrode G8 and the second through via TV2.

For example, the lowermost surface of the second through via TV2 may contact the first lower interlayer insulating layer 100. For example, the lowermost surface of the second through via TV2 may be formed on the same plane as the lowermost surface of the first gate cut GC1. For example, the lowermost surface of the second through via TV2 may be formed on the same plane as the lowermost surface of each of the fourth gate electrode G4 and the eighth gate electrode G8. For example, the top surface of the second through via TV2 may be formed to be lower than the top surfaces of each of the fourth gate electrode G4 and the eighth gate electrode G8. For example, the first gate cut GC1 may cover the top surface of the second through via TV2. For example, the second through via TV2 may include a conductive material.

The third through via TV3 may extend in the first horizontal direction DR1 within the second gate cut GC2. For example, the third through via TV3 may overlap each of the first to fourth gate electrodes G1, G2, G3, and G4 in the second horizontal direction DR2. For example, the third through via TV3 may be electrically insulated from each of the first to fourth gate electrodes G1, G2, G3, and G4. That is, the second gate cut GC2 may be disposed between each of the first to fourth gate electrodes G1, G2, G3, and G4 and the third through via TV3.

For example, the lowermost surface of the third through via TV3 may contact the first lower interlayer insulating layer 100. For example, the lowermost surface of the third through via TV3 may be formed on the same plane as the lowermost surface of the second gate cut GC2. For example, the lowermost surface of the third through via TV3 may be formed on the same plane as the lowermost surface of each of the first to fourth gate electrodes G1, G2, G3, and G4. For example, the top surface of the third through via TV3 may be formed lower than the top surface of each of the first to fourth gate electrodes G1, G2, G3, and G4. For example, the second gate cut GC2 may cover the top surface of the third through via TV3. For example, the third through via TV3 may include a conductive material.

The first lower source/drain contact BCA1 may be disposed between the first gate electrode G1 and the second gate electrode G2. The first lower source/drain contact BCA1 penetrates the second lower interlayer insulating film 140, the third lower interlayer insulating film 160, and the liner layer 150 in the vertical direction DR3 to form the first lower source/drain region. It can be connected to the lower part of (BSD1). For example, the bottom surface of the first lower source/drain contact BCA1 may be in contact with the first lower interlayer insulating layer 100.

The second lower source/drain contact BCA2 may be disposed between the second gate electrode G2 and the third gate electrode G3. The second lower source/drain contact BCA2 may extend in the second horizontal direction DR2. The second lower source/drain contact BCA2 penetrates the second lower interlayer insulating film 140, the third lower interlayer insulating film 160, and the liner layer 150 in the vertical direction DR3 to form the second lower source/drain region. It can be connected to the lower part of (BSD2). Additionally, the second lower source/drain contact BCA2 may be connected to the lower part of the first through via TV1. That is, the second lower source/drain contact BCA2 may electrically connect the second lower source/drain region BSD2 and the first through via TV1. For example, the bottom surface of the second lower source/drain contact BCA2 may be in contact with the first lower interlayer insulating layer 100.

The third lower source/drain contact BCA3 may be disposed between the third gate electrode G3 and the fourth gate electrode G4. The third lower source/drain contact BCA3 penetrates the second lower interlayer insulating film 140, the third lower interlayer insulating film 160, and the liner layer 150 in the vertical direction DR3 to form the third lower source/drain region. It can be connected to the lower part of (BSD3). For example, the bottom surface of the third lower source/drain contact BCA3 may be in contact with the first lower interlayer insulating layer 100.

The fourth lower source/drain contact BCA4 may be disposed between the fifth gate electrode G5 and the sixth gate electrode G6. The fourth lower source/drain contact BCA4 may extend in the second horizontal direction DR2. The fourth lower source/drain contact BCA4 may be connected to the lower part of the first through via TV1. For example, the lower surface of the fourth lower source/drain contact BCA4 may be in contact with the first lower interlayer insulating layer 100.

Each of the first to fourth lower source/drain contacts BCA1, BCA2, BCA3, and BCA4 may include a conductive material. 2, 4, and 5, each of the first to fourth lower source/drain contacts (BCA1, BCA2, BCA3, and BCA4) is shown as being formed as a single layer, but this is for convenience of explanation, and the present invention The technical idea is not limited to this. That is, each of the first to fourth lower source/drain contacts (BCA1, BCA2, BCA3, and BCA4) may be formed as a multilayer.

The first upper source/drain contact UCA1 may be disposed between the first gate electrode G1 and the second gate electrode G2. The first upper source/drain contact UCA1 may extend in the second horizontal direction DR2. The first upper source/drain contact (UCA1) may penetrate the first upper interlayer insulating film 170 and the liner layer 150 in the vertical direction (DR3) and be connected to the upper part of the first upper source/drain region (USD1). . Additionally, the first upper source/drain contact (UCA1) may be connected to the upper part of the third through via (TV3). That is, the first upper source/drain contact (UCA1) may electrically connect the first upper source/drain region (USD1) and the third through via (TV3).

The second upper source/drain contact UCA2 may be disposed between the second gate electrode G2 and the third gate electrode G3. The second upper source/drain contact UCA2 may extend in the second horizontal direction DR2. The second upper source/drain contact UCA2 may penetrate the first upper interlayer insulating film 170 and the liner layer 150 in the vertical direction DR3 and be connected to the upper part of the second upper source/drain region USD2. . Additionally, the second upper source/drain contact UCA2 may be connected to the top of the first through via TV1. That is, the second upper source/drain contact UCA2 may electrically connect the second upper source/drain area USD2 and the first through via TV1.

The third upper source/drain contact UCA3 may be disposed between the third gate electrode G3 and the fourth gate electrode G4. The third upper source/drain contact UCA3 may extend in the second horizontal direction DR2. The third upper source/drain contact (UCA3) may penetrate the first upper interlayer insulating film 170 and the liner layer 150 in the vertical direction (DR3) and be connected to the upper part of the third upper source/drain region (USD3). .

The lower silicide layer SL1 is disposed along the boundary between each of the first to third lower source/drain regions BSD1, BSD2, and BSD3 and the first to third lower source/drain contacts BCA1, BCA2, and BCA3. It can be. The upper silicide layer SL2 is disposed along the boundary between each of the first to third upper source/drain regions USD1, USD2, and USD3 and the first to third upper source/drain contacts UCA1, UCA2, and UCA3, respectively. It can be. Each of the lower silicide layer SL1 and the upper silicide layer SL2 may include, for example, a metal silicide material.

The lower connection pad BP may be disposed inside the second gate cut GC2. The lower connection pad BP may be disposed on the lower surface of the third through via TV3 inside the second gate cut GC2. The lower connection pad BP may extend from the lower surface of the third lower interlayer insulating layer 160 in the vertical direction DR3. The lower connection pad BP may be electrically connected to the third through via TV3. For example, the top surface of the lower connection pad BP may be formed on the same plane as the top surface of the first lower source/drain contact BCA1, but the technical idea of the present invention is not limited thereto. For example, the lower surface of the lower connection pad BP may be formed on the same plane as the lower surface of the second gate cut GC2.

The upper connection pad UP may be disposed inside the first gate cut GC1. The upper connection pad UP may be disposed on the top surface of the first through via TV1 inside the first gate cut GC1. The upper connection pad UP may extend from the top surface of the first upper interlayer insulating film 170 to the top surface of the first through via TV1. The upper connection pad UP may be electrically connected to the first through via TV1. For example, the top surface of the upper connection pad UP may be formed on the same plane as the top surface of the first upper source/drain contact UCA1. For example, the lower surface of the upper connection pad UP may be formed on the same plane as the lower surface of the first upper source/drain contact UCA1, but the technical idea of the present invention is not limited thereto.

Each of the lower connection pad BP and upper connection pad UP may include a conductive material. In FIG. 4, each of the lower connection pad BP and upper connection pad UP is shown as being formed of a single layer, but this is for convenience of explanation and the technical idea of the present invention is not limited thereto. That is, each of the lower connection pad BP and upper connection pad UP may be formed of a multilayer.

For example, the gate contact CB may penetrate the capping pattern 133 in the vertical direction DR3 and be connected to the second gate electrode G2. The arrangement of the gate contact CB shown in FIG. 3 is illustrative and the arrangement of the gate contact CB is not limited. The gate contact (CB) may include a conductive material. Although the gate contact CB is shown in FIG. 3 as being formed of a single layer, this is for convenience of explanation and the technical idea of the present invention is not limited thereto. That is, the gate contact (CB) may be formed as a multilayer.

The second upper interlayer insulating film 180 may be disposed on the first upper interlayer insulating film 170. For example, the second upper interlayer insulating film 180 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. For example, the first lower via BV1 may penetrate the first lower interlayer insulating film 100 in the vertical direction DR3 and be connected to the first lower source/drain contact BCA1. The second lower via BV2 may penetrate the first lower interlayer insulating film 100 in the vertical direction DR3 and be connected to the lower connection pad BP. For example, the first upper via UV1 may penetrate the second upper interlayer insulating film 180 in the vertical direction DR3 and be connected to the gate contact CB. The second upper via UV2 may penetrate the second upper interlayer insulating film 180 in the vertical direction DR3 and be connected to the upper connection pad UP. Each of the first lower via (BV1), the second lower via (BV2), the first upper via (UV1), and the second upper via (UV2) may include a conductive material.

In a semiconductor device having a structure in which a plurality of upper nanosheets are stacked on a plurality of lower nanosheets, through vias are disposed to connect each of the lower source/drain contact and the upper source/drain contact, resulting in the cell region Area may increase. A semiconductor device according to some embodiments of the present invention has a structure in which a plurality of upper nanosheets are stacked on a plurality of lower nanosheets, and a through via connecting each of the lower source/drain contact and the upper source/drain contact is of the gate cut. Can be placed inside. For this reason, the semiconductor device according to some embodiments of the present invention does not require a separate area for disposing the through via in the cell area, and thus the integration of the semiconductor device can be improved by reducing the area of the cell area.

Hereinafter, a method of manufacturing a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 1 to 58.

6 to 58 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.

6 and 7, a first separation material layer 20, a first laminated structure 30, a second separation material layer 40, and a second laminated structure 50 are sequentially formed on the substrate 10. can be laminated. The substrate 10 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 10 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the technical spirit of the present invention This is not limited to this.

The first separation material layer 20 may be formed on the substrate 10 . The first stacked structure 30 may include a first sacrificial layer 31 and a first semiconductor layer 32 alternately stacked on the first separation material layer 20 . For example, a first sacrificial layer 31 may be formed on the lowermost and uppermost portions of the first stacked structure 30, respectively. However, the technical idea of the present invention is not limited thereto. In some other embodiments, the first semiconductor layer 32 may be formed on top of the first stacked structure 30.

The second separation material layer 40 may be formed on the first layered structure 30 . The second stacked structure 50 may include a second sacrificial layer 51 and a second semiconductor layer 52 alternately stacked on the second separation material layer 40 . For example, the second sacrificial layer 51 may be formed at the bottom of the second stacked structure 50, and the second semiconductor layer 52 may be formed at the top of the second stacked structure 50. However, the technical idea of the present invention is not limited thereto. In some other embodiments, the second sacrificial layer 51 may also be formed on the top of the second stacked structure 50.

For example, each of the first separation material layer 20 and the second separation material layer 40 may include silicon germanium (SiGe). For example, each of the first sacrificial layer 31 and the second sacrificial layer 51 may include silicon germanium (SiGe). For example, the concentration of germanium (Ge) contained in each of the first separation material layer 20 and the second separation material layer 40 is included in each of the first sacrificial layer 31 and the second sacrificial layer 51. It may be greater than the concentration of germanium (Ge). For example, each of the first semiconductor layer 32 and the second semiconductor layer 52 may include silicon (Si).

Subsequently, the second laminated structure 50, the second separation material layer 40, the first laminated structure 30, the first separation material layer 20, and a portion of the substrate 10 are etched to form a surface on the substrate 10. An active pattern 11 may be formed in . The active pattern 11 may extend in the first horizontal direction DR1. Subsequently, a field insulating film 15 surrounding the sidewall of the active pattern 11 may be formed on the substrate 10 . For example, the active pattern 11 may protrude from the top surface of the field insulating layer 15 in the vertical direction DR3. Subsequently, a pad oxide film 60 is formed to cover each of the field insulating film 15, the first separation material layer 20, the first stacked structure 30, the second isolation material layer 40, and the second stacked structure 50. This can be formed. For example, the pad oxide film 60 may be formed conformally. The pad oxide film 60 may include, for example, silicon oxide (SiO ₂ ).

8 to 10, first to fourth dummy gates DG1, DG2, DG3, and DG4 extend in the second horizontal direction DR2 on the field insulating film 15 and the second stacked structure 50. can be formed. The first to fourth dummy gates DG1, DG2, DG3, and DG4 may be sequentially spaced apart in the first horizontal direction DR1. Additionally, first to fourth dummy capping patterns DC1, DC2, DC3, and DC4 may be formed on each of the first to fourth dummy gates DG1, DG2, DG3, and DG4. For example, the remaining portion of the pad oxide film 60 except for the portion that overlaps each of the first to fourth dummy gates DG1, DG2, DG3, and DG4 in the vertical direction DR3 may be removed.

Referring to FIGS. 11 to 13 , each of the first separation material layer (20 in FIGS. 8 to 10 ) and the second separation material layer (40 in FIGS. 8 to 10 ) may be etched. For example, each of the first separation material layer (20 in FIGS. 8 to 10 ) and the second separation material layer (40 in FIGS. 8 to 10 ) may be etched by a wet etching process.

14 to 16, the sidewalls of each of the first to fourth dummy gates DG1, DG2, DG3, and DG4, the sidewalls of each of the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4, and A spacer material layer SM may be formed to cover the top surface of the first stacked structure 30, the second stacked structure 50, and the field insulating film 15. The spacer material layer SM may fill the etched portions of the first separation material layer (20 in FIGS. 8 to 10) and the second separation material layer (40 in FIGS. 8 to 10). For example, the spacer material layer SM may be formed conformally. The spacer material layer (SM) may be, for example, silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and combinations thereof. It can contain at least one.

17 and 18, the first to fourth dummy capping patterns (DC1, DC2, DC3, and DC4) and the first to fourth dummy gates (DG1, DG2, DG3, and DG4) are used as masks to form the first capping pattern (DC1, DC2, DC3, and DC4). The stacked structure (30 in FIGS. 14 to 16), the second stacked structure (50 in FIGS. 14 to 16), and the spacer material layer (SM in FIGS. 14 to 16) are etched to form first to third source/drain trenches. (ST1, ST2, ST3) can be formed. For example, each of the first to third source/drain trenches ST1, ST2, and ST3 may extend into the inside of the substrate 10.

For example, the first source/drain trench ST1 may be formed between the first dummy gate DG1 and the second dummy gate DG2 on the substrate 10 . The second source/drain trench ST2 may be formed between the second dummy gate DG2 and the third dummy gate DG3 on the substrate 10 . The third source/drain trench ST3 may be formed between the third dummy gate DG3 and the fourth dummy gate DG4 on the substrate 10 .

While each of the first to third source/drain trenches (ST1, ST2, ST3) is formed, a spacer material layer (FIG. A portion of each of the SM of FIGS. 14 to 16 and the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4 may be etched. The spacer material layer remaining on the sidewalls of each of the first to fourth dummy gates (DG1, DG2, DG3, and DG4) and the remaining first to fourth dummy capping patterns (DC1, DC2, DC3, and DC4) (FIGS. 14 to 14). SM in FIG. 16 may be defined as a gate spacer 131.

For example, after each of the first to third source/drain trenches (ST1, ST2, and ST3) is formed, the first semiconductor remaining under each of the first to fourth dummy gates (DG1, DG2, DG3, and DG4) The layer (32 in FIGS. 14 to 16) may be defined as the first to fourth plurality of lower nanosheets BNW1, BNW2, BNW3, and BNW4, respectively. In addition, after each of the first to third source/drain trenches (ST1, ST2, and ST3) is formed, the second semiconductor layer remaining below each of the first to fourth dummy gates (DG1, DG2, DG3, and DG4) 14 to 16) may be defined as the first to fourth plurality of upper nanosheets UNW1, UNW2, UNW3, and UNW4, respectively.

For example, after each of the first to third source/drain trenches (ST1, ST2, and ST3) is formed, the active pattern 11 and the first to fourth plurality of lower nanosheets (BNW1, BNW2, BNW3, and BNW4) are formed. The spacer material layer remaining between each (SM in FIGS. 14 to 16) may be defined as the lower separation layer 110. In addition, after each of the first to third source/drain trenches (ST1, ST2, ST3) is formed, each of the first to fourth plurality of lower nanosheets (BNW1, BNW2, BNW3, BNW4) and the first to fourth plurality of nanosheets (BNW1, BNW2, BNW3, BNW4) are formed. The spacer material layer (SM in FIGS. 14 to 16 ) remaining between each of the upper nanosheets (UNW1, UNW2, UNW3, and UNW4) may be defined as the upper separation layer 120.

19 and 20, first to third sacrificial epi layers (SE1, SE2, SE3) and first to third sacrificial epi layers (SE1, SE2, SE3) inside each of the first to third source/drain trenches (ST1, ST2, ST3). Lower source/drain regions (BSD1, BSD2, BSD3) may be formed.

For example, each of the first to third sacrificial epitaxial layers (SE1, SE2, and SE3) may be formed between the active patterns 11 inside each of the first to third source/drain trenches (ST1, ST2, and ST3). You can. For example, each of the first to third sacrificial epitaxial layers SE1, SE2, and SE3 may be formed by epitaxially growing from the substrate 10 and the active pattern 11.

For example, the first lower source/drain region BSD1 is formed between the first plurality of lower nanosheets BNW1 and the second plurality of lower nanosheets BNW2 inside the first source/drain trench ST1. can be formed. A second lower source/drain region (BSD2) may be formed between the second plurality of lower nanosheets (BNW2) and the third plurality of lower nanosheets (BNW3) inside the second source/drain trench (ST2). . A third lower source/drain region (BSD3) may be formed between the third plurality of lower nanosheets (BNW3) and the fourth plurality of lower nanosheets (BNW4) inside the third source/drain trench (ST3). . For example, each of the first to third lower source/drain regions (BSD1, BSD2, and BSD3) may be formed by epitaxially growing from each of the first to fourth plurality of lower nanosheets (BNW1, BNW2, BNW3, and BNW4). You can.

21 and 22, a field insulating layer 15, first to third sacrificial epitaxial layers (SE1, SE2, SE3), lower separation layer 110, upper separation layer 120, first to third sacrificial epitaxial layers (SE1, SE2, SE3). Lower source/drain regions (BSD1, BSD2, BSD3), first to third upper source/drain regions (USD1, USD2, USD3), first and second sacrificial layers (31, 51), gate spacer (131), A liner layer 150 may be formed along the exposed surfaces of each of the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4. Subsequently, a third lower interlayer insulating film 160 may be formed on the liner layer 150. For example, the top surface of the third lower interlayer insulating film 160 may be formed to be higher than the top surface of each of the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4.

Referring to FIGS. 23 and 24 , a portion of each of the third lower interlayer insulating film 160 and the liner layer 150 may be etched. For example, after this etching process is performed, the top surface of each of the third lower interlayer insulating film 160 and the liner layer 150 is aligned with the top surface of the upper separation layer 120 and the first plurality of upper nanosheets UNW1. It can be formed between the bottom surfaces of the lowest nanosheets.

Referring to FIGS. 25 and 26 , a first upper source/drain region USD1 may be formed between the first plurality of upper nanosheets UNW1 and the second plurality of upper nanosheets UNW2. A second upper source/drain region USD2 may be formed between the second plurality of upper nanosheets UNW2 and the third plurality of upper nanosheets UNW3. A third upper source/drain region USD3 may be formed between the third plurality of upper nanosheets UNW3 and the fourth plurality of upper nanosheets UNW4. For example, each of the first to third upper source/drain regions (USD1, USD2, and USD3) may be formed by epitaxially growing from each of the first to fourth plurality of upper nanosheets (UNW1, UNW2, UNW3, and UNW4). You can.

Subsequently, the third lower interlayer insulating film 160, first to third upper source/drain regions (USD1, USD2, USD3), second sacrificial layer 51, gate spacer 131, and first to fourth dummy capping. A liner layer 150 may be formed along the exposed surfaces of each of the patterns DC1, DC2, DC3, and DC4. Subsequently, the first upper interlayer insulating film 170 may be formed on the liner layer 150. For example, the top surface of the first upper interlayer insulating film 170 may be formed to be higher than the top surfaces of each of the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4.

Referring to FIGS. 27 and 28 , the top surfaces of each of the first to fourth dummy gates DG1, DG2, DG3, and DG4 may be exposed through a planarization process.

Referring to FIGS. 29 and 30 , first to fourth dummy gates (DG1, DG2, DG3, DG4), pad oxide film (60 in FIG. 27), first sacrificial layer (31 in FIG. 27), and second sacrificial layer. (51 in FIG. 27) can each be etched. For example, the etched portions of the first to fourth dummy gates DG1, DG2, DG3, and DG4 may be defined as first to fourth gate trenches GT1, GT2, GT3, and GT4.

Referring to FIGS. 31 and 32 , a gate insulating layer 132, a first gate electrode (G1), and a capping pattern 133 may be sequentially formed inside the first gate trench (GT1). A gate insulating layer 132, a second gate electrode G2, and a capping pattern 133 may be sequentially formed inside the second gate trench GT2. A gate insulating layer 132, a third gate electrode G3, and a capping pattern 133 may be sequentially formed inside the third gate trench GT3. A gate insulating layer 132, a fourth gate electrode G4, and a capping pattern 133 may be sequentially formed inside the fourth gate trench GT4.

33 and 34, the capping pattern 133, the first to fourth gate electrodes (G1, G2, G3, G4), the first upper interlayer insulating film 170, the liner layer 150, and the third lower A first gate cut trench (GCT1) and a second gate cut trench (GCT2) may be formed that penetrate each of the interlayer insulating layers 160 in the vertical direction (DR3). Each of the first gate cut trench (GCT1) and the second gate cut trench (GCT2) may extend in the first horizontal direction (DR1). For example, each of the first gate cut trench (GCT1) and the second gate cut trench (GCT2) may extend into the interior of the field insulating layer 15. The second gate cut trench (GCT2) may be spaced apart from the first gate cut trench (GCT1) in the second horizontal direction (DR2).

For example, the lower separation layer 110, the first to fourth plurality of lower nanosheets (BNW1, BNW2, BNW3, BNW4), the upper separation layer 120, the first to fourth plurality of upper nanosheets (UNW1) , UNW2, UNW3, and UNW4) may each be located between the first gate cut trench (GCT1) and the second gate cut trench (GCT2). For example, by the first gate cut trench (GCT1) and the second gate cut trench (GCT2), the second gate electrode (G2) is connected to the sixth gate electrode (G6), the second gate electrode (G2), and the tenth gate. It can be separated by the electrode G10.

Subsequently, a first gate cut GC1 may be formed along the sidewalls and bottom surfaces of the first gate cut trench GCT1. Additionally, a second gate cut GC2 may be formed along the sidewalls and bottom of the second gate cut trench GCT2. For example, each of the first gate cut GC1 and the second gate cut GC2 may be formed conformally, but the technical idea of the present invention is not limited thereto.

Referring to FIGS. 35 and 36 , a first through via TV1 may be formed inside the first gate cut trench GCT1 and on the first gate cut GC1. Additionally, a third through via TV3 may be formed inside the second gate cut trench GCT2 on the second gate cut GC2. For example, each of the first through via TV1 and the third through via TV3 may extend in the first horizontal direction DR1. For example, the top surface of each of the first through via TV1 and the third through via TV3 may be formed to be lower than the top surface of the second gate electrode G2.

Referring to FIGS. 37 and 38 , a first gate cut GC1 may be additionally formed on the top surface of the first through via TV1 to fill the remaining portion of the interior of the first gate cut trench GCT1. Additionally, a second gate cut GC2 may be additionally formed on the upper surface of the third through via TV3 to fill the remaining portion of the second gate cut trench GCT2. For example, the top surface of each of the first gate cut GC1 and the second gate cut GC2 may be formed on the same plane as the top surface of the first upper interlayer insulating layer 170.

Referring to FIGS. 39 to 42 , first to third upper source/drain contacts (UCA1, UCA2, UCA3) and upper silicide layer (SL2) may be formed. For example, the first upper source/drain contact (UCA1) may connect the first upper source/drain region (USD1) and the third through via (TV3). The second upper source/drain contact (UCA2) may connect the second upper source/drain area (USD2) and the first through via (TV1). The upper silicide layer SL2 is formed along the interface between each of the first to third upper source/drain regions USD1, USD2, and USD3 and each of the first to third upper source/drain contacts UCA1, UCA2, and UCA3. It can be.

Additionally, an upper connection pad UP may be formed on the first through via TV1 inside the first gate cut trench GCT1. For example, the first upper source/drain contact UCA1 may be spaced apart from the upper connection pad UP in the second horizontal direction DR2. Additionally, for example, a gate contact CB connected to the second gate electrode G2 may be formed by penetrating the capping pattern 133 in the vertical direction DR3.

Subsequently, a second upper interlayer insulating film 180 may be formed on the first upper interlayer insulating film 170. Subsequently, the first upper via UV1 may be formed through the second upper interlayer insulating film 180 in the vertical direction DR3 and connected to the gate contact CB. Additionally, a second upper via UV2 may be formed that penetrates the second upper interlayer insulating film 180 in the vertical direction DR3 and is connected to the upper connection pad UP.

Referring to FIGS. 43 to 46 , after the manufacturing process shown in FIGS. 39 to 42 is performed, the top and bottom may be reversed. The substrate (10 in FIGS. 39 to 42) and the active pattern (11 in FIGS. 39 to 42) can be removed in the upside-down state. As a result, each of the lower separation layer 110, the first to third sacrificial epitaxial layers (SE1, SE2, and SE3), and the field insulating layer 15 may be exposed.

Referring to FIGS. 47 to 50, a sacrificial pattern (SP) is formed to surround the sidewalls of each of the first to third sacrificial epitaxial layers (SE1, SE2, and SE3 in FIGS. 43 to 46) on the lower separation layer 110. It can be. The sacrificial pattern SP may include, for example, silicon nitride (SiN). Subsequently, the first to third sacrificial epi layers (SE1, SE2, and SE3 in FIGS. 43 to 46) may be removed.

Referring to FIGS. 51 to 54 , a second lower interlayer insulating layer 140 may be formed on the sacrificial pattern SP and the field insulating layer 15. The second lower interlayer insulating film 140 may fill the portion where the first to third sacrificial epitaxial layers (SE1, SE2, and SE3 in FIGS. 43 to 46) were removed. Subsequently, first to third lower source/drain contacts (BCA1, BCA2, BCA3) and lower silicide layer (SL1) may be formed.

For example, the first lower source/drain contact BCA1 may be connected to the first lower source/drain region BSD1. The second lower source/drain contact BCA2 may connect the second lower source/drain area BSD2 and the first through via TV1. The third lower source/drain contact BCA3 may be connected to the third lower source/drain region BSD3. The fourth lower source/drain contact (BCA4) may be connected to the first through via (TV1). The lower silicide layer SL1 is formed along the interface between each of the first to third lower source/drain regions (BSD1, BSD2, BSD3) and each of the first to third lower source/drain contacts (BCA1, BCA2, BCA3). It can be. Additionally, a lower connection pad BP may be formed on the second through via TV2 inside the second gate cut trench GCT2. For example, the lower connection pad BP may be spaced apart from the first lower source/drain contact BCA1 in the second horizontal direction DR2.

Referring to FIGS. 55 to 58 , the lower separation layer 110 may be exposed through a planarization process. For example, the sacrificial pattern SP and the field insulating layer 15 may be removed through a planarization process. For example, through the planarization process, the second gate electrode (G2), the first gate cut (GC1), the second gate cut (GC2), the first through via (TV1), the third through via (TV3), and the 3 Each of the lower interlayer insulating films 160 may be exposed.

1 to 5, a lower separation layer 110, a second lower interlayer insulating film 140, first to fourth lower source/drain contacts (BCA1, BCA2, BCA3, BCA4), and a lower connection pad (BP). ), the first lower interlayer insulating film ( 100) can be formed.

Subsequently, the first lower via BV1 may be formed through the first lower interlayer insulating film 100 in the vertical direction DR3 and connected to the first lower source/drain contact BCA1. Additionally, a second lower via BV2 may be formed that penetrates the first lower interlayer insulating film 100 in the vertical direction DR3 and is connected to the lower connection pad BP. After these manufacturing processes are performed, the semiconductor devices shown in FIGS. 1 to 5 can be manufactured by inverting the top and bottom.

Hereinafter, a semiconductor device according to several other embodiments of the present invention will be described with reference to FIG. 59. The description will focus on differences from the semiconductor devices shown in FIGS. 1 to 5.

Figure 59 is a layout diagram for explaining a semiconductor device according to some other embodiments of the present invention.

Referring to FIG. 59, in a semiconductor device according to some other embodiments of the present invention, the first through via (TV21) is electrically connected to each of the second upper source/drain contact (UCA2) and the third upper source/drain contact (UCA3). It can be connected to .

For example, the first through via TV21 may overlap each of the first to fourth gate electrodes G1, G2, G3, and G4 in the second horizontal direction DR2. The second upper source/drain contact (UCA2) may electrically connect the second upper source/drain region (USD2 in FIG. 2) and the first through via (TV21). Additionally, the third upper source/drain contact (UCA3) may electrically connect the third upper source/drain region (USD3 in FIG. 2) and the first through via (TV21).

Hereinafter, a semiconductor device according to some other embodiments of the present invention will be described with reference to FIG. 60. The description will focus on differences from the semiconductor devices shown in FIGS. 1 to 5.

Figure 60 is a layout diagram for explaining a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 60, a semiconductor device according to another embodiment of the present invention includes two through vias TV33 and TV34 spaced apart from each other in the first horizontal direction DR1 inside the second gate cut GC2. can be placed.

For example, the third through via TV33 may extend in the first horizontal direction DR1 within the second gate cut GC2. The third through via TV33 may overlap the first gate electrode G1 in the second horizontal direction DR2. The third through via TV33 does not overlap each of the second gate electrode G2, third gate electrode G3, and fourth gate electrode G4 in the second horizontal direction DR2.

For example, the fourth through via TV34 may extend in the first horizontal direction DR1 within the second gate cut GC2. The fourth through via TV34 may be spaced apart from the third through via TV33 in the first horizontal direction DR1. The fourth through via TV34 may overlap each of the third and fourth gate electrodes G3 and G4 in the second horizontal direction DR2. The fourth through via TV34 does not overlap each of the first and second gate electrodes G1 and G2 in the second horizontal direction DR2. A second gate cut (GC2) may be disposed between the third through via (TV33) and the fourth through via (TV34).

Hereinafter, a semiconductor device according to some other embodiments of the present invention will be described with reference to FIG. 61. The description will focus on differences from the semiconductor devices shown in FIGS. 1 to 5.

Figure 61 is a cross-sectional view for explaining a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 61, in a semiconductor device according to another embodiment of the present invention, the top surfaces of each of the first through via (TV1), the second through via (TV2 in FIG. 1), and the third through via (TV43) are uppermost. The source/drain contacts (UCA1, UCA2, and UCA3) may be formed higher than the lower surface of each.

For example, the top surface TV43a of the third through via TV43 may be formed to be higher than the bottom surface of the second upper source/drain contact UCA2. For example, at least a portion of the second gate cut GC2 may be disposed on the top surface TV43a of the third through via TV43.

Below, a semiconductor device according to some other embodiments of the present invention will be described with reference to FIG. 62. The description will focus on differences from the semiconductor devices shown in FIGS. 1 to 5.

Figure 62 is a cross-sectional view for explaining a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 62, in a semiconductor device according to another embodiment of the present invention, a gate insulating film 532 may be disposed between the gate cuts GC1 and GC2 and the gate electrodes (G1 to G12 in FIG. 1). .

For example, the gate insulating layer 532 may be disposed between the second gate electrode G2 and the first gate cut GC1. The gate insulating layer 532 may be disposed between the second gate electrode (G2) and the second gate cut (GC2). The gate insulating layer 532 may be disposed between the sixth gate electrode G6 and the first gate cut GC1. The gate insulating layer 532 may be disposed between the tenth gate electrode (G10) and the second gate cut (GC2).

Although embodiments according to the technical idea of the present invention have been described with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, which are commonly known in the technical field to which the present invention pertains. Those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: first lower interlayer insulating film 110: lower separation layer
BNW1 to BNW4: first to fourth plurality of lower nanosheets
UNW1 to UNW4: first to fourth plurality of upper nanosheets
120: upper separation layer 131: gate spacer
132: gate insulating film 133: capping pattern
G1 to G12: first to twelfth gate electrodes
BDS1 to BSD3: first to third lower source/drain regions
UDS1 to USD3: first to third upper source/drain regions
BCA1 to BCA4: first to fourth lower source/drain contacts
UCA1 to UCA3: first to fourth upper source/drain contacts
SL1: Lower silicide layer SL2: Upper silicide layer
140: second lower interlayer insulating film 150: liner layer
160: third lower interlayer insulating film 170: first upper interlayer insulating film
180: second upper interlayer insulating film CB: gate contact
GC1: 1st gate cut GC2: 2nd gate cut
TV1 to TV3: first to third through vias
BP: Lower connection pad UP: Upper connection pad
BV1, BV2: first and second bottom vias
UV1, UV2: first and second top vias

Claims (10)

a first plurality of lower nanosheets stacked and spaced apart from each other in a vertical direction;
an upper separation layer disposed on the first plurality of lower nanosheets;
a first plurality of upper nanosheets stacked on the upper separation layer and spaced apart from each other in the vertical direction;
a first upper source/drain region disposed on a first side of the first plurality of upper nanosheets in a first horizontal direction;
a second upper source/drain region disposed on a second side of the first plurality of upper nanosheets opposite to the first side of the first plurality of upper nanosheets in the first horizontal direction;
a first gate electrode extending in a second horizontal direction different from the first horizontal direction and surrounding each of the first plurality of lower nanosheets, the upper separation layer, and the first plurality of upper nanosheets;
A first gate extending in the first horizontal direction from the first side of the second horizontal direction of the first gate electrode and extending in the vertical direction from the lower surface of the first gate electrode to the upper surface of the first gate electrode. cut;
a first through via extending in the first horizontal direction within the first gate cut and insulated from the first gate electrode;
a first upper source/drain contact extending in the second horizontal direction on the first upper source/drain region and electrically connected to the first upper source/drain region; and
A semiconductor device comprising a second upper source/drain contact extending in the second horizontal direction on the second upper source/drain region and electrically connecting the second upper source/drain region and the first through via. According to clause 1,
extending in the first horizontal direction from a second side of the first gate electrode opposite to the first side of the first gate electrode in the second horizontal direction, and extending from a lower surface of the first gate electrode to the first gate. a second gate cut extending in the vertical direction to the top surface of the electrode; and
The semiconductor device further includes a second through via extending in the first horizontal direction within the second gate cut, insulated from the first gate electrode, and electrically connected to the first upper source/drain contact. According to clause 2,
An upper connection pad disposed on the upper surface of the first through via within the first gate cut, electrically connected to the first through via, and having an upper surface formed on the same plane as the upper surface of the first gate cut. ; and
A lower connection pad disposed on the lower surface of the second through via within the second gate cut, electrically connected to the second through via, and having an upper surface formed on the same plane as the lower surface of the second gate cut. A semiconductor device further comprising: According to clause 1,
A semiconductor device wherein a top surface of the first through via is formed lower than a top surface of the first gate electrode. According to clause 1,
a first lower source/drain region disposed on a first side of the first plurality of lower nanosheets in a first horizontal direction;
a second lower source/drain region disposed on a second side of the first plurality of lower nanosheets opposite to the first side of the first plurality of lower nanosheets in the first horizontal direction;
a first lower source/drain contact disposed below the first lower source/drain region and electrically connected to the first lower source/drain region; and
The semiconductor device further includes a second lower source/drain contact disposed below the second lower source/drain region and electrically connecting the second lower source/drain region and the first through via. According to clause 1,
a second plurality of lower nanosheets stacked with the first plurality of lower nanosheets spaced apart from each other in the first horizontal direction and spaced apart from each other in the vertical direction;
a second plurality of upper nanosheets stacked on the second plurality of lower nanosheets, spaced apart from each other in the vertical direction, and a first side of which is in contact with the second upper source/drain region;
a third upper source/drain region disposed on a second side of the second plurality of upper nanosheets opposite to the first side of the second plurality of upper nanosheets in the first horizontal direction; and
A semiconductor device further comprising a second gate electrode extending in the second horizontal direction and surrounding each of the second plurality of lower nanosheets and the second plurality of upper nanosheets. According to clause 6,
The semiconductor device further includes a third through via extending in the first horizontal direction within the first gate cut, spaced apart from the first through via in the first horizontal direction, and insulated from the second gate electrode. . A plurality of lower nanosheets stacked and spaced apart from each other in the vertical direction;
an upper separation layer disposed on the plurality of lower nanosheets;
a plurality of upper nanosheets stacked and spaced apart from each other in the vertical direction on the upper separation layer;
a first gate cut extending in a first horizontal direction;
a second gate cut extending in the first horizontal direction and spaced apart from the first gate cut in a second horizontal direction different from the first horizontal direction;
a first gate electrode extending in the second horizontal direction between the first gate cut and the second gate cut, and surrounding each of the plurality of lower nanosheets, the upper separation layer, and the plurality of upper nanosheets;
a second gate electrode extending in the second horizontal direction and separated from the first gate electrode by the first gate cut;
a third gate electrode extending in the second horizontal direction and separated from the first gate electrode by the second gate cut;
a first lower source/drain region disposed on a first side of the plurality of lower nanosheets in the first horizontal direction;
a first upper source/drain region disposed on the first lower source/drain region on a first side of the plurality of upper nanosheets in the first horizontal direction;
a first through via extending in the first horizontal direction within the first gate cut and insulated from each of the first and second gate electrodes;
a second through via extending in the first horizontal direction within the second gate cut and insulated from each of the first and third gate electrodes;
a first upper source/drain contact extending in the second horizontal direction on the first upper source/drain region and electrically connecting the first upper source/drain region and the second through via; and
A semiconductor device comprising a first lower source/drain contact disposed below the first lower source/drain region and electrically connected to the first lower source/drain region. According to clause 8,
At least a portion of the first gate cut is disposed on a top surface of the first through via. According to clause 8,
A lower separation layer disposed below the plurality of lower nanosheets, the sidewall and upper surface of which are surrounded by the first gate electrode, and the lower surface of which is formed on the same plane as the lowermost surface of each of the first and second through vias. A semiconductor device further comprising:

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