KR20240049521A - Semiconductor device - Google Patents

Abstract

The present disclosure relates to semiconductor devices, and more specifically, to semiconductor devices with improved structures and processes.
A semiconductor device according to an embodiment includes a chip area and an outer area located outside the chip area. At this time, the semiconductor device includes a gate stacked structure located in the chip area and including a plurality of cell insulating layers and a plurality of gate electrodes alternately stacked, a channel structure extending through the gate stacked structure in the chip area, and an outer region. It is located in and includes a key pattern including at least one pattern portion. The pattern portion includes an insulating structure including a base portion and a protrusion protruding from the base portion, and a penetrating portion penetrating the insulating structure on at least one side of the protrusion.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present disclosure relates to semiconductor devices, and more specifically, to semiconductor devices with improved structures and processes.

In electronic systems that require data storage, semiconductor devices capable of storing high-capacity data are required. Accordingly, ways to increase the data storage capacity of semiconductor devices are being studied. For example, as one of the methods to increase the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of memory cells arranged two-dimensionally has been proposed.

Embodiments seek to provide a semiconductor device that can improve performance and productivity.

A semiconductor device according to an embodiment includes a chip area and an outer area located outside the chip area. At this time, the semiconductor device includes a gate stacked structure located in the chip area and including a plurality of cell insulating layers and a plurality of gate electrodes alternately stacked, a channel structure extending through the gate stacked structure in the chip area, and an outer region. It is located in and includes a key pattern including at least one pattern portion. The pattern portion includes an insulating structure including a base portion and a protrusion protruding from the base portion, and a penetrating portion penetrating the insulating structure on at least one side of the protrusion.

According to the embodiment, the pattern portion included in the key pattern includes a plurality of steps, so that sufficient information can be obtained during alignment. At this time, even when the penetrating sacrificial layer is removed in the process of removing the photoresist pattern, the pattern portion of the key pattern can be formed with an easy process. Accordingly, a penetrating sacrificial layer can be formed using a sacrificial material that can overcome process limitations. As a result, the performance and productivity of semiconductor devices can be improved.

1 is a plan view schematically showing a semiconductor device according to an embodiment.
Figure 2 is an enlarged plan view of portion A of Figure 1.
FIG. 3 is a partial cross-sectional view schematically showing part of the semiconductor device shown in FIG. 1.
FIG. 4 is a partial cross-sectional view illustrating an example of a channel structure included in the semiconductor device shown in FIG. 3.
FIG. 5 is a plan view schematically showing a pattern portion of a key pattern included in the semiconductor device shown in FIG. 1.
Figure 6 is a cross-sectional view taken along line B-B' in Figure 5.
FIG. 7 is a cross-sectional view taken along line C-C' of FIG. 5.
8 to 17 are diagrams illustrating a method of manufacturing a pattern portion and a semiconductor device including the same according to an embodiment.
18 is a partial cross-sectional view showing part of a semiconductor device according to another embodiment.
Figure 19 is a partial cross-sectional view schematically showing a part of a semiconductor device according to another embodiment.
Figure 20 is a cross-sectional view schematically showing a semiconductor device according to an additional embodiment.
Figure 21 is a diagram schematically showing an electronic system including a semiconductor device according to an example embodiment.
Figure 22 is a perspective view schematically showing an electronic system including a semiconductor device according to an example embodiment.
23 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment.
24 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment.

Hereinafter, with reference to the attached drawings, various embodiments will be described in detail so that those skilled in the art can easily implement them. Embodiments may be implemented in various forms and are not limited to the embodiments described herein.

In order to clearly explain the present disclosure, parts that are not related to the description have been omitted, and identical or similar elements are denoted by the same reference numerals throughout the specification.

In addition, the size and thickness of each component shown in the drawings are arbitrarily drawn for convenience of explanation, and the present disclosure is not limited to the drawings. For convenience of explanation and/or simple illustration, the thickness of some layers and areas were enlarged or exaggerated.

Additionally, when a part of a layer, membrane, region, plate, etc. is said to be “on” or “on” another part, this includes not only cases where it is “directly above” another part, but also cases where there is another part in between. . Conversely, when a part is said to be “right on top” of another part, it means that there is no other part in between. In addition, being “on” or “on” a reference part means being located above or below the reference part, and does not necessarily mean being located “above” or “on” the direction opposite to gravity. .

In addition, throughout the specification, when a part is said to "include" a certain component, this means that it may further include other components rather than excluding other components, unless specifically stated to the contrary.

In addition, throughout the specification, "on a plane" or "when viewed in plan" means when the object part is viewed from above, and "in cross section" or "when viewed in cross section" means when a cross section cut vertically through the object part is viewed from the side. It can mean time.

Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment will be described in detail with reference to FIGS. 1 to 17.

FIG. 1 is a plan view schematically showing a semiconductor device 10 according to an embodiment, and FIG. 2 is an enlarged plan view of portion A of FIG. 1 . For clear understanding, the position of the protrusion (reference numeral 316 in FIG. 5, hereinafter the same) of the pattern portion 310 included in the key pattern 300 is shown with a dotted line in the portion excluding the enlarged view in FIG. 2. The protruding portion 316 and the penetrating portion 318 are shown as dotted lines.

Referring to FIGS. 1 and 2 , the semiconductor device 10 according to the embodiment may include a chip area CA and an outer area DA located outside the chip area CA.

The chip area (CA) may refer to an area where a memory cell structure, a wiring unit for operating the memory cell structure, and peripheral circuit structures are located. In the chip area (CA). A cell array area where the memory cell structure is located (reference numeral 102 in FIG. 3, hereinafter the same) and a connection area (reference numeral 104 in FIG. 3) that electrically connects the cell array area 102 to the surrounding circuit structure, etc. are located. You can.

The outer area DA may refer to an area set to include a portion to be scribed or cut when dividing into a separate chip area CA. The outer area DA may also be referred to as an external area, scribe lane, scribe line, cut area, divided area, etc.

In an embodiment, a key pattern 300 for alignment or alignment may be located in the outer area DA. The key pattern 300 includes an align key 300a for alignment with the mask used in the manufacturing process, and an overlay key for checking the alignment of the layer formed in the previous process and the layer formed in the current process ( may include an overlay key (300b), etc. The alignment key may be referred to as an alignment mark, an alignment pattern, etc., and the overlay key may be referred to as an overlay mark, an overlay pattern, etc.

The key pattern 300 may include at least one pattern portion 310 having a stepped edge to check alignment. The pattern portion 310 will be described in more detail later with reference to FIGS. 5 to 7 .

In addition, a measurement pattern, a test element group (TEG), etc. may be located in the outer area (DA). The measurement pattern is a pattern for checking the thickness, critical dimension, and shape of each layer, and may include, for example, an optical pattern (eg, an optical critical dimension (OCD) pattern). A test element group may be a pattern for checking performance during the manufacturing process or after completion of manufacturing. However, the type of pattern formed in the outer area DA is not limited to the above. Therefore, the outer area (DA) can be equipped with various patterns that perform various roles.

For clear understanding, FIG. 1 illustrates that the semiconductor device 10 includes a plurality of chip areas (CA) and an outer area (DA). After division, the semiconductor device 10 may include a chip area CA and an outer area DA located outside the chip area CA on at least one side of the chip area CA. In Figure 1, the number, arrangement, and shape of the key pattern 300, the align key 300a, or the overlay key 300b are shown as examples, and the key pattern 300, the align key 300a, or the overlay key 300b are shown as examples. The number, arrangement, and shape of the keys 300b may be varied in various ways.

The semiconductor device 10 according to the embodiment will be described in more detail with reference to FIGS. 3 and 4 along with FIGS. 1 and 2 .

FIG. 3 is a partial cross-sectional view schematically showing part of the semiconductor device 10 shown in FIG. 1. FIG. 4 is a partial cross-sectional view showing an example of the channel structure CH included in the semiconductor device 10 shown in FIG. 3. For clear understanding, the coordinates in FIG. 3 are mainly displayed on the portion corresponding to the cell area 100, and the circuit elements 220 included in the circuit area 200 are schematically shown.

Referring to FIGS. 1 to 4 , the semiconductor device 10 according to an embodiment includes a cell region 100 in which a memory cell structure is provided and a circuit region in which a peripheral circuit structure that controls the operation of the memory cell structure is provided. It may include (200). As an example, the circuit region 200 and the cell region 100 correspond to the first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 shown in FIG. 21, respectively. This may be the part. Alternatively, the circuit region 200 and the cell region 100 may be parts including the first structure 3100 and the second structure 3200 of the semiconductor chip 2200 shown in FIG. 23, respectively.

In an exemplary embodiment, the cell area 100 may be located on the circuit area 200. According to this, the area corresponding to the circuit area 200 does not need to be secured separately from the cell area 100, so the area of the semiconductor device 10 can be reduced. However, the embodiment is not limited to this, and the circuit area 200 may be located next to the cell area 100. Various other variations are possible.

The circuit area 200 may include a first substrate 210, a circuit element 220 formed on the first substrate 210, and a first wiring portion 230.

The first substrate 210 may be a semiconductor substrate containing a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate made of a semiconductor material, or may be a semiconductor substrate in which a semiconductor layer is formed on a base substrate. As an example, the first substrate 210 may be made of single-crystalline or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). ), etc.

The circuit elements 220 formed on the first substrate 210 may include various circuit elements that control the operation of the memory cell structure provided in the cell region 100. As an example, the circuit element 220 may configure peripheral circuit structures such as a decoder circuit (reference numeral 1110 in FIG. 21), a page buffer (reference numeral 1120 in FIG. 21), and a logic circuit (reference numeral 1130 in FIG. 21). there is.

The circuit element 220 may include, for example, a transistor, but is not limited thereto. For example, the circuit element 220 may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, and inductors.

The first wiring portion 230 located on the first substrate 210 may be electrically connected to the circuit element 220. In an exemplary embodiment, the first wiring portion 230 may include a plurality of wiring layers 236 spaced apart with an insulating layer 232 therebetween and connected to form a desired path by a contact via 234. . The wiring layer 236 or contact via 234 may include various conductive materials, and the insulating layer 232 may include various insulating materials. For example, among the plurality of wiring layers 236, the wiring layer 236 located at the top adjacent to the cell region 100 includes a pad portion to which a gate contact portion 184, a source contact portion 186, an input/output connection wiring, etc. are connected. The pad part can be configured.

The cell area 100 may include a cell array area 102 and a connection area 104. The cell region 100 may include at least a gate stack structure 120 and a channel structure (CH) located in the cell array region 102 as memory cell structures. A structure for connecting the memory cell structure to the circuit area 200 or an external circuit may be located in the cell array area 102 and/or the connection area 104.

In one embodiment, the second substrate 110 may include a semiconductor layer containing a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate made of a semiconductor material, or a semiconductor layer may be formed on a base substrate. For example, the second substrate 110 may be made of silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator. Here, the semiconductor layer included in the second substrate 110 may be doped with p-type impurities such as boron (B) or gallium (Ga) or n-type impurities such as phosphorus (P) or arsenic (As). However, the embodiment is not limited to the material of the second substrate 110, the conductivity type and material of the impurity doped in the semiconductor layer, etc.

The gate stacked structure 120 is located on one surface (eg, the front or top surface) of the second substrate 110 and may include cell insulating layers 132 and gate electrodes 130 stacked alternately with each other. You can. The channel structure CH may extend in a direction that penetrates the gate stack structure 120 and intersects the second substrate 110 . For example, the extension direction of the channel structure CH may be a thickness direction of the semiconductor device 10 or an extension direction (eg, perpendicular to) the second substrate 110 (Z-axis direction in the drawing).

In an exemplary embodiment, the channel structure CH and the second substrate 110 are electrically connected (for example, directly connected) between the second substrate 110 and the gate stack structure 120 in the cell array region 102. It may include horizontal conductive layers 112 and 114. The horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 and/or a second horizontal conductive layer 114 sequentially positioned on the second substrate 110 . The first horizontal conductive layer 112 may function as part of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 may function as a common source line together with the second substrate 110.

The first and second horizontal conductive layers 112 and 114 may include a semiconductor material (eg, polycrystalline silicon). For example, the first horizontal conductive layer 112 may include a polycrystalline silicon layer containing impurities. The embodiment is not limited to this, and the second horizontal conductive layer 114 may be made of a material different from the first horizontal conductive layer 112 (for example, an insulating material) or the second horizontal conductive layer 114 may not be provided. It may be possible.

On the second substrate 110 (for example, on the first and second horizontal conductive layers 112 and 114 formed on the second substrate 110), a cell insulating layer 132 and a gate electrode 130 are alternately formed. A gate stacked structure 120 may be located.

The cell insulating layer 132 may include an interlayer insulating layer 132m located between two adjacent gate electrodes 130. In an embodiment, at least two of the plurality of cell insulating layers 132 may have the same thickness or different thicknesses. For simplicity of illustration, the drawing illustrates that the cell insulating layer 132 and the plurality of gate stacked portions 121 and 122 in the connection area 104 are depicted as one portion without a boundary. However, one or more insulating layers in the connection area 104 may have various stacked structures. The shape and structure of the cell insulating layer 132 may vary depending on the embodiment.

The gate electrode 130 may include various conductive materials. For example, the gate electrode 130 may be made of a metal material such as tungsten (W), copper (Cu), aluminum (Al), polycrystalline silicon, or metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN)). etc.), or a combination thereof. As shown in the enlarged view of FIG. 4, a portion of the blocking layer 156 (eg, the first blocking layer 156a) made of an insulating material may be located outside the gate electrode 130. The cell insulating layer 132 may include various insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon nitride, a low dielectric constant material having a smaller dielectric constant than silicon oxide, or a combination thereof.

The channel structure (CH) may include a channel layer 140 and a gate dielectric layer 150 located on the channel layer 140 between the gate electrode 130 and the channel layer 140. The gate dielectric layer 150 located between the gate electrode 130 and the channel layer 140 includes a tunneling layer 152, a charge storage layer 154, and a blocking layer 156, which are sequentially formed on the channel layer 140. may include.

The channel structure CH may further include a core insulating layer 142 located inside the channel layer 140, but in other examples, the core insulating layer 142 may not be provided. The channel structure CH may further include a channel pad 144 disposed on the channel layer 140 and/or the gate dielectric layer 150. The channel pad 144 may be arranged to cover the upper surface (lower surface in FIG. 2) of the core insulating layer 142 and be electrically connected to the channel layer 140.

Each channel structure (CH) forms one memory cell string, and a plurality of channel structures (CH) may be arranged to be spaced apart from each other in rows and columns on a plane. For example, a plurality of channel structures CH may be arranged in various shapes, such as a grid shape or a zigzag shape, on a plane. The channel structure CH may have a pillar shape. As an example, the channel structure CH may have inclined side surfaces so that the width becomes narrower as it approaches the second substrate 110 depending on the aspect ratio when viewed in cross section. However, the embodiment is not limited to this, and the arrangement, structure, and shape of the channel structure CH may be modified in various ways.

The channel layer 140 may include a semiconductor material, for example, polycrystalline silicon. The core insulating layer 142 may include various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon nitride, or a combination thereof. The channel pad 144 may include a conductive material, for example, polycrystalline or single-crystalline silicon doped with impurities.

The tunneling layer 152 may include an insulating material capable of tunneling charges (eg, silicon oxide, silicon nitoxide, etc.). The charge storage layer 154 is used as a data storage area, and the charge storage layer 154 may include polycrystalline silicon, silicon nitride, etc. The blocking layer 156 may include an insulating material that can prevent unwanted charges from flowing into the gate electrode 130. For example, the blocking layer 156 may include silicon oxide, silicon nitride, silicon nitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In one embodiment, the blocking layer 156 includes a first blocking layer 156a including a portion extending horizontally along the gate electrode 130, and between the first blocking layer 156a and the charge storage layer 154. It may include a second blocking layer 156b extending vertically.

However, the embodiment is not limited to the material or structure of the channel layer 140, core insulating layer 142, channel pad 144, or gate dielectric layer 150.

In an exemplary embodiment, the gate stacked structure 120 may include a plurality of gate stacked portions 121 and 122 sequentially stacked on the second substrate 110 . Then, the number of gate electrodes 130 to be stacked can be increased, thereby increasing the number of memory cells with a stable structure. FIG. 3 illustrates that the gate stacked structure 120 includes first and second gate stacked portions 121 and 122. However, the embodiment is not limited to this, and the gate stacked structure 120 may include one or three or more gate stacked parts.

As described above, when the plurality of gate stacked portions 121 and 122 are provided, the channel structure CH passes through the plurality of gate stacked portions 121 and 122, respectively, and has a plurality of channel portions (CH1, CH2) can be provided. Each of the plurality of channel parts (CH1, CH2) has an inclined side surface so that the width becomes narrower as it approaches the second substrate 110 according to the aspect ratio when viewed in cross section, and a connection part of the plurality of channel parts (CH1, CH2) A bent portion may be provided due to a difference in width. As another example, the plurality of channel portions CH1 and CH2 may have inclined sides that are continuously connected without bends. FIG. 4 illustrates that the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel portions CH1 and CH2 extend from each other to have an integral structure. As another example, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel portions CH1 and CH2 are formed separately from each other and electrically connected to each other, or separate channel pads are formed in a plurality of It may be additionally provided at the connection portion of the channel portions (CH1, CH2). As such, the embodiment is not limited to the form of the plurality of channel portions CH1 and CH2.

In the drawing, it is illustrated that the plurality of channel parts CH1 and CH2 include a first channel part CH1 and a second channel part CH2, but the embodiment is not limited thereto.

In one embodiment, the gate stacked structure 120 extends in the thickness direction of the semiconductor device 10 or in an extension direction (eg, perpendicular to) the second substrate 110 (Z-axis direction in the drawing) to form a gate stack. The structure 120 may be divided into a plurality of sections on a plane by a separation structure 146 penetrating the structure 120 . Additionally, an upper isolation region 148 may be formed on the gate stacked structure 120 . On a plane, the separation structure 146 and/or the upper separation area 148 extends in a first direction (Y-axis direction in the drawing) and is spaced a predetermined distance from each other in a second direction (X-axis direction in the drawing) intersecting therewith. It can be provided in plural numbers so that they are spaced apart.

By the separation structure 146, on a plane, a plurality of gate stacked structures 120 extend in a first direction (Y-axis direction in the drawing) and are separated in a second direction (X-axis direction in the drawing) intersecting the first direction. They may be spaced apart from each other at a predetermined distance. The gate stacked structure 120 partitioned by the separation structure 146 may form one memory cell block. However, the embodiment is not limited to this and the scope of the memory cell block is not limited to this.

For example, the isolation structure 146 may extend through the gate stack structure 120 to the second substrate 110, and the upper isolation region 148 may include only one or a portion of the plurality of gate electrodes 130. can be separated from each other. The upper separation area 148 may be located between the separation structures 146.

As an example, the separation structure 146 is illustrated as having an inclined side surface whose width gradually decreases toward the second substrate 110 when viewed in cross section due to a high aspect ratio, but the embodiment is not limited thereto. A side surface of the separation structure 146 may be perpendicular to the second substrate 110 or may have a bent portion at a connection portion of the plurality of gate stacked portions 121 and 122.

Isolation structure 146 or upper isolation region 148 may be filled with various insulating materials. For example, isolation structure 146 or upper isolation region 148 may include an insulating material such as silicon oxide, silicon nitride, or silicon nitride. However, the embodiment is not limited to this, and the structure, shape, and material of the separation structure 146 or the upper separation region 148 can be modified in various ways.

A connection area 104 and a second wiring unit 180 will be provided to connect the gate stacked structure 120 and the channel structure (CH) provided in the cell array area 102 to the circuit area 200 or an external circuit. You can. The connection area 104 may be arranged around the cell array area 102, and a portion of the second wiring unit 180 may be located there.

In one embodiment, the second wiring unit 180 connects the gate electrode 130, the channel structure (CH), the horizontal conductive layers 112 and 114, and/or the second substrate 110 to the circuit area 200 or the outside. It may include all members that are electrically connected to the circuit. For example, the second wiring unit 180 includes the bit line 182, the gate contact unit 184, the source contact unit 186, the input/output connection wires and the contact vias 180a respectively connected to them, and connecting them. It may include a connection wire 180b.

The bit line 182 extends in a second direction (X-axis direction in the drawing) that intersects the first direction (Y-axis direction in the drawing) in which the gate electrode 130 extends, and forms a channel structure (CH), for example , may be electrically connected to the channel pad 144.

A plurality of gate electrodes 130 may be positioned to extend in a first direction (Y-axis direction in the drawing) in the connection area 104, and the extension length of the plurality of gate electrodes 130 in the connection area 104 may be 2 It may sequentially become smaller as it moves away from the substrate 110. For example, the plurality of gate electrodes 130 may have a step shape in one direction or multiple directions in the connection area 104. In the connection area 104 , a plurality of gate contact portions 184 may be electrically connected to a plurality of gate electrodes 130 extending through the cell insulating layer 132 to the connection area 104 .

A connection wire 180b may be located in the cell array area 102 and/or the connection area 104. The bit line 182, the gate contact unit 184, the source contact unit 186, and/or the input/output connection wire may be electrically connected to the connection wire 180b.

In FIG. 3 , the connection wiring 180b is provided as a single layer located on the same plane as the bit line 182, and a separate insulating layer 134 is located in a portion other than the second wiring portion 180. However, this is only a brief illustration for convenience. Therefore, the connection wiring 180b may include a plurality of wiring layers and a contact via for electrical connection with the bit line 182, the gate contact portion 184, the source contact portion 186, and/or the input/output connection wiring. there is.

In this way, the bit line 182, the gate electrode 130, the horizontal conductive layers 112, 114, and/or connected to the channel structure (CH) by the second wiring portion 180 and the first wiring portion 230. The second substrate 110 may be electrically connected to the circuit element 220 of the circuit area 200.

In FIG. 3, the gate contact portion 184 and/or the source contact portion 186 has an inclined side surface so that the width becomes narrower as it approaches the second substrate 110 according to the aspect ratio when viewed in cross section, and a plurality of gate stacked portions. It is exemplified that a bent portion is provided at the boundary of (121, 122). However, the embodiment is not limited to this. It is also possible that the gate contact part 184, the source contact part 186, and/or the input/output connection wiring do not have a bent part at the boundary between the plurality of gate stacked parts 121 and 122. Various other variations are possible.

In one embodiment, the outer area DA may include a sacrificial laminated structure 120s. The sacrificial stacked structure 120s may include a plurality of sacrificial stacked portions 121s and 122s corresponding to the plurality of gate stacked portions 121 and 122 . FIG. 3 illustrates that the sacrificial laminated structure 120s includes first and second sacrificial laminated portions 121s and 122s. However, the embodiment is not limited thereto, and the sacrificial stacked structure 120s may include one, three or more gate stacked portions.

The sacrificial stacked structure 120s may include a plurality of cell insulating layers 132 (eg, interlayer insulating layers 132m) and a plurality of sacrificial insulating layers 130s that are alternately stacked with each other. The sacrificial insulating layer 130s may include a material different from the cell insulating layer 132 (eg, the interlayer insulating layer 132m). For example, the sacrificial insulating layer 130s includes silicon, silicon oxide, silicon carbide, silicon nitride, etc. and may be made of a material different from the cell insulating layer 132.

The plurality of interlayer insulating layers 132m of the gate stacked structure 120 and the plurality of interlayer insulating layers 132m of the sacrificial stacked structure 120s may be insulating layers formed in the same process. After forming the sacrificial stacked structure 120s by alternately stacking a plurality of interlayer insulating layers 132m and a plurality of sacrificial insulating layers 130s in the chip area CA and the outer area DA, the chip area CA A plurality of sacrificial insulating layers 130s located in at least a portion of may be selectively removed and a gate electrode 130 may be formed in the portion from which the sacrificial insulating layers 130s have been removed. Accordingly, the gate stacked structure 120 in which a plurality of interlayer insulating layers 132m and a plurality of gate electrodes 130 are alternately stacked is located in at least a portion of the chip area CA, and a plurality of interlayer insulating layers 132m are located in the outer area DA. A sacrificial stacked structure 120s in which an insulating layer 132m and a plurality of sacrificial insulating layers 130s are alternately stacked may be located.

In the embodiment, in the chip area CA and the outer area DA, except for some areas included in the connection area 104 or the pattern of the outer area DA (e.g., key pattern 300, etc.), The gate stacked structure 120 and the sacrificial stacked structure 120s may be provided as a whole. For example, the gate stacked structure 120 may be located in at least a portion of the chip area CA, and the sacrificial stacked structure 120s may be located in the outer area DA and/or another part of the chip area CA. .

As an example, gate stacking from one side (left side of FIG. 1) of the semiconductor device 10 in the first direction (Y-axis direction of the drawing) to the other side (right side of FIG. 1) of the semiconductor device 10 in the first direction. A portion where the structure 120 and the sacrificial layered structure 120s are formed as a whole may be provided. For example, from one side (upper side in FIG. 1) of the semiconductor device 10 in the second direction (X-axis direction of the drawing) to the other side (lower side in FIG. 1) of the semiconductor device 10 in the first direction. A portion may be provided where the gate stacked structure 120 and the sacrificial stacked structure 120s are continuously formed as a whole.

According to this, the area of the semiconductor device 10 can be reduced because errors in the manufacturing process, etc. do not need to be considered.

In an embodiment, a pattern portion 310 included in the key pattern 300 may be provided in the outer area DA. The key pattern 300 or the pattern portion 310 may be composed of a terminal key having a stepped edge. Then, in order to form a channel structure (CH) with a high aspect ratio, an opaque hard mask (or an opaque photoresist pattern), for example, an amorphous carbon layer, is used. layer, ACL), an alignment process such as an alignment process, an overlay process, etc. can be performed using step information of the key pattern 300 or the pattern portion 310.

As described above, when it includes the first and second sacrificial stacked portions 121s and 122s corresponding to the first and second gate stacked portions 121 and 122, the pattern portion 310 includes the first sacrificial stacked portion located below. It may be located in the stacked portion 121s or the corresponding insulating structure 132. The second gate stacked portion 122 or the second sacrificial stacked portion 122s may be formed by aligning the pattern portion 310 located on the first sacrificial stacked portion 121s. When it includes three or more gate stacked parts and three or more sacrificial stacked parts, the pattern portion 310 may be located in the sacrificial stacked part located below the two adjacent sacrificial stacked parts or in the corresponding insulating structure.

The key pattern 300 according to the embodiment will be described in more detail with reference to FIGS. 5 to 7 along with FIGS. 1 to 4.

FIG. 5 is a plan view schematically showing the pattern portion 310 of the key pattern 300 included in the semiconductor device 10 shown in FIG. 1. Figure 6 is a cross-sectional view taken along line B-B' of Figure 5, and is a cross-sectional view taken along line C-C' of Figure 5 in Figure 7.

FIG. 5 schematically shows the positions of the protruding portion 316 and the penetrating portion 318 of the pattern portion 310. In Figure 5(a), a plurality of first pattern parts 310a are shown to confirm alignment in the first direction (Y-axis direction in the drawing), and in Figure 5(b), a plurality of first pattern parts 310a are shown in the second direction (Y-axis direction in the drawing). A plurality of second pattern portions 310b are shown to confirm alignment in the X-axis direction. For clear understanding, in FIGS. 6 and 7 , the first sacrificial laminated portion 121s where the pattern portion 310 is located, the second substrate 110, and the filling portion 318h located within the through portion 318. ) A portion of the second sacrificial laminated portion 122s including ) is shown together.

1 to 7, the pattern portion 310 according to the embodiment includes an insulating structure 312 including a base portion 314 and a protrusion 316, and an insulating structure on at least one side of the protrusion 316. It may include a penetrating portion 318 penetrating 312 . For example, a penetrating portion 318 penetrating the insulating structure 312 may be directly connected to at least one side of the protruding portion 316 .

Here, the protrusion 316 protrudes above the base portion 314 so that the upper surface 316s of the protrusion 316 is closer to that of the base portion 314 in the thickness direction (Z-axis direction of the drawing) of the semiconductor device 10. It may be located higher than the upper surface 314s. At this time, the upper part may mean a part located far from the second substrate 110 and the lower part may mean a part located close to the second substrate 110. For example, the upper surface 316s of the protrusion 316 may refer to the surface of the protrusion 316 located furthest from the second substrate 110, and the upper surface 314s of the base portion 314 may refer to the surface of the protrusion 316 located furthest from the second substrate 110. 2 This may refer to the side of the base portion 314 located furthest from the substrate 110.

A first penetrating sacrificial layer (reference numeral 331 in FIG. 9, hereinafter the same) for forming at least a portion of the penetrating portion 318 at least a portion of the channel structure CH (e.g., the first channel portion CH1). It can be formed by a process that forms. For example, the second through sacrificial layer (reference numeral 332 in FIG. 9, hereinafter the same) formed in the same process as the first through sacrificial layer 331 for forming the first channel portion CH1 may be selectively formed in a later process. It may be removed to form a penetrating portion 318. For example, the upper surface of the penetrating part 318 or the upper surface 316s of the protruding part 316 may be located on the same plane as the upper surface of the first channel portion CH1, and the upper surface of the penetrating part 318 may be located on the same plane. The lower surface 318s may be located on the same plane as the lower surface of the first channel portion CH1. However, the embodiment is not limited to this. Depending on the embodiment, the upper surface of the penetrating part 318 or the upper surface 316s of the protruding part 316 is located on a different plane from the upper surface of the first channel portion CH1, or the lower surface of the penetrating part 318 (318s) may be located on a plane different from the lower surface of the first channel portion (CH1).

In the embodiment, the first edge 321 of the protrusion 316, including the portion adjacent to the through portion 318, has a first step, and the second edge of the protrusion 316 that is not adjacent to the through portion 318 ( 322) may have a second step that is smaller than the first step. For example, the first step may be a step between the upper surface 316s of the protrusion 316 and the lower surface 318s of the penetrating part 318, and the second step may be the upper surface 316s of the protrusion 316. ) and the upper surface 314s of the base portion 314, or the upper surface 316s of the protrusion 316 and the lower surface of the protrusion 316.

In this way, the pattern portion 310 may have a first edge 321 and a second edge 322 having a plurality of different steps (for example, a first step and a second step). At least one of the plurality of steps (more specifically, the first step) is a first through sacrificial layer 331 for forming at least a portion of the channel structure CH (for example, the first channel portion CH1). It may be formed through a forming process (for example, a process of forming the first through sacrificial layer 331 and the second through sacrificial layer 332). More specifically, the first step may be formed by the boundary surface of the portion where the second penetrating sacrificial layer 332 was located. Accordingly, alignment information or position information during the formation process of the first through sacrificial layer 331 can be obtained from the first step. And another one of the plurality of steps (more specifically, the second step) may be formed through a process of forming the protrusion 316. Accordingly, alignment information or position information in the formation process (e.g., photolithography process) of the photoresist pattern (reference numeral 342 in FIG. 11, the same hereinafter) for forming the protrusion 316 can be obtained from the second step. there is. In this way, since the pattern portion 310 has a plurality of steps, various alignment information or position information can be obtained.

In the embodiment, the second penetrating sacrificial layer 332 located within the penetrating portion 318 is removed, so that the second penetrating sacrificial layer 332 does not remain in the final structure, and the protrusion 316 of the insulating structure 312 forms the first step. and may protrude to form a second step. Accordingly, there is a difference from the comparative example in which the portion excluding the second through sacrificial layer is etched in the manufacturing process, and the second through sacrificial layer protrudes to form a step in the final structure.

In an embodiment, the pattern portion 310 may have a protrusion 316 extending in one direction when viewed in plan, and a penetrating portion 318 may be located on both sides of the protrusion 316 in one direction. A first edge 321 having a first step is located on both sides of the protrusion 316 in one direction, and a second edge 322 is located on both sides of the protrusion 316 in a cross direction that intersects the one direction. can be located That is, the pattern portion 310 includes two first edges 321 extending parallel to each other, and two first edges 321 extending in a direction intersecting (e.g., perpendicular to) the first edge 321 and parallel to each other. 2 May include edges 322. At this time, the first edge 321 may extend in a direction intersecting the extension direction of the protrusion 316, and the second edge 322 may extend in a direction parallel to the extension direction of the protrusion 316.

As shown in (a) of FIG. 5, in the first pattern portion 310a for checking alignment in the first direction (Y-axis direction in the drawing), the protrusion 316 extends in the first direction, Penetrating portions 318 may be located on both sides of the protruding portion 316 in the first direction. Accordingly, the first edge 321 having the first step is located on both sides in the first direction and may extend in the second direction (X-axis direction of the drawing), and the second edge 322 having the second step are located on both sides of the second direction and may extend in the first direction. Alignment in the first direction can be confirmed using the first edge 321 provided with the first step having alignment information or position information during the forming process of the first penetrating sacrificial layer 331.

As shown in (b) of FIG. 5, in the second pattern portion 310b for checking alignment in the second direction (X-axis direction in the drawing), the protrusion 316 extends in the second direction, Penetrating portions 318 may be located on both sides of the protruding portion 316 in the second direction. Accordingly, the first edge 321 having a first step is located on both sides in the second direction and may extend in the first direction (Y-axis direction of the drawing), and the second edge 322 having a second step are located on both sides of the first direction and may extend in the second direction. Alignment in the second direction can be confirmed using the first edge 321 provided with the first step having alignment information or position information during the forming process of the first penetrating sacrificial layer 331.

In this embodiment, the pattern portion 310 may have a certain direction so that the first edge 321 having the first step can be used for alignment. The first step or first edge 321 may constitute a direct alignment step that provides alignment information or position information in the formation process of the first penetrating sacrificial layer 331, and the second step or second edge ( 322 may constitute an indirect alignment step that provides alignment information or position information in the process of forming the protrusion 316 using the photoresist pattern 342.

Various alignment keys 300a or overlay keys 300b can be formed by directionally arranging the above-described first pattern portion 310a and/or second pattern portion 310b at positions requiring alignment confirmation. .

For example, in the align key 300a located at the top of FIG. 2, a plurality of second pattern parts 310b are located in the first direction (Y-axis direction in the drawing) to form one row, and a second A plurality of rows may be provided in the direction (X-axis direction of the drawing). At this time, in each second pattern portion 310b, first edges 321 may be located on both sides in the second direction. Accordingly, alignment in the second direction can be confirmed using the align key 300a located at the top of FIG. 2.

For example, in the align key 300a located at the bottom of FIG. 2, a plurality of first pattern portions 310a are located in the second direction (X-axis direction in the drawing) to form one row, and the first pattern portion 310a is located at the bottom of FIG. A plurality of rows may be provided in the direction (Y-axis direction of the drawing). At this time, in each first pattern portion 310a, first edges 321 may be located on both sides in the first direction. Accordingly, alignment in the first direction can be confirmed using the align key 300a located at the bottom of FIG. 2.

For example, the overlay key 300b shown in FIG. 2 may include a portion where a plurality of first pattern portions 310a are disposed and a portion where a plurality of second pattern portions 310b are disposed. In the portion where the plurality of first pattern parts 310a are arranged, the plurality of first pattern parts 310a are located in the second direction (X-axis direction in the drawing) to form one row, and in the first direction (X-axis direction in the drawing) A plurality of rows may be provided in the Y-axis direction). In the portion where the plurality of second pattern parts 310b are arranged, the plurality of second pattern parts 310b are located in the first direction (Y-axis direction in the drawing) to form one row, and in the second direction (Y-axis direction in the drawing) A plurality of rows may be provided in the X-axis direction).

The align key 300a and overlay key 300b shown in FIG. 2 are provided for illustrative purposes, and the embodiment is not limited thereto.

When viewed in plan, the protrusion 316 in one direction may have an island shape connecting the two penetrating portions 318 located on both sides. The width W1 of the protruding part 316 in the crossing direction may be smaller than the width W2 of the penetrating part 318 in the crossing direction. The width W2 of the penetrating portion 318 can be made relatively large so that the penetrating portion 318 contacts the entire portion from one side of the protruding portion 316 when viewed in plan. As a result, the length of the first edge 321 on the plane can be secured as much as possible. However, the embodiment is not limited to this. Depending on the embodiment, the width W1 of the protruding part 316 in the crossing direction may be equal to or greater than the width W2 of the penetrating part 318 in the crossing direction.

The length L of the protrusion 316 in one direction may be greater than the width W1 of the protrusion 316 in the cross direction. That is, the protrusion 316 extends long between the two penetrating portions 318, so that the length of each second edge 322 may be greater than the length of each first edge 321 when viewed in plan. According to this, the length L of the protrusion 316 can be ensured to be long so that the pattern portion 310 can be easily recognized during alignment. However, the embodiment is not limited to this, and the length L of the protrusion 316 may be equal to or smaller than the width W1 of the protrusion 316 in the crossing direction.

In an embodiment, an edge of the penetrating portion 318 adjacent to the protruding portion 316 may include a straight portion when viewed in plan. As a result, the first edge 321 of the protrusion 316 formed by the penetrating portion 318 has a straight shape when viewed in plan, thereby improving accuracy in the alignment process. In FIG. 5 , the penetrating portion 318 has a square planar shape with rounded corners, and the protrusion 316 has a square (eg, rectangular) planar shape with a uniform width W1. However, the embodiment is not limited to this. The penetrating portion 318 may have various planar shapes, such as circular, oval, or polygonal shapes. And when viewed in plan, the protrusion 316 may include some parts having different widths, have an oval or polygonal planar shape, or have various shapes such as rounded parts, curved parts, or angled parts. It may be possible. Accordingly, at least a portion of the first edge 321 may be provided with a rounded part, a curved part, an angled part, etc.

The planar shape of the penetrating portion 318 may be the same as or different from the planar shape of the first channel portion CH1. When viewed from the same plane, the size or area of the penetrating portion 318 may be the same as or different from the size or area of the first channel portion CH1. For example, when viewed from the same plane, the size or area of the penetrating portion 318 may be larger than the size or area of the first channel portion CH1. According to this, it may be advantageous to form the first edge 321 as an overall straight portion. However, the embodiment is not limited to this. In order to obtain more precise alignment information or position information, the size or area of the penetrating portion 318 may be made the same or very similar to the size or area of the first channel portion CH1 when viewed from the same plane.

As described above, since the sacrificial laminated structure 120s is located in the outer area DA in the embodiment, the insulating structure 312 provided in the pattern portion 310 is the sacrificial laminated structure 120s (e.g., the first It may include a sacrificial laminated portion (121s). For example, the base portion 314 may include a plurality of interlayer insulating layers 132m and a plurality of sacrificial insulating layers 130s that are alternately stacked. The protrusion 316 may include an interlayer insulating layer 132m and/or a sacrificial insulating layer 130s. For example, the protrusion 316 may include a plurality of interlayer insulating layers 132m and/or a plurality of sacrificial insulating layers 130s, such that the thickness of the protrusion 316 at the second edge 322 of the protrusion 316 A sufficient second step corresponding to can be secured. However, the embodiment is not limited to this, and the protrusion 316 may include one interlayer insulating layer 132m and/or one sacrificial insulating layer 130s.

According to this, the sacrificial laminated structure 120s provided in the outer area DA is provided without removing the sacrificial laminated structure 120s, and the process of removing part of the sacrificial laminated structure 120s from the outer area DA is not performed, and the margin due to process errors, etc. There is no need to consider . Accordingly, the semiconductor device 10 can be formed through an easy process and the area of the semiconductor device 10 can be reduced.

In an embodiment, at least a portion of the interior of the penetrating portion 318 may be filled with a filling portion 318h containing an insulating material. This is because the second penetrating sacrificial layer 332 formed in the first sacrificial laminated portion 121s was removed to form the penetrating portion 318, and then the second sacrificial laminated portion 122s was formed. That is, in the process of forming the second sacrificial laminated portion 122s, the sacrificial insulating layer 130s and/or the interlayer insulating layer constituting the second sacrificial laminated portion 122s are placed in the empty space inside the through portion 318 ( 132m) can be filled to form a filled portion 318h. At this time, since the penetrating portion 318 has a high aspect ratio, the sacrificial insulating layer 130s and/or the interlayer insulating layer 132m may not entirely fill the interior of the penetrating portion 318. Accordingly, a void V extending in the vertical direction may be provided inside the penetrating portion 318. Accordingly, a penetrating portion or a sacrificial penetrating layer provided with a sacrificial material including polycrystalline silicon, a metal material, etc. may not be provided therein.

However, the embodiment is not limited to this. Accordingly, the sacrificial insulating layer 130s and/or the interlayer insulating layer 132m may be entirely located inside the penetrating portion 318 and no void V may be provided. As another example, the filling portion 318h that fills the interior of the penetrating portion 318 is formed separately from the second sacrificial laminated portion 122s, or is made of a material different from the sacrificial insulating layer 130s and/or the interlayer insulating layer 132m. It may also include . Various other variations are possible.

According to an embodiment, the pattern portion 310 included in the key pattern 300 includes a plurality of steps, so that sufficient alignment information or position information can be obtained during alignment. And even when using an opaque hard mask, direct alignment is possible using the step of the pattern portion 310. For example, the pattern portion 310 may be used in an alignment process or an alignment process using overlay.

At this time, even when the second penetrating sacrificial layer 332 is removed during the process of removing the photoresist pattern 342, the pattern portion 310 can be formed with an easy process.

For example, in order to increase the number of gate electrodes 130 to improve data storage capacity, the penetrating sacrificial layer (reference numeral 330 in FIG. 9, hereinafter the same) may include carbon. If the penetrating sacrificial layer 330 contains carbon, the penetrating sacrificial layer 330 can be stably formed within the preliminary penetrating portion even if the preliminary penetrating portion is formed deep, and the penetrating sacrificial layer 330 can be stably removed in a later process. Because you can. At this time, if the photoresist pattern 342 contains carbon, the second through sacrificial layer 332 may be removed in the process of removing the photoresist pattern 342. In the embodiment, even in this case, the pattern portion 310 is It can be formed in an easy process. This will be described in more detail in the manufacturing method of the semiconductor device 10 with reference to FIGS. 8 to 17. However, the embodiment is not limited to this. Accordingly, even if the second penetrating sacrificial layer 332 is not removed in the process of removing the photoresist pattern 342, the pattern portion 310 according to the embodiment may be formed.

As a result, the penetrating sacrificial layer 330 can be formed using a sacrificial material (for example, a sacrificial material containing carbon) that can overcome process limitations related to increasing the number of gate electrodes 130. Accordingly, the performance and productivity of the semiconductor device 10 can be improved.

On the other hand, when the sacrificial material included in the through sacrificial layer is polycrystalline silicon, tungsten, etc., if the preliminary penetrating portion is formed deeply to increase the number of gate electrodes, it is difficult to stably form the penetrating sacrificial layer within the preliminary penetrating portion or the preliminary penetrating portion is damaged. There may be a problem in that it is difficult to stably remove the penetrating sacrificial layer from. Accordingly, there was a limit to increasing the number of gate electrodes.

In FIG. 6 , the side adjacent to the sacrificial insulating layer 130s in the through portion 318 and the side of the cell insulating layer 132 in the through portion 318 are located on the same plane. However, the embodiment is not limited to this. As another example, the side adjacent to the sacrificial insulating layer 130s in the through portion 318 and the side of the cell insulating layer 132 in the through portion 318 are located on different planes. An example of this will be described in detail later with reference to FIG. 18.

The manufacturing method of the above-described pattern portion 310 and the semiconductor device 10 including the same will be described in detail with reference to FIGS. 8 to 17. Detailed descriptions of parts that have already been described will be omitted, and parts that have not been explained will be explained in detail.

8 to 17 are diagrams illustrating a method of manufacturing the pattern portion 310 and the semiconductor device 10 including the same according to an embodiment. In the following manufacturing method of the semiconductor device 10, the manufacturing method of the gate stacked structure 120, the channel structure (CH), and the pattern portion 310 will be mainly described.

As shown in FIG. 8, a second substrate 110 is formed on the circuit region 200, and interlayer insulating layers 132m and sacrificial insulating layers 130s are alternately stacked on the second substrate 110. Thus, the first sacrificial laminated portion 121s can be formed.

At this time, the first sacrificial stacked portion 121s may be formed in the chip area CA and the outer area DA. The first sacrificial laminated part 121s located in the outer area DA may be a part of the first sacrificial laminated part 121s shown in FIG. 3 or a part of the insulating structure 312, and may be a part of the chip area ( The first sacrificial stacked portion 121s located at CA) may be a portion for forming the first gate stacked portion 121 shown in FIG. 3.

The sacrificial insulating layer 130s located in the cell array area 102 of the chip area CA is a layer that is replaced with a gate electrode (reference numeral 130 in FIG. 17, hereinafter the same) through a subsequent process. The sacrificial insulating layer 130s located in the cell array area 102 of the chip area CA may be formed to correspond to a portion where the gate electrode 130 is to be formed. Accordingly, when the sacrificial insulating layer 130s located in the cell array area 102 of the chip area CA is replaced with the gate electrode 130 in the subsequent process, the cell insulating layer 132 and the gate electrode 130 are alternately A stacked first gate stacked portion 121 may be formed.

In FIG. 8 , a horizontal insulating layer 116 and a second horizontal conductive layer 114 are formed on the second substrate 110 in the chip area CA, and the horizontal insulating layer 116 and the second horizontal conductive layer 114 are formed on the second substrate 110 in the chip area CA. ) The first sacrificial laminated portion 121s was formed on top. The horizontal insulating layer 116 may be formed of a material different from the cell insulating layer 132 (eg, the interlayer insulating layer 132m). However, the embodiment is not limited to this, and it is possible that the horizontal insulating layer 116 and/or the second horizontal conductive layer 114 are not provided.

Subsequently, as shown in FIG. 9, a penetrating sacrificial layer 330 that penetrates the first sacrificial stacked portion 121s may be formed.

The penetrating sacrificial layer 330 may include a first penetrating sacrificial layer 331 and a second penetrating sacrificial layer 332. The first penetrating sacrificial layer 331 is located in the cell array region 102 and forms at least a portion (e.g., a first channel portion (reference symbol CH1 in FIG. 3) of the channel structure (reference symbol CH in FIG. 17). The second penetrating sacrificial layer 332 is located in the outer area DA and may correspond to the portion where the penetrating portion (reference numeral 318 in FIG. 15, hereinafter the same) will be formed.

More specifically, a preliminary penetration part penetrating the first sacrificial laminated portion 121s is formed corresponding to the portion where the penetration sacrificial layer 330 is to be formed, and a sacrificial material is filled in the preliminary penetration part to form the through sacrificial layer 330. can do. More specifically, a preliminary penetration part penetrating the first sacrificial stacked portion 121s is formed corresponding to the portion where the first penetration sacrificial layer 331 and the second penetration sacrificial layer 332 are to be formed, and the sacrifice is formed in the preliminary penetration part. The first penetrating sacrificial layer 331 and the second penetrating sacrificial layer 332 may be formed by filling the material with the material.

In one embodiment, the preliminary penetration part may be formed through an etching process (eg, a plasma etching process), and the process of filling the preliminary penetration part may be performed through various processes (eg, a deposition process). At this time, the penetrating sacrificial layer 330 may include a material containing carbon (carbon-based material) as a sacrificial material, or may include the same material as the material included in the photoresist pattern (reference numeral 342 in FIG. 11, hereinafter the same). You can. However, the embodiment is not limited to this, and the penetrating sacrificial layer 330 may include at least one of polycrystalline silicon, tungsten, and titanium nitride.

According to an embodiment, in the process of forming the through sacrificial layer 330, a second device located in a portion corresponding to the gate contact portion (reference numeral 184 in FIG. 3), the source contact portion (reference numeral 186 in FIG. 3), the input/output connection wiring, etc. 3 A penetrating sacrificial layer can be formed together.

Subsequently, as shown in FIG. 10, a protective layer 340 may be formed on the first sacrificial laminated portion 121s. The protective layer 340 may protect the first sacrificial stacked portion 121s during the process of forming the photoresist pattern 342. The process of forming the protective layer 340 may be performed by various processes (eg, deposition process).

The protective layer 340 may include various materials. For example, the protective layer 340 may include the same material or a different material from the sacrificial insulating layer 130s or the cell insulating layer 132 (eg, the interlayer insulating layer 132m).

If the protective layer 340 includes a material different from the cell insulating layer 132 (e.g., the interlayer insulating layer 132m) or the sacrificial insulating layer 130s, the cell insulating layer 130 may be removed during the removal process of the protective layer 340. Impact on (132) (eg, interlayer insulating layer 132m) or sacrificial insulating layer 130s can be minimized. If the protective layer 340 includes the same material as the sacrificial insulating layer 130s, the protective layer 340 can be formed using the same process conditions as the process for forming the sacrificial insulating layer 130s. Accordingly, the influence of the protective layer 340 on the first sacrificial laminated portion 121s during the manufacturing process can be minimized, and the protective layer 340 can be manufactured through an easy process.

In an embodiment, the protective layer 340 may include polycrystalline silicon, oxide (eg, silicon oxide), nitride (eg, silicon nitride), nitride (eg, silicon nitride), etc. However, the embodiment is not limited to this, and the material of the protective layer 340 may be modified in various ways.

Subsequently, as shown in FIG. 11, a photoresist pattern 342 may be formed on the protective layer 340. FIG. 12 shows the planar shape of the second penetrating sacrificial layer 332 located in the outer area DA and the photoresist pattern 342 located on the protective layer 340. In FIG. 12, a portion corresponding to FIG. 5 is shown, focusing on the positions of the second through sacrificial layer 332 and the photoresist pattern 342.

A photoresist pattern 342 may be formed entirely in the chip area CA. In the outer area DA, the photoresist pattern 342 is located on both sides of the first part and a first part corresponding to the protrusion (reference numeral 316 in FIG. 13) when viewed in plan and includes a second penetrating sacrificial layer ( A second part may be included in a part overlapping with part of 332). The first part and the second part may have the same width in the crossing direction, but the embodiment is not limited thereto.

Next, as shown in FIG. 13, an etching process is performed to etch a portion of the protective layer 340 of the outer area DA and a portion of the first sacrificial laminated portion 121s using the photoresist pattern 342. You can.

An insulating structure 312 including a base portion 314 and a protruding portion 316 may be formed in the outer area DA through an etching process. At this time, the protrusion 316 is formed by the photoresist pattern 342 and may have a second edge (reference numeral 322 in FIG. 5, hereinafter the same) having a second step. In the etching process, the boundary between the second penetrating sacrificial layer 332 and the protrusion 316, that is, the first edge (reference numeral 321 in FIG. 5, hereinafter the same) is covered by the photoresist pattern 342 and is therefore not etched. It can remain without it.

Subsequently, as shown in FIG. 14, the photoresist pattern (reference numeral 342 in FIG. 13, hereinafter the same) can be removed. At this time, the second penetrating sacrificial layer (reference numeral 332 in FIG. 13, hereinafter the same) may be removed together to form the penetrating portion 318.

In one embodiment, in the process of removing the photoresist pattern 342, the second penetrating sacrificial layer 332 may be removed together. For example, the material included in the photoresist pattern 342 and the sacrificial material included in the second penetrating sacrificial layer 332 may include the same material (eg, carbon). The process of removing the photoresist pattern 342 may include an ashing process and a strip process, and the second through sacrificial layer 332 may be removed in the ashing process. However, the embodiment is not limited to this, and the second through sacrificial layer 332 may be removed in a strip process or in a process different from the photoresist pattern 342.

When the second penetrating sacrificial layer 332 is removed, a first edge 321 of the protrusion 316 adjacent to the penetrating portion 318 and having a first step may be formed.

In this way, in the embodiment, the first sacrificial laminated portion 121s may form the insulating structure 312 provided in the pattern portion 310. Accordingly, the second penetrating sacrificial layer 332 or the penetrating portion 318 may be formed in the first sacrificial stacked portion 121s in the outer area DA.

Subsequently, as shown in FIG. 15, the protective layer 340 can be removed. The process of removing the protective layer 340 may be performed using various processes (eg, an etching process).

Subsequently, as shown in FIG. 16, the interlayer insulating layer 132m and the sacrificial insulating layer 130s may be alternately stacked on the first sacrificial laminated portion 121s to form a second sacrificial laminated portion 122s. . In the process of forming the second sacrificial laminated portion 122s, the second sacrificial laminated portion 122s may be formed in an aligned state using a key pattern including the pattern portion 310.

In one embodiment, a portion of the second sacrificial laminated portion 122s may fill the interior of the penetrating portion 318 to form a filling portion 318h. However, the embodiment is not limited to this, and the penetrating portion 318 may be filled with a material other than the second sacrificial laminated portion 122s, or at least a portion of the penetrating portion 318 may be maintained as an empty space.

Subsequently, as shown in FIG. 17, the semiconductor device 10 can be manufactured by forming the separation structure 146 and the gate electrode 130 and forming the second wiring portion 180.

More specifically, a preliminary penetration part or a penetration sacrificial layer that penetrates the second sacrificial laminated portion 122s may be formed. By removing the through sacrificial layer (for example, the first through sacrificial layer 331) located in the first sacrificial stacked portion 121s and/or the second sacrificial stacked portion 122s in the cell array area 102, A penetration part can be formed.

A channel structure (CH) may be formed within the channel penetrating portion. That is, within the channel penetration portion, at least a portion of the gate dielectric layer (reference numeral 150 in FIG. 4, hereinafter the same), the channel layer (reference numeral 140 in FIG. 4, hereinafter the same), and the core insulating layer (reference numeral 142 in FIG. 4, hereinafter the same) ), channel pads (reference numeral 144 in FIG. 4, hereinafter the same), etc. may be formed sequentially. At least a portion of the gate dielectric layer 150, the channel layer 140, the core insulating layer 142, the channel pad 144, etc. may be formed using various processes (eg, deposition processes). For example, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process may be used. However, the embodiment is not limited to this and various other processes may be applied.

Subsequently, an opening for the separation structure may be formed to penetrate the sacrificial laminated structure 120s in the chip area CA. The opening for this separation structure may be formed in an area corresponding to the separation structure 146. The sacrificial insulating layer 130s located in at least a portion of the chip area CA may be selectively removed by an etching process through the opening for the separation structure. Then, the gate electrode 130 can be formed by filling the portion where the sacrificial insulating layer 130s has been removed with a conductive material constituting the gate electrode 130. At this time, the opening for the separation structure may be formed to expose the horizontal insulating layer (reference numeral 116 in FIG. 16, hereinafter the same). At least a portion of the horizontal insulating layer 116 may be removed in the etching process through the opening for the separation structure, and the portion where the horizontal insulating layer 116 was removed may be filled with a material constituting the first horizontal conductive layer 112. 1 A horizontal conductive layer 112 can be formed. Then, the separation structure 146 can be formed by filling the inside of the separation structure with an insulating material.

In one embodiment, the opening for the separation structure may be formed by an etching process (e.g., a plasma etching process), and the process of filling the opening for the separation structure may be performed by various processes (e.g., a deposition process). there is.

A gate contact portion (reference numeral 184 in FIG. 3 ), a source contact portion ( Reference numeral 186 in FIG. 3), input/output connection wiring, second wiring portion 180, etc. may be formed.

As described above, in the embodiment, the second edge 322 having the second step is formed using an etching process using the photoresist pattern 342, and the removal process of the photoresist pattern 342 (i.e., the second through A first edge 321 having a first step may be formed using a removal process of the sacrificial layer 332.

According to an embodiment, even when the penetrating sacrificial layer 330 is removed during the process of removing the photoresist pattern 342, the pattern portion 310 of the key pattern 300 can be formed with an easy process. For example, even when the penetrating sacrificial layer 330 and the photoresist pattern 342 include the same material (eg, a material containing carbon), the pattern portion 310 can be formed through an easy process. That is, according to the embodiment, the process of forming the protective layer 340, the process of forming the photoresist pattern 342, the process of forming the protrusion 316 using the photoresist pattern 342, and the process of forming the photoresist pattern 342 ) The pattern portion 310 of the key pattern can be formed using a simple process including a process of removing the protective layer 340 and a process of removing the protective layer 340.

On the other hand, in the comparative example in which the second through sacrificial layer protrudes more than other parts in the final structure to form a step, if the second through sacrificial layer includes the same material as the photoresist pattern, the through sacrificial layer is are removed together. In order to prevent this, a step is first formed in a part other than the second penetrating sacrificial layer, a mask pattern is formed in a part of the step, then the second penetrating sacrificial layer is formed, and the mask pattern is removed to form a second protruding shape. A process for forming a penetrating sacrificial layer must be performed. According to this, the process is very complicated because the process of forming the step first and the process of forming the mask pattern in some parts of the step must be added.

Hereinafter, a semiconductor device according to an embodiment different from the above-described embodiment will be described in more detail with reference to FIGS. 18 to 20. Detailed descriptions of parts that are identical or extremely similar to those already described will be omitted, and only other parts will be described in detail.

18 is a partial cross-sectional view showing part of a semiconductor device according to another embodiment. Figure 18 shows a portion corresponding to Figure 6.

Referring to FIG. 18 , in the semiconductor device according to the embodiment, the penetrating portion 318 located in the outer area DA may have an extended portion 318p corresponding to the sacrificial insulating layer 130s. That is, the surface of the penetrating part 318 adjacent to the sacrificial insulating layer 130s may protrude from the surface of the penetrating part 318 where the cell insulating layer 132 is located. For example, a step may be located between a side of the penetrating portion 318 adjacent to the sacrificial insulating layer 130s and a side of the penetrating portion 318 where the cell insulating layer 132 is located.

For example, if the protective layer (reference numeral 340 in FIG. 10, hereinafter) used in the manufacturing process of the semiconductor device includes the same material as the sacrificial insulating layer 130s, the penetrating portion in the process of removing the protective layer 340 A portion of the sacrificial insulating layer 130s adjacent to 318 may be removed. For example, a portion of the sacrificial insulating layer 130s adjacent to the penetration portion 318 may be removed equal to the thickness of the protective layer 340 . Accordingly, the penetrating portion 318 has an expanded portion 318p corresponding to the sacrificial insulating layer 130s. Even if the expansion portion 318p is provided in the penetrating portion 318 in this way, the width of the expansion portion 318p in the horizontal direction is not large, so it may not have an unwanted effect on the manufacturing process or the characteristics of the pattern portion 310.

For example, the protective layer 340 and the sacrificial insulating layer 130s may include nitride (eg, silicon nitride) to improve the stability of the manufacturing process. However, the embodiment is not limited to this, and the protective layer 340 and/or the sacrificial insulating layer 130s may include various materials. Alternatively, even if the protective layer 340 and the sacrificial insulating layer 130s include different materials, the side adjacent to the sacrificial insulating layer 130s in the through portion 318 and the cell insulating layer 132 in the through portion 318 This positioned side may be located on the same plane. Alternatively, the expanded portion 318p of the penetrating portion 318 may be formed in a process other than the process of removing the protective layer 340. Various other variations are possible.

Figure 19 is a partial cross-sectional view schematically showing a part of a semiconductor device according to another embodiment. Figure 19 shows a portion corresponding to Figure 6.

Referring to FIG. 19 , in the embodiment, the insulating structure 312 provided in the pattern portion 310 in the outer area DA may include a single insulating structure 132s. A single insulating structure may mean a structure composed of one insulating layer made of one insulating material. Accordingly, the single insulating structure 132s of the pattern portion 310 includes the base portion 314 and the protrusion 316, and the penetrating portion 318 of the pattern portion 310 is single on at least one side of the protrusion 316. It may penetrate the insulating structure 312.

In an embodiment, the single insulating structure 132s may include oxide, nitride, or nitride. For example, the single insulating structure 132s may include oxide (eg, silicon oxide).

In the embodiment, the sacrificial lamination is performed by removing at least a portion of the sacrificial lamination structure, for example, the first sacrificial lamination portion (reference numeral 121s in FIG. 3, the same hereinafter) from the outer area DA and forming a single insulating structure 132s. Stress caused by the structure, for example, the first sacrificial laminated portion 121s, can be reduced.

In an embodiment, at least a portion of the interior of the penetrating portion 318 may be filled with a filling portion 318h containing an insulating material. This is because the second penetrating sacrificial layer (reference numeral 332 in FIG. 9, hereinafter the same) formed in the single insulating structure 132s was removed to form the penetrating portion 318, and then the second sacrificial laminated portion 122s was formed. am. That is, in the process of forming the second sacrificial laminated portion 122s, the sacrificial insulating layer 130s and/or the interlayer insulating layer constituting the second sacrificial laminated portion 122s are placed in the empty space inside the through portion 318 ( 132m) can be filled to form a filled portion 318h. At this time, since the penetrating portion 318 has a high aspect ratio, the sacrificial insulating layer 130s and/or the interlayer insulating layer 132m may not entirely fill the interior of the penetrating portion 318. Accordingly, a void V extending in the vertical direction may be provided inside the penetrating portion 318. Accordingly, a penetrating portion or a sacrificial penetrating layer provided with a sacrificial material including polycrystalline silicon, a metal material, etc. may not be provided therein.

However, the embodiment is not limited to this. Accordingly, the sacrificial insulating layer 130s and/or the interlayer insulating layer 132m may be entirely located inside the penetrating portion 318 and no void V may be provided. As another example, the filling portion 318h that fills the interior of the penetrating portion 318 is formed separately from the second sacrificial laminated portion 122s, or is made of a material different from the sacrificial insulating layer 130s and/or the interlayer insulating layer 132m. It may also include . Various other variations are possible.

Unless otherwise stated, the description of the manufacturing method with reference to FIGS. 8 to 17 may be directly applied to the manufacturing method of the semiconductor device according to the embodiment.

In an embodiment, a single insulating structure 132s may constitute the insulating structure 312 provided in the pattern portion 310 . Between the process of forming the first sacrificial laminated portion 121s (see FIG. 8) and the process of forming the through sacrificial layer 330 (see FIG. 9), the first sacrificial laminated portion 121s is formed in the outer area DA. A process of removing and forming a single insulating structure 132s may be further included. And the pattern portion 310 may be formed on the heat insulating structure 132s.

If the process of forming the pattern portion 310 is explained based on the outer area DA, a second penetrating sacrificial layer (reference numeral 322 in FIG. 9, hereinafter the same) is formed on the single insulating structure 132s, and a single insulating structure is formed. A protective layer (reference numeral 340 in FIG. 10) and a photoresist pattern (reference numeral 342 in FIG. 11, hereinafter the same) are formed on the structure 132s, and the single insulating structure 132s is formed using the photoresist pattern 342. A portion may be removed to form the insulating structure 312 composed of a single insulating structure 132s including the base portion 314 and the protruding portion 316. Then, the photoresist pattern 342 and the second penetrating sacrificial layer 332 are removed, and the protective layer 340 is removed to form the pattern portion 310. Depending on the embodiment, at least a portion of the second sacrificial laminated portion 122s formed on the pattern portion 310 in the outer area DA may be removed and a single insulating structure may be formed in the corresponding portion.

In FIG. 19 , as shown in FIG. 6 , the penetrating portion 318 is shown not including an expanded portion (reference numeral 318p in FIG. 18 ). However, the embodiment is not limited thereto, and the penetrating portion 318 may include an expanded portion 318p shown in FIG. 18 . Various other variations are possible.

FIG. 20 is a schematic cross-sectional view of a semiconductor device 20 according to an additional embodiment.

Referring to FIG. 20 , the semiconductor device 20 according to the embodiment may be a bonded semiconductor device formed by bonding a circuit region 200a and a cell region 100a. For example, the semiconductor device 20 may have the circuit region 200a and the cell region 100a formed through a hybrid bonding chip-to-chip (C2C) bonding process, a chip-to-wafer bonding process, or It can be bonded by a wafer-to-wafer bonding process.

The circuit region 200a is electrically connected to the first substrate 210, the circuit element 220, the first wiring portion 230, and the first wiring portion 230 and faces the cell region 100a. A first joint structure 290 located on the surface may be provided. Areas other than the first bonding structure 290 on the side opposite to the cell region 100a may be covered by the first bonding insulating layer 292.

The cell region 100a is electrically connected to the second substrate 110a, the gate stack structure 120, the channel structure (CH), the second wiring portion 180, and the second wiring portion 180. and may include a second bonding structure 190 located on the surface opposite to the circuit area 200a. Areas other than the second bonding structure 190 may be covered by the second bonding insulating layer 192.

In an embodiment, the second substrate 110a may be a semiconductor substrate including a semiconductor material. For example, the second substrate 110a may be a semiconductor substrate made of a semiconductor material, or may be a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the second substrate 110a may be made of single crystal or polycrystalline silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator. Alternatively, the second substrate 110a may be composed of an insulating layer or a support member including an insulating material. This is because after bonding the cell region 100a to the circuit region 200a, the semiconductor substrate provided in the cell region 100a can be removed and a support member including an insulating layer or an insulating material can be formed.

In one embodiment, the gate stacked structure 120 may be sequentially stacked on the lower part of the second substrate 110a in the drawing, so that the gate stacked structure 120 shown in FIG. 3 is upside down. Additionally, the channel structure CH penetrating the gate stacked structure 120 may also have a structure that is an up-and-down inversion of the channel structure CH shown in FIG. 3 or FIG. 4 . As a result, the channel structure CH may have an inclined side surface so that the width becomes narrower when viewed in cross section from the circuit area 200a toward the second substrate 110a. Additionally, the channel pad 144 and the second wiring portion 180 located on the gate stacked structure 120 may be located adjacent to the circuit region 200a.

For example, the first bonding structure 290 and/or the second bonding structure 190 may be made of aluminum, copper, tungsten, or an alloy containing them. For example, the first and second bonding structures 290 and 190 include copper, so that the cell region 100a and the circuit region 200a are bonded by copper-to-copper bonding (copper-to-copper bonding). For example, it may be bonded by direct contact.

In FIG. 20 , the gate stacked structure 120 is illustrated to include first and second gate stacked portions 121 and 122. However, differently, it may include one, three or more gate stacked portions. Except as otherwise noted, the structures of the gate stacked structure 120 and the channel structure CH described with reference to FIGS. 1 to 19 may be applied as is. In FIG. 20 , the electrical connection structure of the channel structure CH and the horizontal conductive layers 112 and 114 and/or the second substrate 110a is illustrated to be the same as that in FIG. 2 . The embodiment is not limited to this, and the electrical connection structure between the channel structure CH and the horizontal conductive layers 112 and 114 and/or the second substrate 110a may be modified in various ways.

As described above, when the first and second gate stacked portions 121 and 122 are included, first and second sacrificial stacked portions corresponding to the first and second gate stacked portions 121 and 122 are formed in the outer region. The pattern portion included in the key pattern may be located in the first sacrificial laminated portion located closer to the second substrate 110a than the second sacrificial laminated portion. The second gate stacked portion 122 and/or the second sacrificial stacked portion may be formed by aligning them using a key pattern or pattern portion located in the first sacrificial stacked portion. When it includes three or more gate stacked parts and three or more sacrificial stacked parts, the pattern part included in the key pattern may be located in the sacrificial stacked part located below the two adjacent sacrificial stacked parts.

The semiconductor device 20 according to one example may include an input/output pad and an input/output connection wire electrically connected to the input/output pad. The input/output connection wire may be electrically connected to a portion of the second junction structure 190. For example, the input/output pad may be located on the insulating film 198b covering the outer surface of the second substrate 110a. Depending on the embodiment, a separate input/output pad electrically connected to the circuit area 200a may be provided.

As an example, the circuit region 200a and the cell region 100a correspond to the first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 shown in FIG. 21, respectively. This may be the part. Alternatively, the circuit region 200a and the cell region 100a may be regions including the first structure 4100 and the second structure 4200 of the semiconductor chip 2200a shown in FIG. 24, respectively.

An example of an electronic system including the semiconductor device described above will be described in detail as follows.

Figure 21 is a diagram schematically showing an electronic system including a semiconductor device according to an example embodiment.

Referring to FIG. 21 , the electronic system 1000 according to an exemplary embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or a plurality of semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100 .

The semiconductor device 1100 may be a non-volatile memory device, for example, the NAND flash memory device described with reference to FIGS. 1 to 20 . The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be placed next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S includes a bit line (BL), a common source line (CSL), a word line (WL), first and second gate upper lines (UL1, UL2), and first and second gate lower lines (LL1). , LL2), and a memory cell string (CSTR) between the bit line (BL) and the common source line (CSL).

In the second structure 1100S, each of the memory cell strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 and UT2 adjacent to the bit line BL. , and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1 and LT2) and the upper transistors (UT1 and UT2). The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

In an example embodiment, the lower transistors LT1 and LT2 may include ground select transistors, and the upper transistors UT1 and UT2 may include string select transistors. The first and second gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line (WL) may be the gate electrode of the memory cell transistor (MCT), and the gate upper lines (UL1 and UL2) may be the gate electrodes of the upper transistors (UT1 and UT2), respectively.

The common source line (CSL), the first and second gate lower lines (LL1 and LL2), the word line (WL), and the first and second gate upper lines (UL1 and UL2) are located within the first structure (1100F). It may be electrically connected to the decoder circuit 1110 through a first connection wire 1115 extending from to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection wire 1125 extending from the first structure 1100F to the second structure 1100S.

In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one memory cell transistor selected from a plurality of memory cell transistors (MCT). The decoder circuit 1110 and page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through the input/output pad 1101 that is electrically connected to the logic circuit 1130. The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

The processor 1210 may control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistor (MCT) of the semiconductor device 1100, and memory cell transistor (MCT) of the semiconductor device 1100. Data to be read from may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When receiving a control command from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

Figure 22 is a perspective view schematically showing an electronic system including a semiconductor device according to an example embodiment.

Referring to FIG. 22, an electronic system 2000 according to an exemplary embodiment includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and DRAM 2004. ) may include. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 formed on the main board 2001.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of a plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In an exemplary embodiment, the electronic system 2000 includes interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). You can communicate with an external host according to any one of the following. In an example embodiment, the electronic system 2000 may operate with power supplied from an external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

The controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

DRAM (2004) may be a buffer memory to alleviate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a type of cache memory and may provide space for temporarily storing data during control operations for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b that are spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, It may include a connection structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100. You can.

The package substrate 2100 may be a printed circuit board including a package top pad 2130. Each semiconductor chip 2200 may include an input/output pad 2210. The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 21. Each semiconductor chip 2200 may include a gate stacked structure 3210 and a channel structure 3220. The semiconductor chip 2200 may include the semiconductor devices described with reference to FIGS. 1 to 20 , respectively.

In an exemplary embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input/output pad 2210 and the package top pad 2130. Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method and may be electrically connected to the package upper pad 2130 of the package substrate 2100. can be connected According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chip 2200 includes a through electrode (through silicon via, TSV) instead of the bonding wire-type connection structure 2400. They may be electrically connected to each other through a connecting structure.

In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer board different from the main board 2001, and the controller 2002 and the semiconductor chip 2200 are connected by wiring formed on the interposer board. ) may be connected to each other.

23 and 24 are cross-sectional views schematically showing semiconductor packages according to exemplary embodiments, respectively. FIGS. 23 and 24 each illustrate an exemplary embodiment of the semiconductor package 2003 of FIG. 22 and conceptually show a region where the semiconductor package 2003 of FIG. 22 is cut along the cutting line II′.

Referring to FIG. 23, in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body 2120, a package upper pad 2130 disposed on the upper surface of the package substrate body 2120, and a pad disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface. It may include a package bottom pad 2125 and an internal wiring 2135 that electrically connects the package top pad 2130 and the package bottom pad 2125 inside the package substrate body 2120. The package upper pad 2130 may be electrically connected to the connection structure 2400. The package bottom pad 2125 may be connected to the wiring pattern 2005 of the main board 2001 of the electronic system 2000 as shown in FIG. 22 through the conductive connector 2800.

The semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 that are sequentially stacked on the semiconductor substrate 3010, respectively. The first structure 3100 may include a peripheral circuit area including peripheral wiring 3110. The second structure 3200 includes a common source line 3205, a gate stacked structure 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stacked structure 3210, a separation structure 3230, and a channel. It may include a bit line 3240 electrically connected to the structure 3220, and a gate connection wire electrically connected to the word line (reference symbol WL in FIG. 21) of the gate stacked structure 3210.

In the semiconductor chip 2200 or semiconductor device according to the embodiment, the performance and productivity of the semiconductor chip 2200 or semiconductor device can be improved by including a key pattern including a pattern portion including a plurality of steps.

Each semiconductor chip 2200 may include a through wiring 3245 that is electrically connected to the peripheral wiring 3110 of the first structure 3100 and extends into the second structure 3200. The through wiring 3245 may penetrate the gate stacked structure 3210 and may be further disposed outside the gate stacked structure 3210. Each of the semiconductor chips 2200 is electrically connected to the peripheral wiring 3110 of the first structure 3100 and is electrically connected to the input/output connection wiring 3265 and the input/output connection wiring 3265 extending into the second structure 3200. It may further include a connected input/output pad 2210.

In an exemplary embodiment, a plurality of semiconductor chips 2200 in the semiconductor package 2003 may be electrically connected to each other by a connection structure 2400 in the form of a bonding wire. As another example, a plurality of semiconductor chips 2200 or a plurality of parts constituting the same may be electrically connected by a connection structure including a through electrode.

Referring to FIG. 24, in the semiconductor package 2003A, each of the semiconductor chips 2200a is connected to a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a wafer bonding method on the first structure 4100. It may include a second structure 4200 joined to the first structure 4100.

The first structure 4100 may include a peripheral circuit area including a peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 includes a common source line 4205, a gate stacked structure 4210 between the common source line 4205 and the first structure 4100, and a channel structure 4220 penetrating the gate stacked structure 4210. It may include a second junction structure 4250 electrically connected to the isolation structure 4230, the channel structure 4220, and the word line (WL in FIG. 21, hereinafter the same) of the gate stacked structure 4210, respectively. You can. For example, the second junction structure 4250 is connected to the channel structure 4220 through a gate connection wire that is electrically connected to the bit line 4240 and the word line (WL), respectively. ) and can be electrically connected to the word line (WL). The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 may be joined while contacting each other. The joined portion of the first bonding structure 4150 and the second bonding structure 4250 may be formed of, for example, copper (Cu).

In the semiconductor chip 2200a or semiconductor device according to the embodiment, the performance and productivity of the semiconductor chip 2200a or semiconductor device can be improved by including a key pattern including a pattern portion including a plurality of steps.

Each semiconductor chip 2200a may further include an input/output pad 2210 and an input/output connection wire 4265 below the input/output pad 2210. The input/output connection wire 4265 may be electrically connected to a portion of the second junction structure 4250.

In one embodiment, a plurality of semiconductor chips 2200a in the semiconductor package 2003A may be electrically connected to each other by a connection structure 2400 in the form of a bonding wire. As another example, a plurality of semiconductor chips 2200a or a plurality of parts constituting the semiconductor chip 2200a may be electrically connected by a connection structure including a through electrode.

Although the embodiments have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concept of the present invention as defined in the following claims may also fall within the scope of the present invention.

CA: Chip Area
DA: extralateral area
100: Cell area
102: Cell array area
104: connection area
200: circuit area
300: key pattern
310: Pattern part
312: Insulating structure
314: base part
316: protrusion
318: Penetrating part

Claims (10)

A semiconductor device comprising a chip region and an outer region located outside the chip region,
a gate stacked structure located in the chip area and including a plurality of cell insulating layers and a plurality of gate electrodes that are alternately stacked;
a channel structure extending through the gate stack structure in the chip region;
A key pattern located in the outer area and including at least one pattern portion
Including,
The pattern portion includes an insulating structure including a base portion and a protrusion protruding from the base portion, and a penetrating portion penetrating the insulating structure on at least one side of the protrusion portion. According to paragraph 1,
In the pattern portion, a first edge of the protrusion including a portion adjacent to the through portion has a first step, and a second edge of the protrusion that is not adjacent to the through portion has a second step smaller than the first step. A semiconductor device having a. According to paragraph 2,
The first step corresponds to a step between the upper surface of the protrusion and the lower surface of the penetrating part,
The second step corresponds to a step between the upper surface of the protrusion and the upper surface of the base portion, or a step between the upper surface of the protrusion and the lower surface of the protrusion. According to paragraph 1,
In the pattern section,
The penetrating portion is provided on both sides of the protrusion in one direction, and a first edge having a first step is located on both sides of the protrusion in the one direction,
A semiconductor device wherein a second edge having a second step smaller than the first step is positioned on both sides of the protrusion in a direction intersecting the one direction. According to paragraph 4,
The first edges located on both sides of the protrusion in the one direction extend parallel to each other,
A semiconductor device wherein the second edges located on both sides of the protrusion in the crossing direction extend parallel to each other. According to paragraph 4,
A semiconductor device wherein a length of the protrusion in the one direction is greater than a width of the protrusion in the cross direction. According to paragraph 4,
A semiconductor device wherein the width of the protrusion in the crossing direction is smaller than the width of the penetration part in the crossing direction. According to paragraph 4,
A semiconductor device wherein an edge of the penetration portion adjacent to the protrusion has a straight portion when viewed in plan. According to paragraph 1,
The semiconductor device wherein the insulating structure includes a sacrificial laminate structure including an interlayer insulating layer and a sacrificial insulating layer including different materials, or wherein the insulating structure includes a single insulating structure. According to paragraph 1,
A semiconductor device in which at least a portion of the interior of the penetrating portion is filled with a filling portion containing an insulating material.